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fix: Set LF line endings for assembly files

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MADAO-LUV
2025-06-04 21:29:32 +08:00
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Drivers/STM32H5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h Normal file
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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal.h Normal file
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/**
******************************************************************************
* @file stm32h5xx_hal.h
* @author MCD Application Team
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H5xx_HAL_H
#define __STM32H5xx_HAL_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_conf.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup HAL
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Types HAL Exported Types
* @{
*/
/** @defgroup HAL_TICK_FREQ Tick Frequency
* @{
*/
typedef enum
{
HAL_TICK_FREQ_10HZ = 100U,
HAL_TICK_FREQ_100HZ = 10U,
HAL_TICK_FREQ_1KHZ = 1U,
HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
} HAL_TickFreqTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported variables --------------------------------------------------------*/
/** @defgroup HAL_Exported_Variables HAL Exported Variables
* @{
*/
extern __IO uint32_t uwTick;
extern uint32_t uwTickPrio;
extern HAL_TickFreqTypeDef uwTickFreq;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SBS_Exported_Constants SBS Exported Constants
* @{
*/
/** @defgroup SBS_FPU_Interrupts FPU Interrupts
* @{
*/
#define SBS_IT_FPU_IOC SBS_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */
#define SBS_IT_FPU_DZC SBS_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */
#define SBS_IT_FPU_UFC SBS_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */
#define SBS_IT_FPU_OFC SBS_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */
#define SBS_IT_FPU_IDC SBS_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */
#define SBS_IT_FPU_IXC SBS_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */
/**
* @}
*/
/** @defgroup SBS_BREAK_CONFIG SBS Break Config
* @{
*/
#define SBS_BREAK_FLASH_ECC SBS_CFGR2_ECCL /*!< Enable and lock the FLASH ECC double error with TIM1/8/15/16/17
Break inputs.*/
#define SBS_BREAK_PVD SBS_CFGR2_PVDL /*!< Enable and lock the PVD connection with TIM1/8/15/16/17
Break inputs. */
#define SBS_BREAK_SRAM_ECC SBS_CFGR2_SEL /*!< Enable and lock the SRAM ECC double error signal with
TIM1/8/15/16/17 Break inputs.*/
#define SBS_BREAK_LOCKUP SBS_CFGR2_CLL /*!< Enable and lock the connection of Cortex-M33 LOCKUP (hardfault)
output to TIM1/8/15/16/17 Break inputs.*/
/**
* @}
*/
#if defined(VREFBUF)
/** @defgroup VREFBUF_VoltageScale VREFBUF Voltage Scale
* @{
*/
#define VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */
#define VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */
#define VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */
#define VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */
/**
* @}
*/
/** @defgroup VREFBUF_HighImpedance VREFBUF High Impedance
* @{
*/
#define VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to
Voltage reference buffer output */
#define VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */
/**
* @}
*/
#endif /* VREFBUF */
/** @defgroup SBS_FastModePlus_GPIO Fast-mode Plus on GPIO
* @{
*/
/** @brief Fast-mode Plus driving capability on a specific GPIO
*/
#define SBS_FASTMODEPLUS_PB6 SBS_PMCR_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */
#define SBS_FASTMODEPLUS_PB7 SBS_PMCR_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */
#define SBS_FASTMODEPLUS_PB8 SBS_PMCR_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */
#if defined(SBS_PMCR_PB9_FMP)
#define SBS_FASTMODEPLUS_PB9 SBS_PMCR_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */
#endif /* SBS_PMCR_PB9_FMP */
/**
* @}
*/
#if defined(SBS_PMCR_ETH_SEL_PHY)
/** @defgroup SBS_Ethernet_Config Ethernet Config
* @{
*/
#define SBS_ETH_MII ((uint32_t)0x00000000) /*!< Select the Media Independent Interface (MII) or GMII */
#define SBS_ETH_RMII SBS_PMCR_ETH_SEL_PHY_2 /*!< Select the Reduced Media Independent Interface (RMII) */
#define IS_SBS_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SBS_ETH_MII) || \
((CONFIG) == SBS_ETH_RMII))
/**
* @}
*/
#endif /* SBS_PMCR_ETH_SEL_PHY */
/** @defgroup SBS_Memories_Erase_Flag_Status Memory Erase Flags Status
* @{
*/
#define SBS_MEMORIES_ERASE_FLAG_IPMEE SBS_MESR_IPMEE /*!< Select the Status of End Of Erase for ICACHE
and PKA RAMs */
#define SBS_MEMORIES_ERASE_FLAG_MCLR SBS_MESR_MCLR /*!< Select the Status of Erase after Power-on Reset
(SRAM2, BKPRAM, ICACHE, DCACHE, PKA rams) */
#define IS_SBS_MEMORIES_ERASE_FLAG(FLAG) (((FLAG) == SBS_MEMORIES_ERASE_FLAG_IPMEE) || \
((FLAG) == SBS_MEMORIES_ERASE_FLAG_MCLR))
/**
* @}
*/
/** @defgroup SBS_IOCompenstionCell_Config IOCompenstionCell Config
* @{
*/
#define SBS_VDD_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
#define SBS_VDD_REGISTER_CODE SBS_CCCSR_CS1 /*!< Code from the SBS compensation cell code register */
#define IS_SBS_VDD_CODE_SELECT(SELECT) (((SELECT) == SBS_VDD_CELL_CODE)|| \
((SELECT) == SBS_VDD_REGISTER_CODE))
#define SBS_VDDIO_CELL_CODE ((uint32_t)0x00000000) /*!< Select Code from the cell */
#define SBS_VDDIO_REGISTER_CODE SBS_CCCSR_CS2 /*!< Code from the SBS compensation cell code register */
#define IS_SBS_VDDIO_CODE_SELECT(SELECT) (((SELECT) == SBS_VDDIO_CELL_CODE)|| \
((SELECT) == SBS_VDDIO_REGISTER_CODE))
#define IS_SBS_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))
/**
* @}
*/
#if defined(SBS_EPOCHSELCR_EPOCH_SEL)
/** @defgroup SBS_EPOCH_Selection EPOCH Selection
* @{
*/
#define SBS_EPOCH_SEL_NONSECURE 0x0UL /*!< EPOCH non secure selected */
#define SBS_EPOCH_SEL_SECURE SBS_EPOCHSELCR_EPOCH_SEL_0 /*!< EPOCH secure selected */
#define SBS_EPOCH_SEL_PUFCHECK SBS_EPOCHSELCR_EPOCH_SEL_1 /*!< EPOCH all zeros for PUF integrity check */
#define IS_SBS_EPOCH_SELECTION(SELECT) (((SELECT) == SBS_EPOCH_SEL_SECURE) || \
((SELECT) == SBS_EPOCH_SEL_NONSECURE) || \
((SELECT) == SBS_EPOCH_SEL_PUFCHECK))
/**
* @}
*/
#endif /* SBS_EPOCHSELCR_EPOCH_SEL */
#if defined(SBS_NEXTHDPLCR_NEXTHDPL)
/** @defgroup SBS_NextHDPL_Selection Next HDPL Selection
* @{
*/
#define SBS_OBKHDPL_INCR_0 0x00U /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
#define SBS_OBKHDPL_INCR_1 SBS_NEXTHDPLCR_NEXTHDPL_0 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
#define SBS_OBKHDPL_INCR_2 SBS_NEXTHDPLCR_NEXTHDPL_1 /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
#define SBS_OBKHDPL_INCR_3 SBS_NEXTHDPLCR_NEXTHDPL /*!< Index to add to the current HDPL to point (through OBK-HDPL) to the next secure storage areas */
/**
* @}
*/
#endif /* SBS_NEXTHDPLCR_NEXTHDPL */
/** @defgroup SBS_HDPL_Value HDPL Value
* @{
*/
#define SBS_HDPL_VALUE_0 0x000000B4U /*!< Hide protection level 0 */
#define SBS_HDPL_VALUE_1 0x00000051U /*!< Hide protection level 1 */
#define SBS_HDPL_VALUE_2 0x0000008AU /*!< Hide protection level 2 */
#define SBS_HDPL_VALUE_3 0x0000006FU /*!< Hide protection level 3 */
/**
* @}
*/
#if defined(SBS_DBGCR_DBG_AUTH_SEC)
/** @defgroup SBS_DEBUG_SEC_Value Debug sec Value
* @{
*/
#define SBS_DEBUG_SEC_NSEC 0x000000B4U /*!< Debug opening for secure and non-secure */
#define SBS_DEBUG_NSEC 0x0000003CU /*!< Debug opening for non-secure only */
/**
* @}
*/
#endif /* SBS_DBGCR_DBG_AUTH_SEC */
/** @defgroup SBS_Lock_items SBS Lock items
* @brief SBS items to set lock on
* @{
*/
#define SBS_MPU_NSEC SBS_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or
non-secure only) */
#define SBS_VTOR_NSEC SBS_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or
non-secure only) */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define SBS_SAU (SBS_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */
#define SBS_MPU_SEC (SBS_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only)
*/
#define SBS_VTOR_AIRCR_SEC (SBS_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure
code only) */
#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC|SBS_SAU|SBS_MPU_SEC|SBS_VTOR_AIRCR_SEC) /*!< All */
#else
#define SBS_LOCK_ALL (SBS_MPU_NSEC|SBS_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/** @defgroup SBS_Attributes_items SBS Attributes items
* @brief SBS items to configure secure or non-secure attributes on
* @{
*/
#define SBS_CLK SBS_SECCFGR_SBSSEC /*!< SBS clock control */
#define SBS_CLASSB SBS_SECCFGR_CLASSBSEC /*!< Class B */
#define SBS_FPU SBS_SECCFGR_FPUSEC /*!< FPU */
#define SBS_ALL (SBS_CLK | SBS_CLASSB | SBS_FPU) /*!< All */
/**
* @}
*/
/** @defgroup SBS_attributes SBS attributes
* @brief SBS secure or non-secure attributes
* @{
*/
#define SBS_SEC 0x00000001U /*!< Secure attribute */
#define SBS_NSEC 0x00000000U /*!< Non-secure attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros
* @{
*/
/** @brief Freeze/Unfreeze Peripherals in Debug mode
*/
#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM12_STOP)
#define __HAL_DBGMCU_FREEZE_TIM12() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM12() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM12_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM12_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM13_STOP)
#define __HAL_DBGMCU_FREEZE_TIM13() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM13() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM13_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM13_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_TIM14_STOP)
#define __HAL_DBGMCU_FREEZE_TIM14() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM14() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM14_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_TIM14_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */
#if defined(DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#define __HAL_DBGMCU_FREEZE_I3C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#define __HAL_DBGMCU_UNFREEZE_I3C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I3C1_STOP)
#endif /* DBGMCU_APB1FZR1_DBG_I3C1_STOP */
#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP)
#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP)
#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */
#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP)
#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */
#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP)
#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP)
#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */
#if defined(DBGMCU_APB3FZR_DBG_I2C4_STOP)
#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP)
#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C4_STOP)
#endif /* DBGMCU_APB3FZR_DBG_I2C4_STOP */
#if defined(DBGMCU_APB3FZR_DBG_I3C2_STOP)
#define __HAL_DBGMCU_FREEZE_I3C2() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP)
#define __HAL_DBGMCU_UNFREEZE_I3C2() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I3C2_STOP)
#endif /* DBGMCU_APB3FZR_DBG_I3C2_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM5() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM5() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM5_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM5_STOP */
#if defined(DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
#define __HAL_DBGMCU_FREEZE_LPTIM6() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
#define __HAL_DBGMCU_UNFREEZE_LPTIM6() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM6_STOP)
#endif /* DBGMCU_APB3FZR_DBG_LPTIM6_STOP */
#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP)
#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP)
#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH0_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH1_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH2_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH3_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH4_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH5_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH6_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH7_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH8_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH9_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH10_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA1_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA1_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_CH11_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH0_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH1_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH2_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH3_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH4_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH5_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH6_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH7_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH8_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH9_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH10_STOP */
#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
#define __HAL_DBGMCU_FREEZE_GPDMA2_11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
#define __HAL_DBGMCU_UNFREEZE_GPDMA2_11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP)
#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_CH11_STOP */
/**
* @}
*/
/** @defgroup SBS_Exported_Macros SBS Exported Macros
* @{
*/
/** @brief Floating Point Unit interrupt enable/disable macros
* @param __INTERRUPT__: This parameter can be a value of @ref SBS_FPU_Interrupts
*/
#define __HAL_SBS_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\
SET_BIT(SBS->FPUIMR, (__INTERRUPT__));\
}while(0)
#define __HAL_SBS_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SBS_FPU_INTERRUPT((__INTERRUPT__)));\
CLEAR_BIT(SBS->FPUIMR, (__INTERRUPT__));\
}while(0)
/** @brief SBS Break ECC lock.
* Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SBS_BREAK_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_ECCL)
/** @brief SBS Break Cortex-M33 Lockup lock.
* Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SBS_BREAK_LOCKUP_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_CLL)
/** @brief SBS Break PVD lock.
* Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0]
* in the PWR_CR2 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SBS_BREAK_PVD_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_PVDL)
/** @brief SBS Break SRAM double ECC lock.
* Enable and lock the connection of SRAM double ECC error to TIM1/8/15/16/17 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SBS_BREAK_SRAM_ECC_LOCK() SET_BIT(SBS->CFGR2, SBS_CFGR2_SEL)
/** @brief Fast-mode Plus driving capability enable/disable macros
* @param __FASTMODEPLUS__: This parameter can be a value of :
* @arg @ref SBS_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6
* @arg @ref SBS_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7
* @arg @ref SBS_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8
* @arg @ref SBS_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9
*/
#define __HAL_SBS_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\
SET_BIT(SBS->PMCR, (__FASTMODEPLUS__));\
}while(0)
#define __HAL_SBS_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SBS_FASTMODEPLUS((__FASTMODEPLUS__)));\
CLEAR_BIT(SBS->PMCR, (__FASTMODEPLUS__));\
}while(0)
/** @brief Check SBS Memories Erase Status Flags.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs
* @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM,
* ICACHE, DCACHE, PKA RAMs)
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_SBS_GET_MEMORIES_ERASE_STATUS(__FLAG__) ((((SBS->MESR) & (__FLAG__))!= 0) ? 1 : 0)
/** @brief Clear SBS Memories Erase Status Flags.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref SBS_MEMORIES_ERASE_FLAG_IPMEE Status of End Of Erase for ICACHE and PKA RAMs
* @arg @ref SBS_MEMORIES_ERASE_FLAG_MCLR Status of Erase after Power-on Reset ((SRAM2, BKPRAM,
* ICACHE, DCACHE, PKA RAMs)
*/
#define __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS(__FLAG__) do {assert_param(IS_SBS_MEMORIES_ERASE_FLAG((__FLAG__)));\
WRITE_REG(SBS->MESR, (__FLAG__));\
}while(0)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup SBS_Private_Macros SBS Private Macros
* @{
*/
#define IS_SBS_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SBS_IT_FPU_IOC) == SBS_IT_FPU_IOC) || \
(((__INTERRUPT__) & SBS_IT_FPU_DZC) == SBS_IT_FPU_DZC) || \
(((__INTERRUPT__) & SBS_IT_FPU_UFC) == SBS_IT_FPU_UFC) || \
(((__INTERRUPT__) & SBS_IT_FPU_OFC) == SBS_IT_FPU_OFC) || \
(((__INTERRUPT__) & SBS_IT_FPU_IDC) == SBS_IT_FPU_IDC) || \
(((__INTERRUPT__) & SBS_IT_FPU_IXC) == SBS_IT_FPU_IXC))
#define IS_SBS_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SBS_BREAK_FLASH_ECC) || \
((__CONFIG__) == SBS_BREAK_PVD) || \
((__CONFIG__) == SBS_BREAK_SRAM_ECC) || \
((__CONFIG__) == SBS_BREAK_LOCKUP))
#if defined(VREFBUF)
#define IS_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE1) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE2) || \
((__SCALE__) == VREFBUF_VOLTAGE_SCALE3))
#define IS_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_DISABLE) || \
((__VALUE__) == VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif /* VREFBUF*/
#if defined(SBS_FASTMODEPLUS_PB9)
#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \
(((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \
(((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8) || \
(((__PIN__) & SBS_FASTMODEPLUS_PB9) == SBS_FASTMODEPLUS_PB9))
#else
#define IS_SBS_FASTMODEPLUS(__PIN__) ((((__PIN__) & SBS_FASTMODEPLUS_PB6) == SBS_FASTMODEPLUS_PB6) || \
(((__PIN__) & SBS_FASTMODEPLUS_PB7) == SBS_FASTMODEPLUS_PB7) || \
(((__PIN__) & SBS_FASTMODEPLUS_PB8) == SBS_FASTMODEPLUS_PB8))
#endif /* SBS_FASTMODEPLUS_PB9 */
#define IS_SBS_HDPL(__LEVEL__) (((__LEVEL__) == SBS_HDPL_VALUE_0) || ((__LEVEL__) == SBS_HDPL_VALUE_1) || \
((__LEVEL__) == SBS_HDPL_VALUE_2) || ((__LEVEL__) == SBS_HDPL_VALUE_3))
#define IS_SBS_OBKHDPL_SELECTION(__SELECT__) (((__SELECT__) == SBS_OBKHDPL_INCR_0) || \
((__SELECT__) == SBS_OBKHDPL_INCR_1) || \
((__SELECT__) == SBS_OBKHDPL_INCR_2) || \
((__SELECT__) == SBS_OBKHDPL_INCR_3))
#define IS_SBS_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SBS_CLK) == SBS_CLK) || \
(((__ITEM__) & SBS_CLASSB) == SBS_CLASSB) || \
(((__ITEM__) & SBS_FPU) == SBS_FPU) || \
(((__ITEM__) & ~(SBS_ALL)) == 0U))
#define IS_SBS_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SBS_SEC) ||\
((__ATTRIBUTES__) == SBS_NSEC))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \
(((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \
(((__ITEM__) & SBS_SAU) == SBS_SAU) || \
(((__ITEM__) & SBS_MPU_SEC) == SBS_MPU_SEC) || \
(((__ITEM__) & SBS_VTOR_AIRCR_SEC) == SBS_VTOR_AIRCR_SEC) || \
(((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U))
#else
#define IS_SBS_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SBS_MPU_NSEC) == SBS_MPU_NSEC) || \
(((__ITEM__) & SBS_VTOR_NSEC) == SBS_VTOR_NSEC) || \
(((__ITEM__) & ~(SBS_LOCK_ALL)) == 0U))
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/** @defgroup HAL_Private_Macros HAL Private Macros
* @{
*/
#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
((FREQ) == HAL_TICK_FREQ_100HZ) || \
((FREQ) == HAL_TICK_FREQ_1KHZ))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
*/
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
uint32_t HAL_GetTickPrio(void);
HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
uint32_t HAL_GetUIDw0(void);
uint32_t HAL_GetUIDw1(void);
uint32_t HAL_GetUIDw2(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group3
* @{
*/
/* DBGMCU Peripheral Control functions *****************************************/
void HAL_DBGMCU_EnableDBGStopMode(void);
void HAL_DBGMCU_DisableDBGStopMode(void);
void HAL_DBGMCU_EnableDBGStandbyMode(void);
void HAL_DBGMCU_DisableDBGStandbyMode(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group4
* @{
*/
/* VREFBUF Control functions ****************************************************/
#if defined(VREFBUF)
void HAL_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_EnableVREFBUF(void);
void HAL_DisableVREFBUF(void);
#endif /* VREFBUF */
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group5
* @{
*/
/* SBS System Configuration functions *******************************************/
void HAL_SBS_ETHInterfaceSelect(uint32_t SBS_ETHInterface);
void HAL_SBS_EnableVddIO1CompensationCell(void);
void HAL_SBS_DisableVddIO1CompensationCell(void);
void HAL_SBS_EnableVddIO2CompensationCell(void);
void HAL_SBS_DisableVddIO2CompensationCell(void);
void HAL_SBS_VDDCompensationCodeSelect(uint32_t SBS_CompCode);
void HAL_SBS_VDDIOCompensationCodeSelect(uint32_t SBS_CompCode);
uint32_t HAL_SBS_GetVddIO1CompensationCellReadyFlag(void);
uint32_t HAL_SBS_GetVddIO2CompensationCellReadyFlag(void);
void HAL_SBS_VDDCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode);
void HAL_SBS_VDDIOCompensationCodeConfig(uint32_t SBS_PMOSCode, uint32_t SBS_NMOSCode);
uint32_t HAL_SBS_GetNMOSVddCompensationValue(void);
uint32_t HAL_SBS_GetPMOSVddCompensationValue(void);
uint32_t HAL_SBS_GetNMOSVddIO2CompensationValue(void);
uint32_t HAL_SBS_GetPMOSVddIO2CompensationValue(void);
void HAL_SBS_FLASH_EnableECCNMI(void);
void HAL_SBS_FLASH_DisableECCNMI(void);
uint32_t HAL_SBS_FLASH_ECCNMI_IsDisabled(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group6
* @{
*/
/* SBS Boot control functions ***************************************************/
void HAL_SBS_IncrementHDPLValue(void);
uint32_t HAL_SBS_GetHDPLValue(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group7
* @{
*/
/* SBS Hardware secure storage control functions ********************************/
void HAL_SBS_EPOCHSelection(uint32_t Epoch_Selection);
uint32_t HAL_SBS_GetEPOCHSelection(void);
void HAL_SBS_SetOBKHDPL(uint32_t OBKHDPL_Value);
uint32_t HAL_SBS_GetOBKHDPL(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group8
* @{
*/
/* SBS Debug control functions ***************************************************/
void HAL_SBS_OpenAccessPort(void);
void HAL_SBS_OpenDebug(void);
HAL_StatusTypeDef HAL_SBS_ConfigDebugLevel(uint32_t Level);
uint32_t HAL_SBS_GetDebugLevel(void);
void HAL_SBS_LockDebugConfig(void);
void HAL_SBS_ConfigDebugSecurity(uint32_t Security);
uint32_t HAL_SBS_GetDebugSecurity(void);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group9
* @{
*/
/* SBS Lock functions ********************************************/
void HAL_SBS_Lock(uint32_t Item);
HAL_StatusTypeDef HAL_SBS_GetLock(uint32_t *pItem);
/**
* @}
*/
/** @addtogroup HAL_Exported_Functions_Group10
* @{
*/
/* SBS Attributes functions ********************************************/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
void HAL_SBS_ConfigAttributes(uint32_t Item, uint32_t Attributes);
HAL_StatusTypeDef HAL_SBS_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32H5xx_HAL_H */

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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_cortex.h Normal file
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/**
******************************************************************************
* @file stm32h5xx_hal_cortex.h
* @author MCD Application Team
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H5xx_HAL_CORTEX_H
#define __STM32H5xx_HAL_CORTEX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @defgroup CORTEX CORTEX
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Types CORTEX Exported Types
* @{
*/
/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition
* @{
*/
typedef struct
{
uint8_t Enable; /*!< Specifies the status of the region.
This parameter can be a value of @ref CORTEX_MPU_Region_Enable */
uint8_t Number; /*!< Specifies the index of the region to protect.
This parameter can be a value of @ref CORTEX_MPU_Region_Number */
uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */
uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */
uint8_t AttributesIndex; /*!< Specifies the memory attributes index.
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter
can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */
uint8_t DisableExec; /*!< Specifies the instruction access status.
This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */
uint8_t IsShareable; /*!< Specifies the shareability status of the protected region.
This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */
} MPU_Region_InitTypeDef;
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes
* Initialization Structure Definition
* @{
*/
typedef struct
{
uint8_t Number; /*!< Specifies the number of the memory attributes to configure.
This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */
uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter
can be a combination of @ref CORTEX_MPU_Attributes */
} MPU_Attributes_InitTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
* @{
*/
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority,
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority,
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority,
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority,
1 bit for subpriority */
#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority,
0 bit for subpriority */
/**
* @}
*/
/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */
#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */
/**
* @}
*/
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE 1U /*!< Enable region */
#define MPU_REGION_DISABLE 0U /*!< Disable region */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */
#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */
#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */
#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */
#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */
#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */
#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 0U /*!< MPU region number 0 */
#define MPU_REGION_NUMBER1 1U /*!< MPU region number 1 */
#define MPU_REGION_NUMBER2 2U /*!< MPU region number 2 */
#define MPU_REGION_NUMBER3 3U /*!< MPU region number 3 */
#define MPU_REGION_NUMBER4 4U /*!< MPU region number 4 */
#define MPU_REGION_NUMBER5 5U /*!< MPU region number 5 */
#define MPU_REGION_NUMBER6 6U /*!< MPU region number 6 */
#define MPU_REGION_NUMBER7 7U /*!< MPU region number 7 */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define MPU_REGION_NUMBER8 8U /*!< MPU region number 8 */
#define MPU_REGION_NUMBER9 9U /*!< MPU region number 9 */
#define MPU_REGION_NUMBER10 10U /*!< MPU region number 10 */
#define MPU_REGION_NUMBER11 11U /*!< MPU region number 11 */
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number
* @{
*/
#define MPU_ATTRIBUTES_NUMBER0 0U /*!< MPU attribute number 0 */
#define MPU_ATTRIBUTES_NUMBER1 1U /*!< MPU attribute number 1 */
#define MPU_ATTRIBUTES_NUMBER2 2U /*!< MPU attribute number 2 */
#define MPU_ATTRIBUTES_NUMBER3 3U /*!< MPU attribute number 3 */
#define MPU_ATTRIBUTES_NUMBER4 4U /*!< MPU attribute number 4 */
#define MPU_ATTRIBUTES_NUMBER5 5U /*!< MPU attribute number 5 */
#define MPU_ATTRIBUTES_NUMBER6 6U /*!< MPU attribute number 6 */
#define MPU_ATTRIBUTES_NUMBER7 7U /*!< MPU attribute number 7 */
/**
* @}
*/
/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes
* @{
*/
/* Device memory attributes */
#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */
#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */
#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */
#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */
/* Normal memory attributes */
/* To set with INNER_OUTER() macro for both inner/outer cache attributes */
/* Non-cacheable memory attribute */
#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable. */
/* Cacheable memory attributes: combination of cache write policy, transient and allocation */
/* - cache write policy */
#define MPU_WRITE_THROUGH 0x0U /*!< Normal memory, write-through. */
#define MPU_WRITE_BACK 0x4U /*!< Normal memory, write-back. */
/* - transient mode attribute */
#define MPU_TRANSIENT 0x0U /*!< Normal memory, transient. */
#define MPU_NON_TRANSIENT 0x8U /*!< Normal memory, non-transient. */
/* - allocation attribute */
#define MPU_NO_ALLOCATE 0x0U /*!< Normal memory, no allocate. */
#define MPU_W_ALLOCATE 0x1U /*!< Normal memory, write allocate. */
#define MPU_R_ALLOCATE 0x2U /*!< Normal memory, read allocate. */
#define MPU_RW_ALLOCATE 0x3U /*!< Normal memory, read/write allocate. */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
* @{
*/
#define OUTER(__ATTR__) ((__ATTR__) << 4U)
#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
* @{
*/
/** @defgroup CORTEX_Exported_Functions_Group1 NVIC functions
* @brief NVIC functions
* @{
*/
/* NVIC functions *****************************/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
void HAL_NVIC_SystemReset(void);
uint32_t HAL_NVIC_GetPriorityGrouping(void);
void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority,
uint32_t *const pSubPriority);
uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group2 SYSTICK functions
* @brief SYSTICK functions
* @{
*/
/* SYSTICK functions ***********************************************/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
uint32_t HAL_SYSTICK_GetCLKSourceConfig(void);
void HAL_SYSTICK_IRQHandler(void);
void HAL_SYSTICK_Callback(void);
/**
* @}
*/
/** @defgroup CORTEX_Exported_Functions_Group3 MPU functions
* @brief MPU functions
* @{
*/
/* MPU functions ***********************************************/
void HAL_MPU_Enable(uint32_t MPU_Control);
void HAL_MPU_Disable(void);
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* MPU_NS Control functions ***********************************************/
void HAL_MPU_Enable_NS(uint32_t MPU_Control);
void HAL_MPU_Disable_NS(void);
void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber);
void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber);
void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit);
void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit);
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
* @{
*/
#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
((GROUP) == NVIC_PRIORITYGROUP_1) || \
((GROUP) == NVIC_PRIORITYGROUP_2) || \
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS))
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn)
#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \
((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \
((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS))
#endif /* __ARM_FEATURE_CMSE */
#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \
((STATE) == MPU_REGION_DISABLE))
#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \
((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))
#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \
((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \
((STATE) == MPU_ACCESS_NOT_SHAREABLE))
#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \
((TYPE) == MPU_REGION_ALL_RW) || \
((TYPE) == MPU_REGION_PRIV_RO) || \
((TYPE) == MPU_REGION_ALL_RO))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7) || \
((NUMBER) == MPU_REGION_NUMBER8) || \
((NUMBER) == MPU_REGION_NUMBER9) || \
((NUMBER) == MPU_REGION_NUMBER10)|| \
((NUMBER) == MPU_REGION_NUMBER11))
#define IS_MPU_REGION_NUMBER_NS(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#else
#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \
((NUMBER) == MPU_REGION_NUMBER1) || \
((NUMBER) == MPU_REGION_NUMBER2) || \
((NUMBER) == MPU_REGION_NUMBER3) || \
((NUMBER) == MPU_REGION_NUMBER4) || \
((NUMBER) == MPU_REGION_NUMBER5) || \
((NUMBER) == MPU_REGION_NUMBER6) || \
((NUMBER) == MPU_REGION_NUMBER7))
#endif /* __ARM_FEATURE_CMSE */
#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \
((NUMBER) == MPU_ATTRIBUTES_NUMBER7))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H5xx_HAL_CORTEX_H */

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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_def.h Normal file
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/**
**********************************************************************************************************************
* @file stm32h5xx_hal_def.h
* @author MCD Application Team
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef __STM32H5xx_HAL_DEF
#define __STM32H5xx_HAL_DEF
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ----------------------------------------------------------------------------------------------------------*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#include <arm_cmse.h>
#endif /* __ARM_FEATURE_CMSE */
#include "stm32h5xx.h"
#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h>
#include <math.h>
/* Exported types ----------------------------------------------------------------------------------------------------*/
/**
* @brief HAL Status structures definition
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
} HAL_StatusTypeDef;
/**
* @brief HAL Lock structures definition
*/
typedef enum
{
HAL_UNLOCKED = 0x00,
HAL_LOCKED = 0x01
} HAL_LockTypeDef;
/* Exported macros ---------------------------------------------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define ARMCC_MIN_VERSION 6010050
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT))
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U)
#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \
do{ \
(__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
#if !defined(UNUSED)
#define UNUSED(x) ((void)(x))
#endif /* UNUSED */
/** @brief Reset the Handle's State field.
* @param __HANDLE__: specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
* to set to 0 the Handle's "State" field.
* Otherwise, "State" field may have any random value and the first time the function
* HAL_PPP_Init() is called, the low level hardware initialization will be missed
* (i.e. HAL_PPP_MspInit() will not be executed).
* - When there is a need to reconfigure the low level hardware: instead of calling
* HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
* In this later function, when the Handle's "State" field is set to 0, it will execute the function
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#if (USE_RTOS == 1)
/* Reserved for future use */
#error " USE_RTOS should be 0 in the current HAL release "
#else
#define __HAL_LOCK(__HANDLE__) \
do{ \
if((__HANDLE__)->Lock == HAL_LOCKED) \
{ \
return HAL_BUSY; \
} \
else \
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
}while (0)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined ( __GNUC__ )
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
#ifndef __packed
#define __packed __attribute__((__packed__))
#endif /* __packed */
#endif /* __GNUC__ */
#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
#ifndef __weak
#define __weak __WEAK
#endif /* __weak */
#ifndef __packed
#define __packed __PACKED
#endif /* __packed */
#endif
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4"
must be used instead */
#if defined (__GNUC__) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
#ifndef __ALIGN_END
#define __ALIGN_END __ALIGNED(4)
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#define __ALIGN_BEGIN
#endif /* __ALIGN_BEGIN */
#else
#ifndef __ALIGN_END
#define __ALIGN_END
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
#define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
#if defined (__GNUC__) /* GNU Compiler */
#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
#elif defined (__ICCARM__) /* IAR Compiler */
#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)
#define ALIGN_32BYTES(buf) __ALIGNED(32) buf
#elif defined (__CC_ARM) /* ARM Compiler */
#define ALIGN_32BYTES(buf) __align(32) buf
#endif /* __GNUC__ */
/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION))
/* ARM Compiler
RAM functions are defined using the toolchain options.
Functions that are executed in RAM should reside in a separate source module.
Using the 'Options for File' dialog you can simply change the 'Code / Const'
area of a module to a memory space in physical RAM.
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
#define __RAM_FUNC HAL_StatusTypeDef
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
#elif defined ( __GNUC__ )
/* GNU Compiler
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
#endif /* defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) */
/**
* @brief __NOINLINE definition
*/
#if defined ( __CC_ARM ) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ )
/* ARM & GNUCompiler
*/
#define __NOINLINE __attribute__ ( (noinline) )
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
*/
#define __NOINLINE _Pragma("optimize = no_inline")
#endif /* ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= ARMCC_MIN_VERSION)) || defined ( __GNUC__ ) */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* ___STM32H5xx_HAL_DEF */

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/**
**********************************************************************************************************************
* @file stm32h5xx_hal_dma_ex.h
* @author MCD Application Team
* @brief Header file of DMA HAL extension module.
**********************************************************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
**********************************************************************************************************************
*/
/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/
#ifndef STM32H5xx_HAL_DMA_EX_H
#define STM32H5xx_HAL_DMA_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ----------------------------------------------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup DMAEx
* @{
*/
/* Exported types ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Types DMAEx Exported Types
* @brief DMAEx Exported types
* @{
*/
/**
* @brief DMAEx Data Handling Configuration Structure Definition.
*/
typedef struct
{
uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode.
This parameter can be a value of @ref DMAEx_Data_Exchange */
uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode
This parameter can be a value of @ref DMAEx_Data_Alignment */
} DMA_DataHandlingConfTypeDef;
/**
* @brief DMAEx Trigger Configuration Structure Definition.
*/
typedef struct
{
uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode.
This parameter can be a value of @ref DMAEx_Trigger_Mode */
uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity.
This parameter can be a value of @ref DMAEx_Trigger_Polarity */
uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection.
This parameter can be a value of @ref DMAEx_Trigger_Selection */
} DMA_TriggerConfTypeDef;
/**
* @brief DMAEx Repeated Block Configuration Structure Definition.
*/
typedef struct
{
uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block).
This parameter can be a value between 1 and 2048 */
int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset :
This parameter can be a value between -8191 and 8191.
* If source address offset > 0 => Increment the source address by offset from where
the last single/burst transfer ends.
* If source address offset < 0 => Decrement the source address by offset from where
the last single/burst transfer ends.
* If source address offset == 0 => The next single/burst source address starts from
where the last transfer ends */
int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value :
This parameter can be a value between -8191 and 8191.
* If destination address offset > 0 => Increment the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset < 0 => Decrement the destination address by offset
from where the last single/burst transfer ends.
* If destination address offset == 0 => The next single/burst destination address
starts from where the last transfer ends. */
int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block source address offset > 0 => Increment the block source address by offset
from where the last block ends.
* If block source address offset < 0 => Decrement the next block source address by
offset from where the last block ends.
* If block source address offset == 0 => the next block source address starts from
where the last block ends */
int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value :
This parameter can be a value between -65535 and 65535.
* If block destination address offset > 0 => Increment the block destination address
by offset from where the last block ends.
* If block destination address offset < 0 => Decrement the next block destination
address by offset from where the last block ends.
* If block destination address offset == 0 => the next block destination address
starts from where the last block ends */
} DMA_RepeatBlockConfTypeDef;
/**
* @brief DMAEx Queue State Enumeration Definition.
*/
typedef enum
{
HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */
HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */
HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */
} HAL_DMA_QStateTypeDef;
/**
* @brief DMAEx Linked-List Node Configuration Structure Definition.
*/
typedef struct
{
uint32_t NodeType; /*!< Specifies the DMA channel node type.
This parameter can be a value of @ref DMAEx_Node_Type */
DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */
DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */
DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */
DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */
uint32_t SrcAddress; /*!< Specifies the source memory address */
uint32_t DstAddress; /*!< Specifies the destination memory address */
uint32_t DataSize; /*!< Specifies the source data size in bytes */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
uint32_t SrcSecure; /*!< Specifies the source security attribute */
uint32_t DestSecure; /*!< Specifies the destination security attribute */
#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
} DMA_NodeConfTypeDef;
/**
* @brief DMAEx Linked-List Node Structure Definition.
*/
typedef struct
{
uint32_t LinkRegisters[8U]; /*!< Physical Node register description */
uint32_t NodeInfo; /*!< Node information */
} DMA_NodeTypeDef;
/**
* @brief DMAEx Linked-List Queue Structure Definition.
*/
typedef struct __DMA_QListTypeDef
{
DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */
DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */
uint32_t NodeNumber; /*!< Specifies the queue node number */
__IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */
__IO uint32_t ErrorCode; /*!< Specifies the queue error code */
__IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */
} DMA_QListTypeDef;
/**
* @}
*/
/* Exported constants ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants
* @brief DMAEx Exported Constants
* @{
*/
/** @defgroup Queue_Error_Codes Queue Error Codes
* @brief Queue Error Codes
* @{
*/
#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */
#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */
#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */
#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */
#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization
and queue circular types are incompatible */
#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */
#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */
/**
* @}
*/
/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode
* @brief DMAEx LinkedList Mode
* @{
*/
#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */
#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */
/**
* @}
*/
/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment
* @brief DMAEx Data Alignment
* @{
*/
#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width
=> Right aligned padded with 0 up to destination data
width */
#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width
=> Right aligned left Truncated down to destination
data width */
#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width
=> Right Aligned padded with sign extended up to
destination data width */
#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width
=> Left Aligned Right Truncated down to the
destination data width */
#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width
=> Packed at the destination data width */
#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width
=> Unpacked at the destination data width */
/**
* @}
*/
/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange
* @brief DMAEx Data Exchange
* @{
*/
#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */
#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */
#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */
#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity
* @brief DMAEx Trigger Polarity
* @{
*/
#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */
#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */
#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode
* @brief DMAEx Trigger Mode
* @{
*/
#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */
#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */
/**
* @}
*/
/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection
* @brief DMAEx Trigger Selection
* @{
*/
/* GPDMA1 triggers */
#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */
#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */
#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */
#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */
#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */
#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */
#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */
#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */
#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */
#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */
#if defined (TAMP_CR1_TAMP3E)
#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */
#endif /* TAMP_CR1_TAMP3E */
#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */
#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */
#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */
#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */
#define GPDMA1_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */
#define GPDMA1_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */
#define GPDMA1_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */
#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */
#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH0_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH1_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH2_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH3_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH4_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH5_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH6_TCF */
#define GPDMA1_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA2_CH7_TCF */
#define GPDMA1_TRIGGER_TIM2_TRGO 34U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */
#if defined (TIM15)
#define GPDMA1_TRIGGER_TIM15_TRGO 35U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */
#endif /* TIM15 */
#if defined (TIM12)
#define GPDMA1_TRIGGER_TIM12_TRGO 36U /*!< GPDMA1 HW Trigger signal is TIM12_TRGO */
#endif /* TIM12 */
#if defined (LPTIM3)
#define GPDMA1_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH1 */
#define GPDMA1_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA1 HW Trigger signal is LPTIM3_CH2 */
#endif /* LPTIM3 */
#if defined (LPTIM4)
#define GPDMA1_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA1 HW Trigger signal is LPTIM4_AIT */
#endif /* LPTIM4 */
#if defined (LPTIM5)
#define GPDMA1_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH1 */
#define GPDMA1_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA1 HW Trigger signal is LPTIM5_CH2 */
#endif /* LPTIM5 */
#if defined (LPTIM6)
#define GPDMA1_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH1 */
#define GPDMA1_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA1 HW Trigger signal is LPTIM6_CH2 */
#endif /* LPTIM6 */
#if defined (COMP1)
#define GPDMA1_TRIGGER_COMP1_OUT 44U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */
#endif /* COMP1 */
#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
#define GPDMA1_TRIGGER_EVENTOUT 45U /*!< GPDMA1 HW Trigger signal is EVENTOUT */
#endif /* STM32H503xx || STM32H523xx || STM32H533xx */
/* GPDMA2 triggers */
#define GPDMA2_TRIGGER_EXTI_LINE0 0U /*!< GPDMA2 HW Trigger signal is EXTI_LINE0 */
#define GPDMA2_TRIGGER_EXTI_LINE1 1U /*!< GPDMA2 HW Trigger signal is EXTI_LINE1 */
#define GPDMA2_TRIGGER_EXTI_LINE2 2U /*!< GPDMA2 HW Trigger signal is EXTI_LINE2 */
#define GPDMA2_TRIGGER_EXTI_LINE3 3U /*!< GPDMA2 HW Trigger signal is EXTI_LINE3 */
#define GPDMA2_TRIGGER_EXTI_LINE4 4U /*!< GPDMA2 HW Trigger signal is EXTI_LINE4 */
#define GPDMA2_TRIGGER_EXTI_LINE5 5U /*!< GPDMA2 HW Trigger signal is EXTI_LINE5 */
#define GPDMA2_TRIGGER_EXTI_LINE6 6U /*!< GPDMA2 HW Trigger signal is EXTI_LINE6 */
#define GPDMA2_TRIGGER_EXTI_LINE7 7U /*!< GPDMA2 HW Trigger signal is EXTI_LINE7 */
#define GPDMA2_TRIGGER_TAMP_TRG1 8U /*!< GPDMA2 HW Trigger signal is TAMP_TRG1 */
#define GPDMA2_TRIGGER_TAMP_TRG2 9U /*!< GPDMA2 HW Trigger signal is TAMP_TRG2 */
#define GPDMA2_TRIGGER_TAMP_TRG3 10U /*!< GPDMA2 HW Trigger signal is TAMP_TRG3 */
#define GPDMA2_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH1 */
#define GPDMA2_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA2 HW Trigger signal is LPTIM1_CH2 */
#define GPDMA2_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH1 */
#define GPDMA2_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA2 HW Trigger signal is LPTIM2_CH2 */
#define GPDMA2_TRIGGER_RTC_ALRA_TRG 15U /*!< GPDMA2 HW Trigger signal is RTC_ALRA_TRG */
#define GPDMA2_TRIGGER_RTC_ALRB_TRG 16U /*!< GPDMA2 HW Trigger signal is RTC_ALRB_TRG */
#define GPDMA2_TRIGGER_RTC_WUT_TRG 17U /*!< GPDMA2 HW Trigger signal is RTC_WUT_TRG */
#define GPDMA2_TRIGGER_GPDMA1_CH0_TCF 18U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH0_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH1_TCF 19U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH1_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH2_TCF 20U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH2_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH3_TCF 21U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH3_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH4_TCF 22U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH4_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH5_TCF 23U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH5_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH6_TCF 24U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH6_TCF */
#define GPDMA2_TRIGGER_GPDMA1_CH7_TCF 25U /*!< GPDMA2 HW Trigger signal is GPDMA1_CH7_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH0_TCF 26U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH0_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH1_TCF 27U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH1_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH2_TCF 28U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH2_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH3_TCF 29U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH3_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH4_TCF 30U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH4_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH5_TCF 31U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH5_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH6_TCF 32U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH6_TCF */
#define GPDMA2_TRIGGER_GPDMA2_CH7_TCF 33U /*!< GPDMA2 HW Trigger signal is GPDMA2_CH7_TCF */
#define GPDMA2_TRIGGER_TIM2_TRGO 34U /*!< GPDMA2 HW Trigger signal is TIM2_TRGO */
#if defined (TIM15)
#define GPDMA2_TRIGGER_TIM15_TRGO 35U /*!< GPDMA2 HW Trigger signal is TIM15_TRGO */
#endif /* TIM15 */
#if defined (TIM12)
#define GPDMA2_TRIGGER_TIM12_TRGO 36U /*!< GPDMA2 HW Trigger signal is TIM12_TRGO */
#endif /* TIM12 */
#if defined (LPTIM3)
#define GPDMA2_TRIGGER_LPTIM3_CH1 37U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH1 */
#define GPDMA2_TRIGGER_LPTIM3_CH2 38U /*!< GPDMA2 HW Trigger signal is LPTIM3_CH2 */
#endif /* LPTIM3 */
#if defined (LPTIM4)
#define GPDMA2_TRIGGER_LPTIM4_AIT 39U /*!< GPDMA2 HW Trigger signal is LPTIM4_AIT */
#endif /* LPTIM4 */
#if defined (LPTIM5)
#define GPDMA2_TRIGGER_LPTIM5_CH1 40U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH1 */
#define GPDMA2_TRIGGER_LPTIM5_CH2 41U /*!< GPDMA2 HW Trigger signal is LPTIM5_CH2 */
#endif /* LPTIM5 */
#if defined (LPTIM6)
#define GPDMA2_TRIGGER_LPTIM6_CH1 42U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH1 */
#define GPDMA2_TRIGGER_LPTIM6_CH2 43U /*!< GPDMA2 HW Trigger signal is LPTIM6_CH2 */
#endif /* LPTIM6 */
#if defined (COMP1)
#define GPDMA2_TRIGGER_COMP1_OUT 44U /*!< GPDMA2 HW Trigger signal is COMP1_OUT */
#endif /* COMP1 */
#if defined (STM32H503xx) || defined(STM32H523xx) || defined(STM32H533xx)
#define GPDMA2_TRIGGER_EVENTOUT 45U /*!< GPDMA2 HW Trigger signal is EVENTOUT */
#endif /* STM32H503xx || STM32H523xx || STM32H533xx */
/**
* @}
*/
/** @defgroup DMAEx_Node_Type DMAEx Node Type
* @brief DMAEx Node Type
* @{
*/
#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */
#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */
/**
* @}
*/
/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port
* @brief DMAEx Linked-List Allocated Port
* @{
*/
#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */
#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */
/**
* @}
*/
/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode
* @brief DMAEx Link Step Mode
* @{
*/
#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */
#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */
/**
* @}
*/
/**
* @}
*/
/* Exported functions ------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
* @brief DMAEx Exported functions
* @{
*/
/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions
* @brief Linked-List Initialization and De-Initialization Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions
* @brief Linked-List IO Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions
* @brief Linked-List Management Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig,
DMA_NodeTypeDef const *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pPrevNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNode);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pOldNode,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pNewNode);
HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList,
DMA_NodeTypeDef const *const pPrevNode,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList,
DMA_QListTypeDef *const pDestQList);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList,
DMA_NodeTypeDef *const pFirstCircularNode);
HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma,
DMA_QListTypeDef *const pQList);
HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions
* @brief Data Handling, Repeated Block and Trigger Configuration Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma,
DMA_DataHandlingConfTypeDef const *const pConfigDataHandling);
HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma,
DMA_TriggerConfTypeDef const *const pConfigTrigger);
HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma,
DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions
* @brief Suspend and Resume Operation Functions
* @{
*/
HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma);
HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma);
/**
* @}
*/
/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function
* @brief FIFO Status Function
* @{
*/
uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma);
/**
* @}
*/
/**
* @}
*/
/* Private types -----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Types DMAEx Private Types
* @brief DMAEx Private Types
* @{
*/
/**
* @brief DMA Node in Queue Information Structure Definition.
*/
typedef struct
{
uint32_t cllr_offset; /* CLLR register offset */
uint32_t previousnode_addr; /* Previous node address */
uint32_t currentnode_pos; /* Current node position */
uint32_t currentnode_addr; /* Current node address */
uint32_t nextnode_addr; /* Next node address */
} DMA_NodeInQInfoTypeDef;
/**
* @}
*/
/* Private constants -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Constants DMAEx Private Constants
* @brief DMAEx Private Constants
* @{
*/
#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */
#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */
#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */
#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */
#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */
#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */
#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */
#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */
#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */
#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */
#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */
#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */
#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */
#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */
#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */
#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */
#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */
#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */
#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */
#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */
#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */
#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */
#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */
#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */
#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */
#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */
#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */
#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */
/**
* @}
*/
/* Private macros ----------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMAEx Private Macros
* @brief DMAEx Private Macros
* @{
*/
#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \
(((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \
((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \
((ALIGNMENT) == DMA_DATA_PACK))
#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \
(((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U)
#define IS_DMA_REPEAT_COUNT(COUNT) \
(((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos)))
#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \
(((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \
((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX))
#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \
(((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \
((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX))
#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \
(((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U)
#define IS_DMA_LINK_STEP_MODE(MODE) \
(((MODE) == DMA_LSM_FULL_EXECUTION) || \
((MODE) == DMA_LSM_1LINK_EXECUTION))
#define IS_DMA_TRIGGER_MODE(MODE) \
(((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \
((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER))
#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \
(((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \
((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \
((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER))
#define IS_DMA_LINKEDLIST_MODE(MODE) \
(((MODE) == DMA_LINKEDLIST_NORMAL) || \
((MODE) == DMA_LINKEDLIST_CIRCULAR))
#define IS_DMA_TRIGGER_POLARITY(POLARITY) \
(((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \
((POLARITY) == DMA_TRIG_POLARITY_RISING) || \
((POLARITY) == DMA_TRIG_POLARITY_FALLING))
#if defined (I3C2)
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_EVENTOUT)
#else
#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_LPTIM6_CH2)
#endif /* I3C2 */
#define IS_DMA_NODE_TYPE(TYPE) \
(((TYPE) == DMA_GPDMA_LINEAR_NODE) || \
((TYPE) == DMA_GPDMA_2D_NODE))
/**
* @}
*/
/* Private functions -------------------------------------------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions
* @brief DMAEx Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H5xx_HAL_DMA_EX_H */

483
Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_exti.h Normal file
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@@ -0,0 +1,483 @@
/**
******************************************************************************
* @file stm32h5xx_hal_exti.h
* @author MCD Application Team
* @brief Header file of EXTI HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_EXTI_H
#define STM32H5xx_HAL_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @defgroup EXTI EXTI
* @brief EXTI HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Types EXTI Exported Types
* @{
*/
typedef enum
{
HAL_EXTI_COMMON_CB_ID = 0x00U,
HAL_EXTI_RISING_CB_ID = 0x01U,
HAL_EXTI_FALLING_CB_ID = 0x02U,
} EXTI_CallbackIDTypeDef;
/**
* @brief EXTI Handle structure definition
*/
typedef struct
{
uint32_t Line; /*!< Exti line number */
void (* RisingCallback)(void); /*!< Exti rising callback */
void (* FallingCallback)(void); /*!< Exti falling callback */
} EXTI_HandleTypeDef;
/**
* @brief EXTI Configuration structure definition
*/
typedef struct
{
uint32_t Line; /*!< The Exti line to be configured. This parameter
can be a value of @ref EXTI_Line */
uint32_t Mode; /*!< The Exit Mode to be configured for a core.
This parameter can be a combination of @ref EXTI_Mode */
uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter
can be a value of @ref EXTI_Trigger */
uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured.
This parameter is only possible for line 0 to 15. It
can be a value of @ref EXTI_GPIOSel */
} EXTI_ConfigTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Constants EXTI Exported Constants
* @{
*/
/** @defgroup EXTI_Line EXTI Line
* @{
*/
#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U)
#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U)
#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U)
#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U)
#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U)
#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U)
#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U)
#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U)
#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U)
#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U)
#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU)
#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU)
#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU)
#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU)
#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU)
#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU)
#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U)
#define EXTI_LINE_17 (EXTI_DIRECT | EXTI_REG1 | 0x11U)
#if defined(EXTI_IMR1_IM18)
#define EXTI_LINE_18 (EXTI_DIRECT | EXTI_REG1 | 0x12U)
#endif /* EXTI_IMR1_IM18 */
#define EXTI_LINE_19 (EXTI_DIRECT | EXTI_REG1 | 0x13U)
#if defined(EXTI_IMR1_IM20)
#define EXTI_LINE_20 (EXTI_DIRECT | EXTI_REG1 | 0x14U)
#endif /* EXTI_IMR1_IM20 */
#define EXTI_LINE_21 (EXTI_DIRECT | EXTI_REG1 | 0x15U)
#define EXTI_LINE_22 (EXTI_DIRECT | EXTI_REG1 | 0x16U)
#if defined(EXTI_IMR1_IM23)
#define EXTI_LINE_23 (EXTI_DIRECT | EXTI_REG1 | 0x17U)
#endif /* EXTI_IMR1_IM23 */
#define EXTI_LINE_24 (EXTI_DIRECT | EXTI_REG1 | 0x18U)
#define EXTI_LINE_25 (EXTI_DIRECT | EXTI_REG1 | 0x19U)
#define EXTI_LINE_26 (EXTI_DIRECT | EXTI_REG1 | 0x1AU)
#define EXTI_LINE_27 (EXTI_DIRECT | EXTI_REG1 | 0x1BU)
#define EXTI_LINE_28 (EXTI_DIRECT | EXTI_REG1 | 0x1CU)
#define EXTI_LINE_29 (EXTI_DIRECT | EXTI_REG1 | 0x1DU)
#if defined(EXTI_IMR1_IM30)
#define EXTI_LINE_30 (EXTI_DIRECT | EXTI_REG1 | 0x1EU)
#endif /* EXTI_IMR1_IM30 */
#define EXTI_LINE_31 (EXTI_DIRECT | EXTI_REG1 | 0x1FU)
#if defined(EXTI_IMR2_IM32)
#define EXTI_LINE_32 (EXTI_DIRECT | EXTI_REG2 | 0x00U)
#endif /* EXTI_IMR2_IM32 */
#if defined(EXTI_IMR2_IM33)
#define EXTI_LINE_33 (EXTI_DIRECT | EXTI_REG2 | 0x01U)
#endif /* EXTI_IMR2_IM33 */
#if defined(EXTI_IMR2_IM34)
#define EXTI_LINE_34 (EXTI_DIRECT | EXTI_REG2 | 0x02U)
#endif /* EXTI_IMR2_IM34 */
#if defined(EXTI_IMR2_IM35)
#define EXTI_LINE_35 (EXTI_DIRECT | EXTI_REG2 | 0x03U)
#endif /* EXTI_IMR2_IM35 */
#if defined(EXTI_IMR2_IM36)
#define EXTI_LINE_36 (EXTI_DIRECT | EXTI_REG2 | 0x04U)
#endif /* EXTI_IMR2_IM36 */
#define EXTI_LINE_37 (EXTI_DIRECT | EXTI_REG2 | 0x05U)
#define EXTI_LINE_38 (EXTI_DIRECT | EXTI_REG2 | 0x06U)
#define EXTI_LINE_39 (EXTI_DIRECT | EXTI_REG2 | 0x07U)
#define EXTI_LINE_40 (EXTI_DIRECT | EXTI_REG2 | 0x08U)
#define EXTI_LINE_41 (EXTI_DIRECT | EXTI_REG2 | 0x09U)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0AU)
#if defined(EXTI_IMR2_IM43)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0BU)
#endif /* EXTI_IMR2_IM43 */
#if defined(EXTI_IMR2_IM44)
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0CU)
#endif /* EXTI_IMR2_IM44 */
#if defined(EXTI_IMR2_IM45)
#endif /* EXTI_IMR2_IM45 */
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0DU)
#if defined(ETH)
#define EXTI_LINE_46 (EXTI_CONFIG | EXTI_REG2 | 0x0EU)
#endif /* ETH */
#define EXTI_LINE_47 (EXTI_DIRECT | EXTI_REG2 | 0x0FU)
#if defined(EXTI_IMR2_IM48)
#define EXTI_LINE_48 (EXTI_DIRECT | EXTI_REG2 | 0x10U)
#endif /* EXTI_IMR2_IM48 */
#define EXTI_LINE_49 (EXTI_DIRECT | EXTI_REG2 | 0x11U)
#define EXTI_LINE_50 (EXTI_CONFIG | EXTI_REG2 | 0x12U)
#if defined(EXTI_IMR2_IM51)
#define EXTI_LINE_51 (EXTI_DIRECT | EXTI_REG2 | 0x13U)
#endif /* EXTI_IMR2_IM51 */
#if defined(EXTI_IMR2_IM52)
#define EXTI_LINE_52 (EXTI_DIRECT | EXTI_REG2 | 0x14U)
#endif /* EXTI_IMR2_IM52 */
#define EXTI_LINE_53 (EXTI_CONFIG | EXTI_REG2 | 0x15U)
#if defined(EXTI_IMR2_IM54)
#define EXTI_LINE_54 (EXTI_DIRECT | EXTI_REG2 | 0x16U)
#endif /* EXTI_IMR2_IM54 */
#if defined(EXTI_IMR2_IM55)
#define EXTI_LINE_55 (EXTI_DIRECT | EXTI_REG2 | 0x17U)
#endif /* EXTI_IMR2_IM55 */
#if defined(EXTI_IMR2_IM56)
#define EXTI_LINE_56 (EXTI_DIRECT | EXTI_REG2 | 0x18U)
#endif /* EXTI_IMR2_IM56 */
#if defined(EXTI_IMR2_IM57)
#define EXTI_LINE_57 (EXTI_DIRECT | EXTI_REG2 | 0x19U)
#endif /* EXTI_IMR2_IM57 */
#if defined(EXTI_IMR2_IM58)
#if defined(I3C2)
#define EXTI_LINE_58 (EXTI_DIRECT | EXTI_REG2 | 0x1AU)
#endif /* I3C2 */
#endif /* EXTI_IMR2_IM58 */
/**
* @}
*/
/** @defgroup EXTI_Mode EXTI Mode
* @{
*/
#define EXTI_MODE_NONE 0x00000000U
#define EXTI_MODE_INTERRUPT 0x00000001U
#define EXTI_MODE_EVENT 0x00000002U
/**
* @}
*/
/** @defgroup EXTI_Trigger EXTI Trigger
* @{
*/
#define EXTI_TRIGGER_NONE 0x00000000U
#define EXTI_TRIGGER_RISING 0x00000001U
#define EXTI_TRIGGER_FALLING 0x00000002U
#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @}
*/
/** @defgroup EXTI_GPIOSel EXTI GPIOSel
* @brief
* @{
*/
#define EXTI_GPIOA 0x00000000U
#define EXTI_GPIOB 0x00000001U
#define EXTI_GPIOC 0x00000002U
#define EXTI_GPIOD 0x00000003U
#if defined(GPIOE)
#define EXTI_GPIOE 0x00000004U
#endif /* GPIOE */
#if defined(GPIOF)
#define EXTI_GPIOF 0x00000005U
#endif /* GPIOF */
#if defined(GPIOG)
#define EXTI_GPIOG 0x00000006U
#endif /* GPIOG */
#define EXTI_GPIOH 0x00000007U
#if defined(GPIOI)
#define EXTI_GPIOI 0x00000008U
#endif /* GPIOI */
/**
* @}
*/
/** @defgroup EXTI_Line_attributes EXTI line attributes
* @brief EXTI line secure or non-secure and privileged or non-privileged attributes
* @note secure and non-secure attributes are only available from secure state when the system
* implement the security (TZEN=1)
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/*!< Secure line attribute */
#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U)
/*!< Non-secure line attribute */
#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U)
#endif /* __ARM_FEATURE_CMSE */
/*!< Privileged line attribute */
#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U)
/*!< Non-privileged line attribute */
#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U)
/**
* @}
*/
/** @defgroup EXTI_Security_Privilege_Configuration EXTI Security Privilege Configuration
* @brief EXTI security and privilege configurations
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Security and privilege configuration open, can be modified */
#define EXTI_ATTRIBUTES_UNLOCKED 0x00000000U
/* Security and privilege configuration locked, can no longer be modified */
#define EXTI_ATTRIBUTES_LOCKED 0x00000001U
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup EXTI_Exported_Macros EXTI Exported Macros
* @{
*/
/**
* @}
*/
/* Private constants --------------------------------------------------------*/
/** @defgroup EXTI_Private_Constants EXTI Private Constants
* @{
*/
/**
* @brief EXTI Line property definition
*/
#define EXTI_PROPERTY_SHIFT 24U
#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT)
#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT)
#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)
#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT)
#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)
/**
* @brief EXTI Register and bit usage
*/
#define EXTI_REG_SHIFT 16U
#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT)
#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT)
#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2)
#define EXTI_PIN_MASK 0x0000001FU
/**
* @brief EXTI Mask for interrupt & event mode
*/
#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)
/**
* @brief EXTI Mask for trigger possibilities
*/
#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)
/**
* @brief EXTI Line number
*/
#if defined(EXTI_IMR2_IM58)
#define EXTI_LINE_NB 59U
#elif defined(EXTI_IMR2_IM57)
#define EXTI_LINE_NB 58U
#else
#define EXTI_LINE_NB 54U
#endif /* EXTI_IMR2_IM58 */
/**
* @brief EXTI Mask for secure & privilege attributes
*/
#define EXTI_LINE_ATTR_SEC_MASK 0x100U
#define EXTI_LINE_ATTR_PRIV_MASK 0x200U
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup EXTI_Private_Macros EXTI Private Macros
* @{
*/
#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \
EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \
&&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \
(((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \
(((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \
(((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U))))
#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \
(((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U))
#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U)
#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \
((__EXTI_LINE__) == EXTI_TRIGGER_FALLING))
#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U)
#if defined(GPIOI)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH) || \
((__PORT__) == EXTI_GPIOI))
#elif defined(GPIOE)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOF) || \
((__PORT__) == EXTI_GPIOG) || \
((__PORT__) == EXTI_GPIOH))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOH))
#endif /* GPIOI */
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U)
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \
(((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \
(((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
(((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \
EXTI_LINE_NPRIV)) == 0U))
#else
#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \
(((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \
(((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U))
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup EXTI_Exported_Functions EXTI Exported Functions
* @brief EXTI Exported Functions
* @{
*/
/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions
* @brief Configuration functions
* @{
*/
/* Configuration functions ****************************************************/
HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);
HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti);
HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID,
void (*pPendingCbfn)(void));
HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);
/**
* @}
*/
/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti);
uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge);
void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti);
/**
* @}
*/
/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions
* @{
*/
/* EXTI line attributes management functions **********************************/
void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes);
HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes);
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
HAL_StatusTypeDef HAL_EXTI_LockConfigAttributes(void);
HAL_StatusTypeDef HAL_EXTI_GetLockConfigAttributes(uint32_t *const pLockState);
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_EXTI_H */

823
Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_flash.h Normal file
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@@ -0,0 +1,823 @@
/**
******************************************************************************
* @file stm32h5xx_hal_flash.h
* @author MCD Application Team
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_FLASH_H
#define STM32H5xx_HAL_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup FLASH
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Types FLASH Exported Types
* @{
*/
/**
* @brief FLASH handle Structure definition
*/
typedef struct
{
HAL_LockTypeDef Lock; /*!< FLASH locking object */
uint32_t ErrorCode; /*!< FLASH error code */
uint32_t ProcedureOnGoing; /*!< Internal variable to indicate which procedure is ongoing or not
in IT context */
uint32_t Address; /*!< Internal variable to save address selected for program */
uint32_t Bank; /*!< Internal variable to save current bank selected during erase in
IT context */
uint32_t Sector; /*!< Internal variable to define the current sector which is erasing */
uint32_t NbSectorsToErase; /*!< Internal variable to save the remaining sectors to erase in
IT context */
} FLASH_ProcessTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
* @{
*/
/** @defgroup FLASH_Flag_definition FLASH Flag definition
* @brief Flag definition
* @{
*/
#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
#define FLASH_FLAG_WBNE FLASH_SR_WBNE /*!< FLASH Write Buffer Not Empty flag */
#define FLASH_FLAG_DBNE FLASH_SR_DBNE /*!< FLASH data Buffer Not Empty flag */
#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End Of operation flag */
#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write Protection Error flag */
#define FLASH_FLAG_PGSERR FLASH_SR_PGSERR /*!< FLASH Program Sequence Error flag */
#define FLASH_FLAG_STRBERR FLASH_SR_STRBERR /*!< FLASH Strobe Error flag */
#define FLASH_FLAG_INCERR FLASH_SR_INCERR /*!< FLASH Inconsistency Error flag */
#if defined (FLASH_SR_OBKERR)
#define FLASH_FLAG_OBKERR FLASH_SR_OBKERR /*!< FLASH OBK Error flag */
#define FLASH_FLAG_OBKWERR FLASH_SR_OBKWERR /*!< FLASH OBK Write Error flag */
#endif /* FLASH_SR_OBKERR */
#define FLASH_FLAG_OPTCHANGEERR FLASH_SR_OPTCHANGEERR /*!< FLASH Option Byte change Error flag */
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC Correction flag */
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC Detection flag */
#if defined (FLASH_SR_OBKERR)
#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \
FLASH_SR_STRBERR | FLASH_SR_INCERR | \
FLASH_SR_OBKERR | FLASH_SR_OBKWERR | \
FLASH_SR_OPTCHANGEERR)
#else
#define FLASH_FLAG_SR_ERRORS (FLASH_SR_WRPERR | FLASH_SR_PGSERR | \
FLASH_SR_STRBERR | FLASH_SR_INCERR | \
FLASH_SR_OPTCHANGEERR)
#endif /* FLASH_SR_OBKERR */
#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) /*!< All FLASH error flags */
/**
* @}
*/
/** @defgroup FLASH_Interrupt_definition FLASH Interrupts definition
* @brief FLASH Interrupt definition
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation interrupt enable */
#define FLASH_IT_WRPERR FLASH_CR_WRPERRIE /*!< Write Protection Error interrupt enable */
#define FLASH_IT_PGSERR FLASH_CR_PGSERRIE /*!< Program Sequence Error interrupt enable */
#define FLASH_IT_STRBERR FLASH_CR_STRBERRIE /*!< Strobe Error interrupt enable */
#define FLASH_IT_INCERR FLASH_CR_INCERRIE /*!< Inconsistency Error interrupt enable */
#if defined (FLASH_SR_OBKERR)
#define FLASH_IT_OBKERR FLASH_CR_OBKERRIE /*!< OBK Error interrupt enable */
#define FLASH_IT_OBKWERR FLASH_CR_OBKWERRIE /*!< OBK Write Error interrupt enable */
#endif /* FLASH_SR_OBKERR */
#define FLASH_IT_OPTCHANGEERR FLASH_CR_OPTCHANGEERRIE /*!< Option Byte change Error interrupt enable */
#define FLASH_IT_ECCC FLASH_ECCR_ECCIE /*!< Single ECC Error Correction interrupt enable */
#if defined (FLASH_SR_OBKERR)
#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \
FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
FLASH_IT_INCERR | FLASH_IT_OBKERR | \
FLASH_IT_OBKWERR | FLASH_IT_OPTCHANGEERR | \
FLASH_IT_ECCC) /*!< All Flash interrupt sources */
#else
#define FLASH_IT_ALL (FLASH_IT_EOP | FLASH_IT_WRPERR | \
FLASH_IT_PGSERR | FLASH_IT_STRBERR | \
FLASH_IT_INCERR | FLASH_IT_OPTCHANGEERR | \
FLASH_IT_ECCC) /*!< All Flash interrupt sources */
#endif /* FLASH_SR_OBKERR */
/**
* @}
*/
/** @defgroup FLASH_Error_Code FLASH Error Code
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE 0x00000000U /*!< No error */
#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR /*!< Write Protection Error */
#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR /*!< Program Sequence Error */
#define HAL_FLASH_ERROR_STRB FLASH_FLAG_STRBERR /*!< Strobe Error */
#define HAL_FLASH_ERROR_INC FLASH_FLAG_INCERR /*!< Inconsistency Error */
#if defined (FLASH_SR_OBKERR)
#define HAL_FLASH_ERROR_OBK FLASH_FLAG_OBKERR /*!< OBK Error */
#define HAL_FLASH_ERROR_OBKW FLASH_FLAG_OBKWERR /*!< OBK Write Error */
#endif /* FLASH_SR_OBKERR */
#define HAL_FLASH_ERROR_OB_CHANGE FLASH_FLAG_OPTCHANGEERR /*!< Option Byte Change Error */
#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC /*!< ECC Single Correction Error */
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD /*!< ECC Double Detection Error */
/**
* @}
*/
/** @defgroup FLASH_Type_Program FLASH Program Type
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word
(128-bit) at a specified secure address */
#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_CR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word
(128-bit) at a specified non-secure address */
#if defined (FLASH_SR_OBKERR)
#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word
(128-bit) of OBK to current sector */
#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word
(128-bit) of OBK to alternate sector */
#endif /* FLASH_SR_OBKERR */
#if defined (FLASH_EDATAR_EDATA_EN)
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash
high-cycle data half-word (16-bit)at a specified secure address */
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS (FLASH_CR_PG | FLASH_EDATA_HALFWORD | FLASH_NON_SECURE_MASK) /*!< Program a flash
high-cycle data half-word (16-bit)at a specified non-secure address */
#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash
high-cycle data word (32-bit)at a specified secure address */
#define FLASH_TYPEPROGRAM_WORD_EDATA_NS (FLASH_CR_PG | FLASH_EDATA_WORD | FLASH_NON_SECURE_MASK) /*!< Program a flash
high-cycle data word (32-bit)at a specified non-secure address */
#endif /* FLASH_EDATAR_EDATA_EN */
#else
#define FLASH_TYPEPROGRAM_QUADWORD FLASH_CR_PG /*!< Program a quad-word
(128-bit) at a specified address */
#if defined (FLASH_SR_OBKERR)
#define FLASH_TYPEPROGRAM_QUADWORD_OBK (FLASH_CR_PG | FLASH_OBK) /*!< Program a quad-word
(128-bit) of OBK to current sector */
#define FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT (FLASH_CR_PG | FLASH_OBK | FLASH_OBKCFGR_ALT_SECT) /*!< Program a quad-word
(128-bit) of OBK to alternate sector */
#endif /* FLASH_SR_OBKERR */
#if defined (FLASH_EDATAR_EDATA_EN)
#define FLASH_TYPEPROGRAM_HALFWORD_EDATA (FLASH_CR_PG | FLASH_EDATA_HALFWORD) /*!< Program a flash
high-cycle data half-word (16-bit)at a specified address */
#define FLASH_TYPEPROGRAM_WORD_EDATA (FLASH_CR_PG | FLASH_EDATA_WORD) /*!< Program a flash
high-cycle data half-word (32-bit)at a specified address */
#endif /* FLASH_EDATAR_EDATA_EN */
#endif /* __ARM_FEATURE_CMSE */
#define FLASH_TYPEPROGRAM_HALFWORD_OTP (FLASH_CR_PG | FLASH_OTP | FLASH_NON_SECURE_MASK) /*!< Program an OTP
half-word (16-bit)at a specified address */
/**
* @}
*/
/** @defgroup FLASH_Latency FLASH Latency
* @{
*/
#define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait cycle */
#define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait cycle */
#define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait cycles */
#define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait cycles */
#define FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait cycles */
#define FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH Five wait cycles */
#define FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH Six wait cycles */
#define FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait cycles */
#define FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait cycle */
#define FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH Nine wait cycle */
#define FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH Ten wait cycles */
#define FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH Eleven wait cycles */
#define FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH Twelve wait cycles */
#define FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH Thirteen wait cycles */
#define FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH Fourteen wait cycles */
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen wait cycles */
/**
* @}
*/
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 0x45670123U
#define FLASH_KEY2 0xCDEF89ABU
#define FLASH_OPT_KEY1 0x08192A3BU
#define FLASH_OPT_KEY2 0x4C5D6E7FU
#if defined (FLASH_SR_OBKERR)
#define FLASH_OBK_KEY1 0x192A083BU
#define FLASH_OBK_KEY2 0x6E7F4C5DU
#endif /* FLASH_SR_OBKERR */
/**
* @}
*/
/** @defgroup FLASH_Sectors FLASH Sectors
* @{
*/
#define FLASH_SECTOR_0 0U /*!< Sector Number 0 */
#define FLASH_SECTOR_1 1U /*!< Sector Number 1 */
#define FLASH_SECTOR_2 2U /*!< Sector Number 2 */
#define FLASH_SECTOR_3 3U /*!< Sector Number 3 */
#define FLASH_SECTOR_4 4U /*!< Sector Number 4 */
#define FLASH_SECTOR_5 5U /*!< Sector Number 5 */
#define FLASH_SECTOR_6 6U /*!< Sector Number 6 */
#define FLASH_SECTOR_7 7U /*!< Sector Number 7 */
#if (FLASH_SECTOR_NB >= 32)
#define FLASH_SECTOR_8 8U /*!< Sector Number 8 */
#define FLASH_SECTOR_9 9U /*!< Sector Number 9 */
#define FLASH_SECTOR_10 10U /*!< Sector Number 10 */
#define FLASH_SECTOR_11 11U /*!< Sector Number 11 */
#define FLASH_SECTOR_12 12U /*!< Sector Number 12 */
#define FLASH_SECTOR_13 13U /*!< Sector Number 13 */
#define FLASH_SECTOR_14 14U /*!< Sector Number 14 */
#define FLASH_SECTOR_15 15U /*!< Sector Number 15 */
#define FLASH_SECTOR_16 16U /*!< Sector Number 16 */
#define FLASH_SECTOR_17 17U /*!< Sector Number 17 */
#define FLASH_SECTOR_18 18U /*!< Sector Number 18 */
#define FLASH_SECTOR_19 19U /*!< Sector Number 19 */
#define FLASH_SECTOR_20 20U /*!< Sector Number 20 */
#define FLASH_SECTOR_21 21U /*!< Sector Number 21 */
#define FLASH_SECTOR_22 22U /*!< Sector Number 22 */
#define FLASH_SECTOR_23 23U /*!< Sector Number 23 */
#define FLASH_SECTOR_24 24U /*!< Sector Number 24 */
#define FLASH_SECTOR_25 25U /*!< Sector Number 25 */
#define FLASH_SECTOR_26 26U /*!< Sector Number 26 */
#define FLASH_SECTOR_27 27U /*!< Sector Number 27 */
#define FLASH_SECTOR_28 28U /*!< Sector Number 28 */
#define FLASH_SECTOR_29 29U /*!< Sector Number 29 */
#define FLASH_SECTOR_30 30U /*!< Sector Number 30 */
#define FLASH_SECTOR_31 31U /*!< Sector Number 31 */
#endif /* (FLASH_SECTOR_NB >= 32) */
#if (FLASH_SECTOR_NB >= 128)
#define FLASH_SECTOR_32 32U /*!< Sector Number 32 */
#define FLASH_SECTOR_33 33U /*!< Sector Number 33 */
#define FLASH_SECTOR_34 34U /*!< Sector Number 34 */
#define FLASH_SECTOR_35 35U /*!< Sector Number 35 */
#define FLASH_SECTOR_36 36U /*!< Sector Number 36 */
#define FLASH_SECTOR_37 37U /*!< Sector Number 37 */
#define FLASH_SECTOR_38 38U /*!< Sector Number 38 */
#define FLASH_SECTOR_39 39U /*!< Sector Number 39 */
#define FLASH_SECTOR_40 40U /*!< Sector Number 40 */
#define FLASH_SECTOR_41 41U /*!< Sector Number 41 */
#define FLASH_SECTOR_42 42U /*!< Sector Number 42 */
#define FLASH_SECTOR_43 43U /*!< Sector Number 43 */
#define FLASH_SECTOR_44 44U /*!< Sector Number 44 */
#define FLASH_SECTOR_45 45U /*!< Sector Number 45 */
#define FLASH_SECTOR_46 46U /*!< Sector Number 46 */
#define FLASH_SECTOR_47 47U /*!< Sector Number 47 */
#define FLASH_SECTOR_48 48U /*!< Sector Number 48 */
#define FLASH_SECTOR_49 49U /*!< Sector Number 49 */
#define FLASH_SECTOR_50 50U /*!< Sector Number 50 */
#define FLASH_SECTOR_51 51U /*!< Sector Number 51 */
#define FLASH_SECTOR_52 52U /*!< Sector Number 52 */
#define FLASH_SECTOR_53 53U /*!< Sector Number 53 */
#define FLASH_SECTOR_54 54U /*!< Sector Number 54 */
#define FLASH_SECTOR_55 55U /*!< Sector Number 55 */
#define FLASH_SECTOR_56 56U /*!< Sector Number 56 */
#define FLASH_SECTOR_57 57U /*!< Sector Number 57 */
#define FLASH_SECTOR_58 58U /*!< Sector Number 58 */
#define FLASH_SECTOR_59 59U /*!< Sector Number 59 */
#define FLASH_SECTOR_60 60U /*!< Sector Number 60 */
#define FLASH_SECTOR_61 61U /*!< Sector Number 61 */
#define FLASH_SECTOR_62 62U /*!< Sector Number 62 */
#define FLASH_SECTOR_63 63U /*!< Sector Number 63 */
#define FLASH_SECTOR_64 64U /*!< Sector Number 64 */
#define FLASH_SECTOR_65 65U /*!< Sector Number 65 */
#define FLASH_SECTOR_66 66U /*!< Sector Number 66 */
#define FLASH_SECTOR_67 67U /*!< Sector Number 67 */
#define FLASH_SECTOR_68 68U /*!< Sector Number 68 */
#define FLASH_SECTOR_69 69U /*!< Sector Number 69 */
#define FLASH_SECTOR_70 70U /*!< Sector Number 70 */
#define FLASH_SECTOR_71 71U /*!< Sector Number 71 */
#define FLASH_SECTOR_72 72U /*!< Sector Number 72 */
#define FLASH_SECTOR_73 73U /*!< Sector Number 73 */
#define FLASH_SECTOR_74 74U /*!< Sector Number 74 */
#define FLASH_SECTOR_75 75U /*!< Sector Number 75 */
#define FLASH_SECTOR_76 76U /*!< Sector Number 76 */
#define FLASH_SECTOR_77 77U /*!< Sector Number 77 */
#define FLASH_SECTOR_78 78U /*!< Sector Number 78 */
#define FLASH_SECTOR_79 79U /*!< Sector Number 79 */
#define FLASH_SECTOR_80 80U /*!< Sector Number 80 */
#define FLASH_SECTOR_81 81U /*!< Sector Number 81 */
#define FLASH_SECTOR_82 82U /*!< Sector Number 82 */
#define FLASH_SECTOR_83 83U /*!< Sector Number 83 */
#define FLASH_SECTOR_84 84U /*!< Sector Number 84 */
#define FLASH_SECTOR_85 85U /*!< Sector Number 85 */
#define FLASH_SECTOR_86 86U /*!< Sector Number 86 */
#define FLASH_SECTOR_87 87U /*!< Sector Number 87 */
#define FLASH_SECTOR_88 88U /*!< Sector Number 88 */
#define FLASH_SECTOR_89 89U /*!< Sector Number 89 */
#define FLASH_SECTOR_90 90U /*!< Sector Number 90 */
#define FLASH_SECTOR_91 91U /*!< Sector Number 91 */
#define FLASH_SECTOR_92 92U /*!< Sector Number 92 */
#define FLASH_SECTOR_93 93U /*!< Sector Number 93 */
#define FLASH_SECTOR_94 94U /*!< Sector Number 94 */
#define FLASH_SECTOR_95 95U /*!< Sector Number 95 */
#define FLASH_SECTOR_96 96U /*!< Sector Number 96 */
#define FLASH_SECTOR_97 97U /*!< Sector Number 97 */
#define FLASH_SECTOR_98 98U /*!< Sector Number 98 */
#define FLASH_SECTOR_99 99U /*!< Sector Number 99 */
#define FLASH_SECTOR_100 100U /*!< Sector Number 100 */
#define FLASH_SECTOR_101 101U /*!< Sector Number 101 */
#define FLASH_SECTOR_102 102U /*!< Sector Number 102 */
#define FLASH_SECTOR_103 103U /*!< Sector Number 103 */
#define FLASH_SECTOR_104 104U /*!< Sector Number 104 */
#define FLASH_SECTOR_105 105U /*!< Sector Number 105 */
#define FLASH_SECTOR_106 106U /*!< Sector Number 106 */
#define FLASH_SECTOR_107 107U /*!< Sector Number 107 */
#define FLASH_SECTOR_108 108U /*!< Sector Number 108 */
#define FLASH_SECTOR_109 109U /*!< Sector Number 109 */
#define FLASH_SECTOR_110 110U /*!< Sector Number 110 */
#define FLASH_SECTOR_111 111U /*!< Sector Number 111 */
#define FLASH_SECTOR_112 112U /*!< Sector Number 112 */
#define FLASH_SECTOR_113 113U /*!< Sector Number 113 */
#define FLASH_SECTOR_114 114U /*!< Sector Number 114 */
#define FLASH_SECTOR_115 115U /*!< Sector Number 115 */
#define FLASH_SECTOR_116 116U /*!< Sector Number 116 */
#define FLASH_SECTOR_117 117U /*!< Sector Number 117 */
#define FLASH_SECTOR_118 118U /*!< Sector Number 118 */
#define FLASH_SECTOR_119 119U /*!< Sector Number 119 */
#define FLASH_SECTOR_120 120U /*!< Sector Number 120 */
#define FLASH_SECTOR_121 121U /*!< Sector Number 121 */
#define FLASH_SECTOR_122 122U /*!< Sector Number 122 */
#define FLASH_SECTOR_123 123U /*!< Sector Number 123 */
#define FLASH_SECTOR_124 124U /*!< Sector Number 124 */
#define FLASH_SECTOR_125 125U /*!< Sector Number 125 */
#define FLASH_SECTOR_126 126U /*!< Sector Number 126 */
#define FLASH_SECTOR_127 127U /*!< Sector Number 127 */
#endif /* (FLASH_SECTOR_NB >= 128) */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
*/
/**
* @brief Set the FLASH Latency.
* @param __LATENCY__: FLASH Latency
* This parameter can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
* @arg FLASH_LATENCY_8: FLASH Eight wait states
* @arg FLASH_LATENCY_9: FLASH Nine wait states
* @arg FLASH_LATENCY_10: FLASH Ten wait states
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
* @retval none
*/
#define __HAL_FLASH_SET_LATENCY(__LATENCY__) MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (__LATENCY__))
/**
* @brief Get the FLASH Latency.
* @retval FLASH Latency
* This return value can be one of the following values :
* @arg FLASH_LATENCY_0: FLASH Zero wait state
* @arg FLASH_LATENCY_1: FLASH One wait state
* @arg FLASH_LATENCY_2: FLASH Two wait states
* @arg FLASH_LATENCY_3: FLASH Three wait states
* @arg FLASH_LATENCY_4: FLASH Four wait states
* @arg FLASH_LATENCY_5: FLASH Five wait states
* @arg FLASH_LATENCY_6: FLASH Six wait states
* @arg FLASH_LATENCY_7: FLASH Seven wait states
* @arg FLASH_LATENCY_8: FLASH Eight wait states
* @arg FLASH_LATENCY_9: FLASH Nine wait states
* @arg FLASH_LATENCY_10: FLASH Ten wait states
* @arg FLASH_LATENCY_11: FLASH Eleven wait states
* @arg FLASH_LATENCY_12: FLASH Twelve wait states
* @arg FLASH_LATENCY_13: FLASH Thirteen wait states
* @arg FLASH_LATENCY_14: FLASH Fourteen wait states
* @arg FLASH_LATENCY_15: FLASH Fifteen wait states
*/
#define __HAL_FLASH_GET_LATENCY() READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)
/**
* @brief Enable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP : End of FLASH Operation Interrupt
* @arg FLASH_IT_WRPERR : Write Protection Error Interrupt
* @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt
* @arg FLASH_IT_STRBERR : Strobe Error Interrupt
* @arg FLASH_IT_INCERR : Inconsistency Error Interrupt
* @arg FLASH_IT_OBKERR : OBK Error Interrupt
* @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt
* @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt
* @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt
* @retval none
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Enable secure FLASH interrupts from the secure world */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \
{ SET_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
{ SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~(FLASH_IT_ECCC | \
FLASH_IT_OPTCHANGEERR)))); }\
} while(0)
/* Enable non-secure FLASH interrupts from the secure world */
#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
{ SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
} while(0)
#else
/* Enable non-secure FLASH interrupts from the non-secure world */
#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
{ SET_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
{ SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
} while(0)
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Disable the specified FLASH interrupt.
* @param __INTERRUPT__ : FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP : End of FLASH Operation Interrupt
* @arg FLASH_IT_WRPERR : Write Protection Error Interrupt
* @arg FLASH_IT_PGSERR : Program Sequence Error Interrupt
* @arg FLASH_IT_STRBERR : Strobe Error Interrupt
* @arg FLASH_IT_INCERR : Inconsistency Error Interrupt
* @arg FLASH_IT_OBKERR : OBK Error Interrupt
* @arg FLASH_IT_OBKWERR : OBK Write Error Interrupt
* @arg FLASH_IT_OPTCHANGEERR : Option Byte Change Error Interrupt
* @arg FLASH_IT_ECCC : Single ECC Error Correction Interrupt
* @retval none
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Disable secure FLASH interrupts from the secure world */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \
{ CLEAR_BIT(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & FLASH_IT_OPTCHANGEERR) != 0U) \
{ CLEAR_BIT(FLASH->NSCR, FLASH_IT_OPTCHANGEERR); } \
if(((__INTERRUPT__) & (~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR))) \
!= 0U){ CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & \
(~(FLASH_IT_ECCC | FLASH_IT_OPTCHANGEERR)))); }\
} while(0)
/* Disable non-secure FLASH interrupts from the secure world */
#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \
(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \
{ CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));\
} \
} while(0)
#else
/* Disable non-secure FLASH interrupts from the non-secure world */
#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) { CLEAR_BIT \
(FLASH->ECCCORR, FLASH_IT_ECCC); } \
if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) { CLEAR_BIT \
(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); } \
} while(0)
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Checks whether the specified FLASH flag is set or not.
* @param __FLAG__: specifies the FLASH flag to check.
* This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag
* @arg FLASH_FLAG_EOP : End Of Operation flag
* @arg FLASH_FLAG_WRPERR : Write Protection Error flag
* @arg FLASH_FLAG_PGSERR : Program Sequence Error flag
* @arg FLASH_FLAG_STRBERR : Strobe Error flag
* @arg FLASH_FLAG_INCERR : Inconsistency Error flag
* @arg FLASH_FLAG_OBKERR : OBK Error flag
* @arg FLASH_FLAG_OBKWERR : OBK Write Error flag
* @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag
* @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag
* @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag
* @retval The new state of FLASH_FLAG (SET or RESET).
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Get secure FLASH flags from the secure world */
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
((((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR)) != 0U) ? \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__))))
/* Get non-secure FLASH flags from the secure world */
#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))))
#else
/* Get non-secure FLASH flags from the non-secure world */
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC)) != 0U) ? \
(READ_BIT(FLASH->ECCCORR, (__FLAG__)) == (__FLAG__)) : \
(((__FLAG__) & (FLASH_FLAG_ECCD)) != 0U) ? \
(READ_BIT(FLASH->ECCDETR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)))
#endif /* __ARM_FEATURE_CMSE */
/**
* @brief Clear the specified FLASH flag.
* @param __FLAG__: specifies the FLASH flags to clear.
* This parameter can be one of the following values :
* @arg FLASH_FLAG_BSY : FLASH Busy flag
* @arg FLASH_FLAG_WBNE : Write Buffer Not Empty flag
* @arg FLASH_FLAG_EOP : End Of Operation flag
* @arg FLASH_FLAG_WRPERR : Write Protection Error flag
* @arg FLASH_FLAG_PGSERR : Program Sequence Error flag
* @arg FLASH_FLAG_STRBERR : Strobe Error flag
* @arg FLASH_FLAG_INCERR : Inconsistency Error flag
* @arg FLASH_FLAG_OBKERR : OBK Error flag
* @arg FLASH_FLAG_OBKWERR : OBK Write Error flag
* @arg FLASH_FLAG_OPTCHANGEERR : Option Byte Change Error flag
* @arg FLASH_FLAG_ECCC : Single ECC Error Correction flag
* @arg FLASH_FLAG_ECCD : Double Detection ECC Error flag
* @arg FLASH_FLAG_ALL_ERRORS: All errors flags
* @retval none
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* Clear secure FLASH flags from the secure world */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
((__FLAG__) & FLASH_FLAG_ECCC)); } \
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
((__FLAG__) & FLASH_FLAG_ECCD)); } \
if(((__FLAG__) & FLASH_FLAG_OPTCHANGEERR) != 0U) { SET_BIT \
(FLASH->NSCCR, ((__FLAG__) & (FLASH_FLAG_OPTCHANGEERR))); } \
if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \
FLASH_FLAG_OPTCHANGEERR)) != 0U) { WRITE_REG(FLASH->SECCCR, \
((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \
FLASH_FLAG_OPTCHANGEERR))); } \
} while(0)
/* Clear non-secure FLASH flags from the secure world */
#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
((__FLAG__) & FLASH_FLAG_ECCC)); } \
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
((__FLAG__) & FLASH_FLAG_ECCD)); } \
if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \
(FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \
} while(0)
#else
/* Clear non-secure FLASH flags from the non-secure world */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCC) != 0U) { SET_BIT(FLASH->ECCCORR,\
((__FLAG__) & FLASH_FLAG_ECCC)); } \
if(((__FLAG__) & FLASH_FLAG_ECCD) != 0U) { SET_BIT(FLASH->ECCDETR,\
((__FLAG__) & FLASH_FLAG_ECCD)); } \
if(((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG \
(FLASH->NSCCR, ((__FLAG__) & (~FLASH_FLAG_ECCR_ERRORS))); } \
} while(0)
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Include FLASH HAL Extension module */
#include "stm32h5xx_hal_flash_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASH_Exported_Functions
* @{
*/
/** @addtogroup FLASH_Exported_Functions_Group1
* @{
*/
/* Program operation functions */
HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);
/* FLASH IRQ handler method */
void HAL_FLASH_IRQHandler(void);
/* Callbacks in non blocking modes */
void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group2
* @{
*/
/* Peripheral Control functions */
HAL_StatusTypeDef HAL_FLASH_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_Lock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);
/* Option bytes control */
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);
/**
* @}
*/
/** @addtogroup FLASH_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions */
uint32_t HAL_FLASH_GetError(void);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Variables FLASH Private Variables
* @{
*/
extern FLASH_ProcessTypeDef pFlash;
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{
*/
#define FLASH_TIMEOUT_VALUE 1000U /*!< 1 s */
#if defined (FLASH_SR_OBKERR)
#define FLASH_OBK 0x10000000U
#endif /* FLASH_SR_OBKERR */
#define FLASH_OTP 0x20000000U
#if defined (FLASH_EDATAR_EDATA_EN)
#define FLASH_EDATA_HALFWORD 0x40000000U
#define FLASH_EDATA_WORD 0x60000000U
#endif /* FLASH_EDATAR_EDATA_EN */
#define FLASH_NON_SECURE_MASK 0x80000000U
#define FLASH_EDATA_SECTOR_NB 8U /*!< Maximum number of FLASH high-cycle data sectors */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASH_Private_Macros FLASH Private Macros
* @{
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN)
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA_NS) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA_NS) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT))
#else
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP))
#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */
#else
#if defined (FLASH_SR_OBKERR) && defined (FLASH_EDATAR_EDATA_EN)
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_EDATA) || \
((VALUE) == FLASH_TYPEPROGRAM_WORD_EDATA) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK) || \
((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_OBK_ALT))
#else
#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \
((VALUE) == FLASH_TYPEPROGRAM_HALFWORD_OTP))
#endif /* FLASH_SR_OBKERR && FLASH_EDATAR_EDATA_EN */
#endif /* __ARM_FEATURE_CMSE */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \
(((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE))))
#if defined (FLASH_SR_OBKERR)
#define IS_FLASH_OBK_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_OBK_BASE) && \
((ADDRESS) < (FLASH_OBK_BASE+FLASH_OBK_SIZE))) || \
(((ADDRESS) >= FLASH_OBK_BASE_NS) && \
((ADDRESS) < (FLASH_OBK_BASE_NS+FLASH_OBK_SIZE))))
#endif /* FLASH_SR_OBKERR */
#if defined (FLASH_EDATAR_EDATA_EN)
#define IS_FLASH_EDATA_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_EDATA_BASE_S) && \
((ADDRESS) < (FLASH_EDATA_BASE_S+FLASH_EDATA_SIZE))) || \
(((ADDRESS) >= FLASH_EDATA_BASE_NS) && \
((ADDRESS) < (FLASH_EDATA_BASE_NS+FLASH_EDATA_SIZE))))
#endif /* FLASH_EDATAR_EDATA_EN */
#else
#define IS_FLASH_USER_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && \
((ADDRESS) < (FLASH_BASE+FLASH_SIZE)))
#if defined (FLASH_SR_OBKERR)
#define IS_FLASH_OBK_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OBK_BASE) && \
((ADDRESS) < (FLASH_OBK_BASE + FLASH_OBK_SIZE)))
#endif /* FLASH_SR_OBKERR */
#if defined (FLASH_EDATAR_EDATA_EN)
#define IS_FLASH_EDATA_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_EDATA_BASE_NS) && \
((ADDRESS) < (FLASH_EDATA_BASE_NS + FLASH_EDATA_SIZE)))
#endif /* FLASH_EDATAR_EDATA_EN */
#endif /* __ARM_FEATURE_CMSE */
#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE) && \
((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE)))
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2))
#define IS_FLASH_SECTOR(SECTOR) ((SECTOR) < FLASH_SECTOR_NB)
#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || \
((LATENCY) == FLASH_LATENCY_1) || \
((LATENCY) == FLASH_LATENCY_2) || \
((LATENCY) == FLASH_LATENCY_3) || \
((LATENCY) == FLASH_LATENCY_4) || \
((LATENCY) == FLASH_LATENCY_5) || \
((LATENCY) == FLASH_LATENCY_6) || \
((LATENCY) == FLASH_LATENCY_7) || \
((LATENCY) == FLASH_LATENCY_8) || \
((LATENCY) == FLASH_LATENCY_9) || \
((LATENCY) == FLASH_LATENCY_10) || \
((LATENCY) == FLASH_LATENCY_11) || \
((LATENCY) == FLASH_LATENCY_12) || \
((LATENCY) == FLASH_LATENCY_13) || \
((LATENCY) == FLASH_LATENCY_14) || \
((LATENCY) == FLASH_LATENCY_15))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U)
#else
#define IS_FLASH_SECURE_OPERATION() (1U == 0U)
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup FLASH_Private_Functions FLASH Private Functions
* @{
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_FLASH_H */

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/**
******************************************************************************
* @file stm32h5xx_hal_gpio.h
* @author MCD Application Team
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_GPIO_H
#define STM32H5xx_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @defgroup GPIO GPIO
* @brief GPIO HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Types GPIO Exported Types
* @{
*/
/**
* @brief GPIO Init structure definition
*/
typedef struct
{
uint32_t Pin; /*!< Specifies the GPIO pins to be configured.
This parameter can be a value of @ref GPIO_pins */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIO_mode */
uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
This parameter can be a value of @ref GPIO_pull */
uint32_t Speed; /*!< Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIO_speed */
uint32_t Alternate; /*!< Peripheral to be connected to the selected pins
This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
} GPIO_InitTypeDef;
/**
* @brief GPIO Bit SET and Bit RESET enumeration
*/
typedef enum
{
GPIO_PIN_RESET = 0U,
GPIO_PIN_SET
} GPIO_PinState;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
* @{
*/
/** @defgroup GPIO_pins GPIO pins
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_ALL ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_MASK (0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
/** @defgroup GPIO_mode GPIO mode
* @brief GPIO Configuration Mode
* Elements values convention: 0xX0yz00YZ
* - X : GPIO mode or EXTI Mode
* - y : External IT or Event trigger detection
* - z : IO configuration on External IT or Event
* - Y : Output type (Push Pull or Open Drain)
* - Z : IO Direction mode (Input, Output, (Alternate or Analog))
* @{
*/
/*!< Input Floating Mode */
#define GPIO_MODE_INPUT (0x00000000U)
/*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_PP (0x00000001U)
/*!< Output Open Drain Mode */
#define GPIO_MODE_OUTPUT_OD (0x00000011U)
/*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_PP (0x00000002U)
/*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_AF_OD (0x00000012U)
/*!< Analog Mode */
#define GPIO_MODE_ANALOG (0x00000003U)
/*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_RISING (0x10110000U)
/*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_FALLING (0x10210000U)
/*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING (0x10310000U)
/*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_RISING (0x10120000U)
/*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_FALLING (0x10220000U)
/*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U)
/**
* @}
*/
/** @defgroup GPIO_speed GPIO speed
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */
#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */
/**
* @}
*/
/** @defgroup GPIO_pull GPIO pull
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */
/**
* @}
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @defgroup GPIO_attributes GPIO attributes
* @brief GPIO pin secure or non-secure attributes
* @{
*/
#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */
#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */
/**
* @}
*/
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
* @{
*/
/**
* @brief Check whether the specified EXTI line is rising edge asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line rising pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is falling edge asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__))
/**
* @brief Clear the EXTI's line falling pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line is asserted or not.
* @param __EXTI_LINE__: specifies the EXTI line to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \
__HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__))
/**
* @brief Clear the EXTI's line pending bits.
* @param __EXTI_LINE__: specifies the EXTI lines to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \
do { \
__HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \
} while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line(s).
* @param __EXTI_LINE__: specifies the EXTI line to set.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__))
/**
* @brief Check whether the specified EXTI line flag is set or not.
* @param __EXTI_LINE__ specifies the EXTI line flag to check.
* This parameter can be GPIO_PIN_x where x can be(0..15)
* @retval The new state of __EXTI_LINE__ (SET or RESET).
*/
#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__)
/**
* @brief Clear the EXTI line pending flags.
* @param __EXTI_LINE__ specifies the EXTI lines flags to clear.
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
* @retval None
*/
#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__)
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup GPIO_Private_Macros GPIO Private Macros
* @{
*/
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
(((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\
((__PIN__) == GPIO_PIN_1) ||\
((__PIN__) == GPIO_PIN_2) ||\
((__PIN__) == GPIO_PIN_3) ||\
((__PIN__) == GPIO_PIN_4) ||\
((__PIN__) == GPIO_PIN_5) ||\
((__PIN__) == GPIO_PIN_6) ||\
((__PIN__) == GPIO_PIN_7) ||\
((__PIN__) == GPIO_PIN_8) ||\
((__PIN__) == GPIO_PIN_9) ||\
((__PIN__) == GPIO_PIN_10) ||\
((__PIN__) == GPIO_PIN_11) ||\
((__PIN__) == GPIO_PIN_12) ||\
((__PIN__) == GPIO_PIN_13) ||\
((__PIN__) == GPIO_PIN_14) ||\
((__PIN__) == GPIO_PIN_15))
#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \
(((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u)
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\
((__MODE__) == GPIO_MODE_AF_PP) ||\
((__MODE__) == GPIO_MODE_AF_OD) ||\
((__MODE__) == GPIO_MODE_IT_RISING) ||\
((__MODE__) == GPIO_MODE_IT_FALLING) ||\
((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING) ||\
((__MODE__) == GPIO_MODE_EVT_FALLING) ||\
((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\
((__MODE__) == GPIO_MODE_ANALOG))
#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\
((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\
((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\
((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH))
#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\
((__PULL__) == GPIO_PULLUP) || \
((__PULL__) == GPIO_PULLDOWN))
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\
((__ATTRIBUTES__) == GPIO_PIN_NSEC))
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Include GPIO HAL Extended module */
#include "stm32h5xx_hal_gpio_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup GPIO_Exported_Functions GPIO Exported Functions
* @brief GPIO Exported Functions
* @{
*/
/** @addtogroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init);
void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin);
/**
* @}
*/
/** @addtogroup GPIO_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
* @{
*/
/* IO operation functions *****************************************************/
GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet);
void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin);
void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin);
/**
* @}
*/
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/** @addtogroup GPIO_Exported_Functions_Group3 IO attributes management functions
* @{
*/
/* IO attributes management functions *****************************************/
void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes);
HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin,
uint32_t *pPinAttributes);
/**
* @}
*/
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_GPIO_H */

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/**
******************************************************************************
* @file stm32h5xx_hal_gpio_ex.h
* @author MCD Application Team
* @brief Header file of GPIO HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_GPIO_EX_H
#define STM32H5xx_HAL_GPIO_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @defgroup GPIOEx GPIOEx
* @brief GPIO Extended HAL module driver
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
* @{
*/
/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection
* @{
*/
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#if defined(TIM16)
#define GPIO_AF1_TIM16 ((uint8_t)0x01) /* TIM16 Alternate Function mapping */
#endif /* TIM16 */
#if defined(TIM17)
#define GPIO_AF1_TIM17 ((uint8_t)0x01) /* TIM17 Alternate Function mapping */
#endif /* TIM17 */
#if !defined(STM32H503xx)
#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */
#endif /* STM32H503xx */
/**
* @brief AF 2 selection
*/
#if defined(STM32H503xx)
#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */
#endif /* STM32H503xx */
#if defined(LPTIM3)
#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */
#endif /* LPTIM3 */
#if defined(SAI1)
#define GPIO_AF2_SAI1 ((uint8_t)0x02) /* SAI1 Alternate Function mapping */
#endif /* SAI1 */
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#if defined(TIM4)
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#endif /* TIM4 */
#if defined(TIM5)
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#endif /* TIM5 */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF2_TIM8 ((uint8_t)0x02) /* TIM8 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
#if defined(TIM12)
#define GPIO_AF2_TIM12 ((uint8_t)0x02) /* TIM12 Alternate Function mapping */
#endif /* TIM12 */
#if defined(TIM15)
#define GPIO_AF2_TIM15 ((uint8_t)0x02) /* TIM15 Alternate Function mapping */
#endif /* TIM15 */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_I3C1 ((uint8_t)0x03) /* I3C1 Alternate Function mapping */
#if defined(I3C2)
#define GPIO_AF3_I3C2 ((uint8_t)0x03) /* I3C2 Alternate Function mapping */
#endif /* I3C2 */
#define GPIO_AF3_LPTIM2 ((uint8_t)0x03) /* LPTIM2 Alternate Function mapping */
#if defined(LPTIM3)
#define GPIO_AF3_LPTIM3 ((uint8_t)0x03) /* LPTIM3 Alternate Function mapping */
#endif /* LPTIM3 */
#define GPIO_AF3_LPUART1 ((uint8_t)0x03) /* LPUART1 Alternate Function mapping */
#if defined(OCTOSPI1)
#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */
#endif /* OCTOSPI1 */
#if !defined(STM32H503xx)
#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */
#endif /* STM32H503xx */
#if defined(TIM8)
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#endif /* TIM8 */
/**
* @brief AF 4 selection
*/
#if defined(CEC)
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#endif /* CEC */
#if defined(DCMI)
#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */
#endif /* DCMI */
#if defined(PSSI)
#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */
#endif /* PSSI */
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#if defined(I2C3)
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#endif /* I2C3 */
#if defined(I2C4)
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#define GPIO_AF4_LPTIM1 ((uint8_t)0x04) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF4_LPTIM2 ((uint8_t)0x04) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF4_SPI1 ((uint8_t)0x04) /* SPI1 Alternate Function mapping */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF4_SPI3 ((uint8_t)0x04) /* SPI3 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
#if defined(TIM15)
#define GPIO_AF4_TIM15 ((uint8_t)0x04) /* TIM15 Alternate Function mapping */
#endif /* TIM15 */
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#if defined(STM32H503xx)
#define GPIO_AF4_USART2 ((uint8_t)0x04) /* USART2 Alternate Function mapping */
#endif /* STM32H503xx */
/**
* @brief AF 5 selection
*/
#if defined(CEC)
#define GPIO_AF5_CEC ((uint8_t)0x05) /* CEC Alternate Function mapping */
#endif /* CEC */
#if !defined(STM32H503xx)
#define GPIO_AF5_I3C1 ((uint8_t)0x05) /* I3C1 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */
#endif /* STM32H503xx */
#define GPIO_AF5_LPTIM1 ((uint8_t)0x05) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */
#if defined(SPI4)
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#endif /* SPI4 */
#if defined(SPI5)
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#endif /* SPI5 */
#if defined(SPI6)
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#endif /* SPI6 */
/**
* @brief AF 6 selection
*/
#if defined(I2C4)
#define GPIO_AF6_I2C4 ((uint8_t)0x06) /* I2C4 Alternate Function mapping */
#endif /* I2C4 */
#if defined(OCTOSPI1)
#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */
#endif /* OCTOSPI1 */
#if defined(SAI1)
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#endif /* SAI1 */
#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF6_SPI1 ((uint8_t)0x06) /* SPI1 Alternate Function mapping */
#define GPIO_AF6_SPI2 ((uint8_t)0x06) /* SPI2 Alternate Function mapping */
#endif /* STM32H503xx || STM32H533xx || STM32H523xx */
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */
#if defined(SPI4)
#define GPIO_AF6_SPI4 ((uint8_t)0x06) /* SPI4 Alternate Function mapping */
#endif /* SPI4 */
#if defined(UART4)
#define GPIO_AF6_UART4 ((uint8_t)0x06) /* UART4 Alternate Function mapping */
#endif /* UART4 */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF6_USART6 ((uint8_t)0x06) /* USART6 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
#if defined(UART12)
#define GPIO_AF6_UART12 ((uint8_t)0x06) /* UART12 Alternate Function mapping */
#endif /* UART12 */
#if defined(USART10)
#define GPIO_AF6_USART10 ((uint8_t)0x06) /* USART10 Alternate Function mapping */
#endif /* USART10 */
#if defined(UCPD1)
#define GPIO_AF6_UCPD1 ((uint8_t)0x06) /* UCPD1 Alternate Function mapping */
#endif /* UCPD1 */
/**
* @brief AF 7 selection
*/
#if defined(SDMMC1)
#define GPIO_AF7_SDMMC1 ((uint8_t)0x07) /* SDMMC1 Alternate Function mapping */
#endif /* SDMMC1 */
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#if defined(SPI6)
#define GPIO_AF7_SPI6 ((uint8_t)0x07) /* SPI6 Alternate Function mapping */
#endif /* SPI6 */
#if defined(UART7)
#define GPIO_AF7_UART7 ((uint8_t)0x07) /* UART7 Alternate Function mapping */
#endif /* UART7 */
#if defined(UART8)
#define GPIO_AF7_UART8 ((uint8_t)0x07) /* UART8 Alternate Function mapping */
#endif /* UART8 */
#if defined(UART12)
#define GPIO_AF7_UART12 ((uint8_t)0x07) /* UART12 Alternate Function mapping */
#endif /* UART12 */
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#if defined(USART6)
#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */
#endif /* USART6 */
#if defined(USART10)
#define GPIO_AF7_USART10 ((uint8_t)0x07) /* USART10 Alternate Function mapping */
#endif /* USART10 */
#if defined(USART11)
#define GPIO_AF7_USART11 ((uint8_t)0x07) /* USART11 Alternate Function mapping */
#endif /* USART11 */
/**
* @brief AF 8 selection
*/
#if defined(STM32H503xx)
#define GPIO_AF8_I2C2 ((uint8_t)0x08) /* I2C2 Alternate Function mapping */
#define GPIO_AF8_I3C1 ((uint8_t)0x08) /* I3C1 Alternate Function mapping */
#define GPIO_AF8_USART1 ((uint8_t)0x08) /* USART1 Alternate Function mapping */
#endif /* STM32H503xx */
#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */
#if defined(SAI2)
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#endif /* SAI2 */
#if defined(SDMMC1)
#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */
#endif /* SDMMC1 */
#if defined(SPI6)
#define GPIO_AF8_SPI6 ((uint8_t)0x08) /* SPI6 Alternate Function mapping */
#endif /* SPI6 */
#if defined(UART4)
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#endif /* UART4 */
#if defined(UART5)
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#endif /* UART5 */
#if defined(UART8)
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#endif /* UART8 */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */
#if defined(FDCAN2)
#define GPIO_AF9_FDCAN2 ((uint8_t)0x09) /* FDCAN2 Alternate Function mapping */
#endif /* FDCAN2 */
#if defined(FMC_BANK1)
#define GPIO_AF9_FMC ((uint8_t)0x09) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#if defined(OCTOSPI1)
#define GPIO_AF9_OCTOSPI1 ((uint8_t)0x09) /* OCTOSPI1 Alternate Function mapping */
#endif /* OCTOSPI1 */
#if defined(SDMMC2)
#define GPIO_AF9_SDMMC2 ((uint8_t)0x09) /* SDMMC2 Alternate Function mapping */
#endif /* SDMMC2 */
#if defined(TIM13)
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#endif /* TIM13 */
#if defined(TIM14)
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#endif /* TIM14 */
#if defined(STM32H503xx)
#define GPIO_AF9_USART2 ((uint8_t)0x09) /* USART2 Alternate Function mapping */
#define GPIO_AF9_USART3 ((uint8_t)0x09) /* USART3 Alternate Function mapping */
#endif /* STM32H503xx */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */
#define GPIO_AF9_I3C2 ((uint8_t)0x09) /* I3C2 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */
#if defined(STM32H503xx)
#define GPIO_AF10_I3C1 ((uint8_t)0x0A) /* I3C1 Alternate Function mapping */
#define GPIO_AF10_SPI3 ((uint8_t)0x0A) /* SPI3 Alternate Function mapping */
#endif /* STM32H503xx */
#if (defined(STM32H503xx) || defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF10_I3C2 ((uint8_t)0x0A) /* I3C2 Alternate Function mapping */
#endif /* STM32H503xx || STM32H533xx || STM32H523xx */
#if defined(FMC_BANK1)
#define GPIO_AF10_FMC ((uint8_t)0x0A) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#if defined(OCTOSPI1)
#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */
#endif /* OCTOSPI1 */
#if defined(SAI2)
#define GPIO_AF10_SAI2 ((uint8_t)0x0A) /* SAI2 Alternate Function mapping */
#endif /* SAI2 */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF10_SDMMC1 ((uint8_t)0x0A) /* SDMMC1 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
#if defined(SDMMC2)
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0A) /* SDMMC2 Alternate Function mapping */
#endif /* SDMMC2 */
#if defined(TIM8)
#define GPIO_AF10_TIM8 ((uint8_t)0x0A) /* TIM8 Alternate Function mapping */
#endif /* TIM8 */
#if defined(USB_DRD_FS)
#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */
#endif /* USB_DRD_FS */
#if defined(LTDC)
#define GPIO_AF10_LTDC ((uint8_t)0x0A) /* LTDC Alternate Function mapping */
#endif /* LTDC */
/**
* @brief AF 11 selection
*/
#if defined(ETH)
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETH Alternate Function mapping */
#endif /* ETH */
#if defined(FMC_BANK1)
#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#if defined(OCTOSPI1)
#define GPIO_AF11_OCTOSPI1 ((uint8_t)0x0B) /* OCTOSPI1 Alternate Function mapping */
#endif /* OCTOSPI1 */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF11_SDMMC1 ((uint8_t)0x0B) /* SDMMC1 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
#if defined(SDMMC2)
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */
#endif /* SDMMC2 */
#if defined(UART7)
#define GPIO_AF11_UART7 ((uint8_t)0x0B) /* UART7 Alternate Function mapping */
#endif /* UART7 */
#if defined(UART9)
#define GPIO_AF11_UART9 ((uint8_t)0x0B) /* UART9 Alternate Function mapping */
#endif /* UART9 */
#if defined(UCPD1)
#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */
#endif /* UCPD1 */
#if defined(STM32H503xx)
#define GPIO_AF11_I2C1 ((uint8_t)0x0B) /* I2C1 Alternate Function mapping */
#define GPIO_AF11_I2C2 ((uint8_t)0x0B) /* I2C2 Alternate Function mapping */
#define GPIO_AF11_SPI2 ((uint8_t)0x0B) /* SPI2 Alternate Function mapping */
#define GPIO_AF11_USART2 ((uint8_t)0x0B) /* USART2 Alternate Function mapping */
#endif /* STM32H503xx */
/**
* @brief AF 12 selection
*/
#if defined(FMC_BANK1)
#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#if defined(SDMMC1)
#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */
#endif /* SDMMC1 */
#if defined(STM32H503xx)
#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */
#define GPIO_AF12_SPI1 ((uint8_t)0x0C) /* SPI1 Alternate Function mapping */
#endif /* STM32H503xx */
/**
* @brief AF 13 selection
*/
#if defined(DCMI)
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#define GPIO_AF13_PSSI ((uint8_t)0x0D) /* PSSI Alternate Function mapping */
#endif /* DCMI */
#if defined(FMC_BANK1)
#define GPIO_AF13_FMC ((uint8_t)0x0D) /* FMC Alternate Function mapping */
#endif /* FMC_BANK1 */
#if defined(LPTIM5)
#define GPIO_AF13_LPTIM5 ((uint8_t)0x0D) /* LPTIM5 Alternate Function mapping */
#endif /* LPTIM5 */
#if defined(STM32H503xx)
#define GPIO_AF13_USART2 ((uint8_t)0x0D) /* USART2 Alternate Function mapping */
#define GPIO_AF13_USART3 ((uint8_t)0x0D) /* USART3 Alternate Function mapping */
#endif /* STM32H503xx */
/**
* @brief AF 14 selection
*/
#if defined(STM32H503xx)
#define GPIO_AF14_LPTIM1 ((uint8_t)0x0E) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */
#define GPIO_AF14_TIM1 ((uint8_t)0x0E) /* TIM1 Alternate Function mapping */
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#define GPIO_AF14_TIM3 ((uint8_t)0x0E) /* TIM3 Alternate Function mapping */
#endif /* STM32H503xx */
#if defined(LPTIM3)
#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */
#endif /* LPTIM3 */
#if defined(LPTIM4)
#define GPIO_AF14_LPTIM4 ((uint8_t)0x0E) /* LPTIM4 Alternate Function mapping */
#endif /* LPTIM4 */
#if defined(LPTIM5)
#define GPIO_AF14_LPTIM5 ((uint8_t)0x0E) /* LPTIM5 Alternate Function mapping */
#endif /* LPTIM5 */
#if defined(LPTIM6)
#define GPIO_AF14_LPTIM6 ((uint8_t)0x0E) /* LPTIM6 Alternate Function mapping */
#endif /* LPTIM6 */
#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || defined(STM32H523xx)
#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */
#endif /* STM32H573xx || STM32H563xx || STM32H562xx || STM32H533xx || STM32H523xx */
#if defined(UART5)
#define GPIO_AF14_UART5 ((uint8_t)0x0E) /* UART5 Alternate Function mapping */
#endif /* UART5 */
#if (defined(STM32H533xx) || defined(STM32H523xx))
#define GPIO_AF14_USART6 ((uint8_t)0x0E) /* USART6 Alternate Function mapping */
#endif /* STM32H533xx || STM32H523xx */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F)
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros
* @{
*/
/** @defgroup GPIOEx_Get_Port_Index GPIOEx_Get Port Index
* @{
*/
/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */
#if defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \
defined(STM32H523xx) || defined(STM32H503xx)
#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10)
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) || defined(STM32H533xx) || \
defined(STM32H523xx) || defined(STM32H503xx) */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_GPIO_EX_H */

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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h Normal file
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/**
******************************************************************************
* @file stm32h5xx_hal_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H5xx_HAL_ICACHE_H
#define STM32H5xx_HAL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
#if defined(ICACHE)
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup ICACHE
* @{
*/
/* Exported types -----------------------------------------------------------*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_Exported_Types ICACHE Exported Types
* @{
*/
/**
* @brief HAL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */
uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */
uint32_t Size; /*!< Configures the Region size.
This parameter can be a value of @ref ICACHE_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_Output_Burst_Type */
} ICACHE_RegionConfigTypeDef;
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_WaysSelection Ways selection
* @{
*/
#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_Monitor_Type Monitor type
* @{
*/
#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_Region Remapped Region number
* @{
*/
#define ICACHE_REGION_0 0U /*!< Region 0 */
#define ICACHE_REGION_1 1U /*!< Region 1 */
#define ICACHE_REGION_2 2U /*!< Region 2 */
#define ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_Region_Size Remapped Region size
* @{
*/
#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
* @{
*/
#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
* @{
*/
#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/** @defgroup ICACHE_Interrupts Interrupts
* @{
*/
#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_Flags Flags
* @{
*/
#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
* @brief macros to manage the specified ICACHE flags and interrupts.
* @{
*/
/** @brief Enable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Disable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
* @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
* @retval The state of __INTERRUPT__ (0 or 1).
*/
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
/** @brief Check whether the selected ICACHE flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref ICACHE_FLAG_BUSY Busy flag
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
* @retval The state of __FLAG__ (0 or 1).
*/
#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
/** @brief Clear the selected ICACHE flags.
* @param __FLAG__ specifies the ICACHE flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
*/
#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions -------------------------------------------------------*/
/** @addtogroup ICACHE_Exported_Functions
* @{
*/
/** @addtogroup ICACHE_Exported_Functions_Group1
* @brief Initialization and control functions
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
uint32_t HAL_ICACHE_IsEnabled(void);
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
/******* Invalidate in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
/******* Invalidate in non-blocking mode (Interrupt) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
/******* Wait for Invalidate complete in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
/******* Performance instruction cache monitoring functions */
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
/**
* @}
*/
/** @addtogroup ICACHE_Exported_Functions_Group2
* @brief IRQ and callback functions
* @{
*/
/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
void HAL_ICACHE_IRQHandler(void);
void HAL_ICACHE_InvalidateCompleteCallback(void);
void HAL_ICACHE_ErrorCallback(void);
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @addtogroup ICACHE_Exported_Functions_Group3
* @brief Memory remapped regions functions
* @{
*/
/******* Memory remapped regions functions */
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig);
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_ICACHE_H */

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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr.h Normal file
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/**
******************************************************************************
* @file stm32h5xx_hal_pwr.h
* @author MCD Application Team
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_PWR_H
#define STM32H5xx_HAL_PWR_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup PWR
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWR_Exported_Types PWR Exported Types
* @{
*/
/**
* @brief PWR PVD configuration structure definition
*/
typedef struct
{
uint32_t PVDLevel; /*!< Specifies the PVD detection level.
This parameter can be a value of
@ref PWR_PVD_Detection_Level. */
uint32_t Mode; /*!< Specifies the operating mode for the selected pins.
This parameter can be a value of @ref PWR_PVD_Mode. */
} PWR_PVDTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWR_Exported_Constants PWR Exported Constants
* @{
*/
/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level
* @{
*/
#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 1.95 V */
#define PWR_PVDLEVEL_1 (PWR_VMCR_PLS_0) /*!< PVD threshold around 2.1 V */
#define PWR_PVDLEVEL_2 (PWR_VMCR_PLS_1) /*!< PVD threshold around 2.25 V */
#define PWR_PVDLEVEL_3 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_1) /*!< PVD threshold around 2.4 V */
#define PWR_PVDLEVEL_4 (PWR_VMCR_PLS_2) /*!< PVD threshold around 2.55 V */
#define PWR_PVDLEVEL_5 (PWR_VMCR_PLS_0 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.7 V */
#define PWR_PVDLEVEL_6 (PWR_VMCR_PLS_1 | PWR_VMCR_PLS_2) /*!< PVD threshold around 2.85 V */
#define PWR_PVDLEVEL_7 (PWR_VMCR_PLS) /*!< External input analog voltage
(compared internally to VREFINT) */
/**
* @}
*/
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */
#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling
edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling
edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in SLEEP/STOP Mode
* @{
*/
#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */
#define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */
/**
* @}
*/
/** @defgroup PWR_SLEEP_Mode_Entry PWR SLEEP Mode Entry
* @{
*/
#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */
#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */
/**
* @}
*/
/** @defgroup PWR_STOP_Mode_Entry PWR STOP Mode Entry
* @{
*/
#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */
#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */
/**
* @}
*/
/** @defgroup PWR_Flags PWR Flags
* @{
*/
#define PWR_FLAG_STOPF (0x01U) /*!< STOP flag */
#define PWR_FLAG_SBF (0x02U) /*!< STANDBY flag */
#define PWR_FLAG_VOSRDY (0x03U) /*!< Voltage scaling ready flag */
#define PWR_FLAG_ACTVOSRDY (0x04U) /*!< Currently applied VOS ready flag */
#define PWR_FLAG_BRR (0x05U) /*!< Backup regulator ready flag */
#define PWR_FLAG_VBATL (0x06U) /*!< Backup domain voltage level flag (versus low threshold) */
#define PWR_FLAG_VBATH (0x07U) /*!< Backup domain voltage level flag (versus high threshold) */
#define PWR_FLAG_TEMPL (0x08U) /*!< Temperature level flag (versus low threshold) */
#define PWR_FLAG_TEMPH (0x09U) /*!< Temperature level flag (versus high threshold) */
#define PWR_FLAG_AVDO (0x0AU) /*!< VDDA voltage detector output flag */
#define PWR_FLAG_VDDIO2RDY (0x0BU) /*!< VDDIO2 voltage detector output flag */
#define PWR_FLAG_PVDO (0x0CU) /*!< VDD voltage detector output flag */
#define PWR_FLAG_USB33RDY (0x0DU) /*!< VDDUSB33 ready flag */
#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wake up line 1 flag */
#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wake up line 2 flag */
#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wake up line 3 flag */
#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wake up line 4 flag */
#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wake up line 5 flag */
#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wake up line 6 flag */
#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wake up line 7 flag */
#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wake up line 8 flag */
#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */
/**
* @}
*/
/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins
* @{
*/
/* High level and No pull (default configuration) */
#define PWR_WAKEUP_PIN1 PWR_WUCR_WUPEN1
#define PWR_WAKEUP_PIN2 PWR_WUCR_WUPEN2
#define PWR_WAKEUP_PIN3 PWR_WUCR_WUPEN3
#define PWR_WAKEUP_PIN4 PWR_WUCR_WUPEN4
#define PWR_WAKEUP_PIN5 PWR_WUCR_WUPEN5
#if defined (PWR_WUCR_WUPEN6)
#define PWR_WAKEUP_PIN6 PWR_WUCR_WUPEN6
#define PWR_WAKEUP_PIN7 PWR_WUCR_WUPEN7
#define PWR_WAKEUP_PIN8 PWR_WUCR_WUPEN8
#endif /* PWR_WUCR_WUPEN6 */
/* High level and No pull */
#define PWR_WAKEUP_PIN1_HIGH PWR_WUCR_WUPEN1
#define PWR_WAKEUP_PIN2_HIGH PWR_WUCR_WUPEN2
#define PWR_WAKEUP_PIN3_HIGH PWR_WUCR_WUPEN3
#define PWR_WAKEUP_PIN4_HIGH PWR_WUCR_WUPEN4
#define PWR_WAKEUP_PIN5_HIGH PWR_WUCR_WUPEN5
#if defined (PWR_WUCR_WUPEN6)
#define PWR_WAKEUP_PIN6_HIGH PWR_WUCR_WUPEN6
#define PWR_WAKEUP_PIN7_HIGH PWR_WUCR_WUPEN7
#define PWR_WAKEUP_PIN8_HIGH PWR_WUCR_WUPEN8
#endif /* PWR_WUCR_WUPEN6 */
/* Low level and No pull */
#define PWR_WAKEUP_PIN1_LOW (PWR_WUCR_WUPP1 | PWR_WUCR_WUPEN1)
#define PWR_WAKEUP_PIN2_LOW (PWR_WUCR_WUPP2 | PWR_WUCR_WUPEN2)
#define PWR_WAKEUP_PIN3_LOW (PWR_WUCR_WUPP3 | PWR_WUCR_WUPEN3)
#define PWR_WAKEUP_PIN4_LOW (PWR_WUCR_WUPP4 | PWR_WUCR_WUPEN4)
#define PWR_WAKEUP_PIN5_LOW (PWR_WUCR_WUPP5 | PWR_WUCR_WUPEN5)
#if defined (PWR_WUCR_WUPEN6)
#define PWR_WAKEUP_PIN6_LOW (PWR_WUCR_WUPP6 | PWR_WUCR_WUPEN6)
#define PWR_WAKEUP_PIN7_LOW (PWR_WUCR_WUPP7 | PWR_WUCR_WUPEN7)
#define PWR_WAKEUP_PIN8_LOW (PWR_WUCR_WUPP8 | PWR_WUCR_WUPEN8)
#endif /* PWR_WUCR_WUPEN6 */
/**
* @}
*/
/** @defgroup PWR_Items PWR Items
* @{
*/
#if defined(PWR_SECCFGR_WUP1SEC)
#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */
#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */
#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */
#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */
#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */
#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */
#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */
#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */
#define PWR_RET (PWR_SECCFGR_RETSEC) /*!< IO Retention secure protection */
#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */
#define PWR_SCM (PWR_SECCFGR_SCMSEC) /*!< Voltage detection and monitoring secure protection */
#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */
#define PWR_VUSB (PWR_SECCFGR_VUSBSEC) /*!< Voltage USB secure protection */
#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \
PWR_WKUP5 | PWR_WKUP6 | PWR_WKUP7 | PWR_WKUP8 | \
PWR_LPM | PWR_SCM | PWR_VB | PWR_VUSB | \
PWR_RET)
#else
#define PWR_ALL 0xFF /*!< Dummy Value */
#endif /* PWR_SECCFGR_WUP1SEC */
/**
* @}
*/
/** @defgroup PWR_Attributes PWR Attributes
* @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes
* @{
*/
#if defined(PWR_PRIVCFGR_NSPRIV)
#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */
#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */
#else
#define PWR_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< Privileged attribute */
#define PWR_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NPrivileged attribute */
#endif /* PWR_PRIVCFGR_NSPRIV */
#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */
#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWR_Exported_Macros PWR Exported Macros
* @{
*/
/** @brief Check PWR flags are set or not.
* @param __FLAG__ : Specifies the flag to check.
* This parameter can be one of the following values :
* @arg @ref PWR_FLAG_STOPF : Stop flag.
* Indicates that the device was resumed from Stop mode.
* @arg @ref PWR_FLAG_SBF : Standby flag.
* Indicates that the device was resumed from Standby mode.
* @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag.
* Indicates that the Vcore level at or above VOS selected level.
* @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag.
* Indicates that Vcore is equal to the current
* voltage scaling provided by ACTVOS.
* @arg @ref PWR_FLAG_BRR : Backup regulator ready flag. This bit is not
* reset when the device wakes up from STANDBY
* mode or by a system reset or power-on reset.
* @arg @ref PWR_FLAG_VBATL : Backup domain voltage level flag (versus low threshold).
* Indicates the backup domain voltage
* level is equal or above low threshold.
* @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold).
* Indicates the backup domain voltage
* level is equal or above high threshold.
* @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold).
* Indicates the temperature is equal or above low threshold.
* @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold).
* Indicates the temperature is equal or above high threshold.
* @arg @ref PWR_FLAG_AVDO : Regulator selection flag.
* Indicates the regulator selected.
* @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold).
* Indicates that VDDIO2 is equal or above the threshold
* of the VDDIO2 voltage monitor (around 0.9 V).
* @arg @ref PWR_FLAG_PVDO : Voltage detector output flag.
* Indicates that Vdd is equal or above
* the PVD threshold selected by PVDLS.
* @arg @ref PWR_FLAG_USB33RDY : VDDUSB ready flag (versus 1.2 V threshold).
* Indicates that VDDUSB is equal or above the threshold
* of the VDDUSB voltage monitor (around 1.2 V).
* @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1.
* Indicates that a wakeup event was received from the WKUP line 1.
* @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2.
* Indicates that a wakeup event was received from the WKUP line 2.
* @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3.
* Indicates that a wakeup event was received from the WKUP line 3.
* @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4.
* Indicates that a wakeup event was received from the WKUP line 4.
* @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5.
* Indicates that a wakeup event was received from the WKUP line 5.
* @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6.
* Indicates that a wakeup event was received from the WKUP line 6.
* @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7.
* Indicates that a wakeup event was received from the WKUP line 7.
* @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8.
* Indicates that a wakeup event was received from the WKUP line 8.
* @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices.
* @retval The state of __FLAG__ (TRUE or FALSE).
*/
#if defined (PWR_WUSR_WUF6)
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \
((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \
((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \
((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \
((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \
((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \
((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \
((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \
((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \
((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \
((__FLAG__) == PWR_FLAG_USB33RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == PWR_VMSR_USB33RDY) : \
((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \
((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \
((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \
((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \
((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \
((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \
((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \
(READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8))
#else
#define __HAL_PWR_GET_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == PWR_PMSR_STOPF) : \
((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == PWR_PMSR_SBF) : \
((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == PWR_VOSSR_VOSRDY) : \
((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == PWR_VOSSR_ACTVOSRDY) : \
((__FLAG__) == PWR_FLAG_BRR) ? (READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == PWR_BDSR_BRRDY) : \
((__FLAG__) == PWR_FLAG_VBATL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == PWR_BDSR_VBATL) : \
((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \
((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \
((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \
((__FLAG__) == PWR_FLAG_AVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == PWR_VMSR_AVDO) : \
((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->VMSR, PWR_VMSR_VDDIO2RDY) == PWR_VMSR_VDDIO2RDY) : \
((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == PWR_VMSR_PVDO) : \
((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \
((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \
((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \
((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \
(READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5))
#endif /* PWR_WUSR_WUF6 */
/** @brief Clear PWR flags.
* @param __FLAG__ : Specifies the flag to clear.
* This parameter can be one of the following values :
* @arg @ref PWR_FLAG_STOPF : STOP flag.
* Indicates that the device was resumed from STOP mode.
* @arg @ref PWR_FLAG_SBF : STANDBY flag.
* Indicates that the device was resumed from STANDBY mode.
* @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1.
* Indicates that a wakeup event was received from the WKUP line 1.
* @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2.
* Indicates that a wakeup event was received from the WKUP line 2.
* @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3.
* Indicates that a wakeup event was received from the WKUP line 3.
* @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4.
* Indicates that a wakeup event was received from the WKUP line 4.
* @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5.
* Indicates that a wakeup event was received from the WKUP line 5.
* @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6.
* Indicates that a wakeup event was received from the WKUP line 6.
* @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7.
* Indicates that a wakeup event was received from the WKUP line 7.
* @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8.
* Indicates that a wakeup event was received from the WKUP line 8.
* @note The PWR_WAKEUP_FLAG6, PWR_WAKEUP_FLAG7 AND PWR_WAKEUP_FLAG8 are not available for STM32H503xx devices.
* @retval None.
*/
#if defined (PWR_WUSCR_CWUF6)
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \
((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \
((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \
((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \
((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \
((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \
((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \
((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \
((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \
((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \
(SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF)))
#else
#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \
(((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \
((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->PMCR, PWR_PMCR_CSSF)) : \
((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \
((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \
((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \
((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \
((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \
(SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF)))
#endif /* PWR_WUSCR_CWUF6 */
/**
* @brief Enable the PVD Extended Interrupt Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Event Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Event Line.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Disable the PVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)
/**
* @brief Enable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do \
{ \
__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do \
{ \
__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0)
/**
* @brief Generate a Software Interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)
/**
* @brief Check whether the specified PVD EXTI Rising interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_RISING_FLAG() \
((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
/**
* @brief Check whether the specified PVD EXTI Falling interrupt flag is set or not.
* @retval EXTI PVD Line Status.
*/
#define __HAL_PWR_PVD_EXTI_GET_FALLING_FLAG()\
((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)
/**
* @brief Clear the PVD EXTI Interrupt Rising flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_RISING_FLAG() WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD);
/**
* @brief Clear the PVD EXTI Interrupt Falling flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FALLING_FLAG() WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD);
/**
* @brief Clear the PVD EXTI Interrupt flag.
* @retval None.
*/
#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \
do \
{ \
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \
} while(0)
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWR_Private_Constants PWR Private Constants
* @{
*/
/* Define PVD extended interrupts and event line */
#define PWR_EXTI_LINE_PVD EXTI_IMR1_IM16 /*!< PVD EXTI Line */
/* Defines wake up lines shift */
#define PWR_EWUP_MASK (0x0FFF3F3FU)
/* Defines attribute */
#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */
#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup PWR_Private_Macros PWR Private Macros
* @{
*/
#if defined(PWR_WUCR_WUPEN6)
/* Check wake up pin parameter */
#define IS_PWR_WAKEUP_PIN(PIN) \
(((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\
((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN6) ||\
((PIN) == PWR_WAKEUP_PIN7) || ((PIN) == PWR_WAKEUP_PIN8) ||\
((PIN) == PWR_WAKEUP_PIN1_HIGH) || ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN3_HIGH) || ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN5_HIGH) || ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN7_HIGH) || ((PIN) == PWR_WAKEUP_PIN8_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
((PIN) == PWR_WAKEUP_PIN5_LOW) || ((PIN) == PWR_WAKEUP_PIN6_LOW) ||\
((PIN) == PWR_WAKEUP_PIN7_LOW) || ((PIN) == PWR_WAKEUP_PIN8_LOW))
#else
/* Check wake up pin parameter */
#define IS_PWR_WAKEUP_PIN(PIN) \
(((PIN) == PWR_WAKEUP_PIN1) || ((PIN) == PWR_WAKEUP_PIN2) ||\
((PIN) == PWR_WAKEUP_PIN3) || ((PIN) == PWR_WAKEUP_PIN4) ||\
((PIN) == PWR_WAKEUP_PIN5) || ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN2_HIGH) || ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN4_HIGH) || ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\
((PIN) == PWR_WAKEUP_PIN1_LOW) || ((PIN) == PWR_WAKEUP_PIN2_LOW) ||\
((PIN) == PWR_WAKEUP_PIN3_LOW) || ((PIN) == PWR_WAKEUP_PIN4_LOW) ||\
((PIN) == PWR_WAKEUP_PIN5_LOW))
#endif /* PWR_WUCR_WUPEN6 */
/* PVD level check macro */
#define IS_PWR_PVD_LEVEL(LEVEL) \
(((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\
((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
/* PVD mode check macro */
#define IS_PWR_PVD_MODE(MODE) \
(((MODE) == PWR_PVD_MODE_NORMAL) ||\
((MODE) == PWR_PVD_MODE_IT_RISING) ||\
((MODE) == PWR_PVD_MODE_IT_FALLING) ||\
((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING))
/* SLEEP mode entry check macro */
#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
/* STOP mode entry check macro */
#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
#if defined (PWR_SECCFGR_WUP1SEC)
/* PWR items check macro */
#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U))
#endif /* PWR_SECCFGR_WUP1SEC */
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
/* PWR attribute check macro (Secure) */
#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \
((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) &((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U))
#elif defined(PWR_PRIVCFGR_NSPRIV)
/* PWR attribute check macro (NSecure) */
#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV))
#else
/* PWR attribute check macro (NSecure) */
#define IS_PWR_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == PWR_NPRIV) || ((ATTRIBUTES) == PWR_PRIV))
#endif /* __ARM_FEATURE_CMSE */
/**
* @}
*/
/* Include PWR HAL Extended module */
#include "stm32h5xx_hal_pwr_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PWR_Exported_Functions
* @{
*/
/** @addtogroup PWR_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
void HAL_PWR_DeInit(void);
void HAL_PWR_EnableBkUpAccess(void);
void HAL_PWR_DisableBkUpAccess(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group2
* @{
*/
/* Programmable voltage detector functions ************************************/
HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD);
void HAL_PWR_EnablePVD(void);
void HAL_PWR_DisablePVD(void);
/* Wake up pins configuration functions ***************************************/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
/* Low power modes configuration functions ************************************/
void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
void HAL_PWR_EnterSTANDBYMode(void);
/* Sleep on exit and sev on pending configuration functions *******************/
void HAL_PWR_EnableSleepOnExit(void);
void HAL_PWR_DisableSleepOnExit(void);
void HAL_PWR_EnableSEVOnPend(void);
void HAL_PWR_DisableSEVOnPend(void);
/* Interrupt handler functions ************************************************/
void HAL_PWR_PVD_IRQHandler(void);
void HAL_PWR_PVDCallback(void);
/**
* @}
*/
/** @addtogroup PWR_Exported_Functions_Group3
* @{
*/
/* Privileges and security configuration functions ****************************/
void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes);
HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H5xx_HAL_PWR_H */

562
Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_pwr_ex.h Normal file
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@@ -0,0 +1,562 @@
/**
******************************************************************************
* @file stm32h5xx_hal_pwr_ex.h
* @author MCD Application Team
* @brief Header file of PWR HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_PWR_EX_H
#define STM32H5xx_HAL_PWR_EX_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup PWREx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup PWREx_Exported_Types PWR Extended Exported Types
* @{
*/
/**
* @brief PWREx AVD configuration structure definition
*/
typedef struct
{
uint32_t AVDLevel; /*!< AVDLevel: Specifies the AVD detection level. This
parameter can be a value of @ref
PWREx_AVD_detection_level
*/
uint32_t Mode; /*!< Mode: Specifies the EXTI operating mode for the AVD
event. This parameter can be a value of @ref
PWREx_AVD_Mode.
*/
} PWREx_AVDTypeDef;
/**
* @brief PWREx Wakeup pin configuration structure definition
*/
typedef struct
{
uint32_t WakeUpPin; /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.
This parameter can be a value of @ref
PWREx_WakeUp_Pins
*/
uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.
This parameter can be a value of @ref
PWREx_PIN_Polarity
*/
uint32_t PinPull; /*!< PinPull: Specifies the Wake-Up pin pull. This
parameter can be a value of @ref
PWREx_PIN_Pull
*/
} PWREx_WakeupPinTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants
* @{
*/
/** @defgroup PWREx_Supply_configuration PWREx Supply configuration
* @{
*/
#define PWR_EXTERNAL_SOURCE_SUPPLY PWR_SCCR_BYPASS /*!< The SMPS disabled and the LDO Bypass. The Core domains
are supplied from an external source */
#if defined (SMPS)
#define PWR_SUPPLY_CONFIG_MASK (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)
#else
#define PWR_SUPPLY_CONFIG_MASK (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS)
#endif /* defined (SMPS) */
/**
* @}
*/
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
* @{
*/
#define PWR_PIN_POLARITY_HIGH (0x00000000U)
#define PWR_PIN_POLARITY_LOW (0x00000001U)
/**
* @}
*/
/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration
* @{
*/
#define PWR_PIN_NO_PULL (0x00000000U)
#define PWR_PIN_PULL_UP (0x00000001U)
#define PWR_PIN_PULL_DOWN (0x00000002U)
/**
* @}
*/
/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level
* @{
*/
#define PWR_AVDLEVEL_0 (0x00000000U) /*!< Analog voltage detector level 0 selection : 1V7 */
#define PWR_AVDLEVEL_1 PWR_VMCR_ALS_0 /*!< Analog voltage detector level 1 selection : 2V1 */
#define PWR_AVDLEVEL_2 PWR_VMCR_ALS_1 /*!< Analog voltage detector level 2 selection : 2V5 */
#define PWR_AVDLEVEL_3 PWR_VMCR_ALS /*!< Analog voltage detector level 3 selection : 2V8 */
/**
* @}
*/
/** @defgroup PWREx_AVD_Mode PWREx AVD Mode
* @{
*/
#define PWR_AVD_MODE_NORMAL (0x00000000U)/*!< Basic mode is used */
#define PWR_AVD_MODE_IT_RISING (0x00010001U)/*!< External Interrupt Mode with Rising edge trigger detection*/
#define PWR_AVD_MODE_IT_FALLING (0x00010002U)/*!< External Interrupt Mode with
Falling edge trigger detection */
#define PWR_AVD_MODE_IT_RISING_FALLING (0x00010003U)/*!< External Interrupt Mode with
Rising/Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING (0x00020001U)/*!< Event Mode with Rising edge trigger detection */
#define PWR_AVD_MODE_EVENT_FALLING (0x00020002U)/*!< Event Mode with Falling edge trigger detection */
#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)/*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale
* @{
*/
#define PWR_REGULATOR_VOLTAGE_SCALE0 PWR_VOSCR_VOS /*!< Voltage scaling range 0 */
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_VOSCR_VOS_1 /*!< Voltage scaling range 1 */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSCR_VOS_0 /*!< Voltage scaling range 2 */
#define PWR_REGULATOR_VOLTAGE_SCALE3 (0U) /*!< Voltage scaling range 3 */
/**
* @}
*/
/** @defgroup PWREx_System_Stop_Mode_Voltage_Scale PWREx System Stop Mode Voltage Scale
* @{
*/
#define PWR_REGULATOR_SVOS_SCALE5 (PWR_PMCR_SVOS_0)
#define PWR_REGULATOR_SVOS_SCALE4 (PWR_PMCR_SVOS_1)
#define PWR_REGULATOR_SVOS_SCALE3 (PWR_PMCR_SVOS_0 | PWR_PMCR_SVOS_1)
/**
* @}
*/
/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection
* @{
*/
#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */
#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */
/**
* @}
*/
/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection
* @{
*/
#define PWR_RAM1_MEMORY_BLOCK PWR_PMCR_SRAM1SO /*!< RAM1 shut-off control in Stop mode */
#if defined (PWR_PMCR_SRAM2_16SO)
#define PWR_RAM2_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16SO /*!< RAM2 16k byte shut-off control in Stop mode */
#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */
#elif defined (PWR_PMCR_SRAM2_16LSO)
#define PWR_RAM2_LOW_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16LSO /*!< RAM2 low 16k byte shut-off control in Stop mode */
#define PWR_RAM2_HIGH_16_MEMORY_BLOCK PWR_PMCR_SRAM2_16HSO /*!< RAM2 High 16k byte shut-off control in Stop mode */
#define PWR_RAM2_48_MEMORY_BLOCK PWR_PMCR_SRAM2_48SO /*!< RAM2 48k byte shut-off control in Stop mode */
#else
#define PWR_RAM2_MEMORY_BLOCK PWR_PMCR_SRAM2SO /*!< RAM2 shut-off control in Stop mode */
#endif /* PWR_PMCR_SRAM2_16SO */
#if defined (PWR_PMCR_SRAM3SO)
#define PWR_RAM3_MEMORY_BLOCK PWR_PMCR_SRAM3SO /*!< RAM3 shut-off control in Stop mode */
#endif /* PWR_PMCR_SRAM3SO */
#if defined (PWR_PMCR_ETHERNETSO)
#define PWR_ETHERNET_MEMORY_BLOCK PWR_PMCR_ETHERNETSO /*!< Ethernet shut-off control in Stop mode */
#endif /* PWR_PMCR_ETHERNETSO */
/**
* @}
*/
/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16
* @{
*/
#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16
Connected to the AVD EXTI Line */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros
* @{
*/
/**
* @brief Enable the AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD EXTI Line 16
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable event on AVD EXTI Line 16.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Rising Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Disable the AVD Extended Interrupt Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)
/**
* @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \
do { \
__HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE(); \
__HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE(); \
} while(0);
/**
* @brief Check whether the specified AVD EXTI Rising interrupt flag is set or not.
* @retval EXTI AVD Line Status.
*/
#define __HAL_PWR_PVD_AVD_EXTI_GET_RISING_FLAG() ((READ_BIT(EXTI->RPR1, PWR_EXTI_LINE_AVD)\
== PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
/**
* @brief Check whether the specified AVD EXTI Falling interrupt flag is set or not.
* @retval EXTI AVD Line Status.
*/
#define __HAL_PWR_PVD_AVD_EXTI_GET_FALLING_FLAG() ((READ_BIT(EXTI->FPR1, PWR_EXTI_LINE_AVD)\
== PWR_EXTI_LINE_AVD) ? 1UL : 0UL)
/**
* @brief Clear the AVD EXTI flag.
* @retval None.
*/
#define __HAL_PWR_PVD_AVD_EXTI_CLEAR_FLAG() \
do \
{ \
WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVD); \
WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVD); \
} while(0)
/**
* @brief Generates a Software interrupt on AVD EXTI line.
* @retval None.
*/
#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)
/**
* @brief Configure the main internal regulator output voltage.
* @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but
* doesn't check whether or not VOSREADY flag is set. User may resort
* to __HAL_PWR_GET_FLAG() macro to check VOSF bit state.
* @param __REGULATOR__ : Specifies the regulator output voltage to achieve a
* tradeoff between performance and power consumption.
* This parameter can be one of the following values :
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output scale 0.
* Provides a typical output voltage at 1.2 V.
* Used when system clock frequency is up to 160 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1.
* Provides a typical output voltage at 1.1 V.
* Used when system clock frequency is up to 100 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2.
* Provides a typical output voltage at 1.0 V.
* Used when system clock frequency is up to 50 MHz.
* @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3.
* Provides a typical output voltage at 0.9 V.
* Used when system clock frequency is up to 24 MHz.
* @retval None.
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \
do \
{ \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS); \
UNUSED(tmpreg); \
} while(0)
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup PWREx_Private_Constants PWR Extended Private Constants
* @{
*/
/** @defgroup PWREx_AVD_Mode_Mask PWR Extended AVD Mode Mask
* @{
*/
#define AVD_MODE_IT (0x00010000U)
#define AVD_MODE_EVT (0x00020000U)
#define AVD_RISING_EDGE (0x00000001U)
#define AVD_FALLING_EDGE (0x00000002U)
#define AVD_RISING_FALLING_EDGE (0x00000003U)
/**
* @}
*/
/**
* @}
*/
/* Private macros --------------------------------------------------------*/
/** @defgroup PWREx_Private_Macros PWR Extended Private Macros
* @{
*/
/* Check PWR regulator configuration parameter */
#define IS_PWR_SUPPLY(PWR_SOURCE) ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY)
/* Check wake up pin polarity parameter */
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\
((POLARITY) == PWR_PIN_POLARITY_LOW))
/* Check wake up pin pull configuration parameter */
#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\
((PULL) == PWR_PIN_PULL_UP) ||\
((PULL) == PWR_PIN_PULL_DOWN))
/* Check wake up flag parameter */
#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\
((FLAG) == PWR_WAKEUP_FLAG2) ||\
((FLAG) == PWR_WAKEUP_FLAG3) ||\
((FLAG) == PWR_WAKEUP_FLAG4) ||\
((FLAG) == PWR_WAKEUP_FLAG5) ||\
((FLAG) == PWR_WAKEUP_FLAG6) ||\
((FLAG) == PWR_WAKEUP_FLAG_ALL))
/* Voltage scaling range check macro */
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE0) ||\
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
/* Check PWR regulator configuration in STOP mode parameter */
#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3) ||\
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4) ||\
((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))
/* Battery charging resistor selection check macro */
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
/* Check memory block parameter */
#if defined (PWR_PMCR_SRAM2_16SO)
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_ETHERNET_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_16_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
#elif defined (PWR_PMCR_SRAM2_16LSO)
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM3_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_LOW_16_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_HIGH_16_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM2_48_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
#else
#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_RAM2_MEMORY_BLOCK) || \
((BLOCK) == PWR_RAM1_MEMORY_BLOCK))
#endif /* PWR_PMCR_SRAM2_16SO */
/* Check wake up flag parameter */
#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\
((LEVEL) == PWR_AVDLEVEL_1) ||\
((LEVEL) == PWR_AVDLEVEL_2) ||\
((LEVEL) == PWR_AVDLEVEL_3))
/* Check AVD mode parameter */
#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING) ||\
((MODE) == PWR_AVD_MODE_IT_FALLING) ||\
((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING) ||\
((MODE) == PWR_AVD_MODE_EVENT_FALLING) ||\
((MODE) == PWR_AVD_MODE_NORMAL) ||\
((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions
* @{
*/
/** @addtogroup PWREx_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);
uint32_t HAL_PWREx_GetSupplyConfig(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);
uint32_t HAL_PWREx_GetStopModeVoltageRange(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group2
* @{
*/
void HAL_PWREx_ConfigAVD(const PWREx_AVDTypeDef *sConfigAVD);
void HAL_PWREx_EnableAVD(void);
void HAL_PWREx_DisableAVD(void);
#if defined (PWR_USBSCR_USB33DEN)
void HAL_PWREx_EnableUSBVoltageDetector(void);
void HAL_PWREx_DisableUSBVoltageDetector(void);
void HAL_PWREx_EnableVddUSB(void);
void HAL_PWREx_DisableVddUSB(void);
#endif /* PWR_USBSCR_USB33DEN */
void HAL_PWREx_EnableMonitoring(void);
void HAL_PWREx_DisableMonitoring(void);
void HAL_PWREx_EnableUCPDStandbyMode(void);
void HAL_PWREx_DisableUCPDStandbyMode(void);
void HAL_PWREx_EnableUCPDDeadBattery(void);
void HAL_PWREx_DisableUCPDDeadBattery(void);
void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);
void HAL_PWREx_DisableBatteryCharging(void);
void HAL_PWREx_EnableAnalogBooster(void);
void HAL_PWREx_DisableAnalogBooster(void);
void HAL_PWREx_PVD_AVD_IRQHandler(void);
void HAL_PWREx_PVD_AVD_Rising_Callback(void);
void HAL_PWREx_PVD_AVD_Falling_Callback(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group3
* @{
*/
void HAL_PWREx_EnableWakeUpPin(const PWREx_WakeupPinTypeDef *sPinParams);
void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPinx);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group4
* @{
*/
void HAL_PWREx_EnableFlashPowerDown(void);
void HAL_PWREx_DisableFlashPowerDown(void);
void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);
void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);
HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void);
void HAL_PWREx_DisableBkupRAMRetention(void);
/**
* @}
*/
/** @addtogroup PWREx_Exported_Functions_Group5
* @{
*/
void HAL_PWREx_EnableStandbyIORetention(void);
void HAL_PWREx_DisableStandbyIORetention(void);
void HAL_PWREx_EnableStandbyJTAGIORetention(void);
void HAL_PWREx_DisableStandbyJTAGIORetention(void);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* STM32H5xx_HAL_PWR_EX_H */

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/**
******************************************************************************
* @file stm32h5xx_ll_crs.h
* @author MCD Application Team
* @brief Header file of CRS LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_LL_CRS_H
#define STM32H5xx_LL_CRS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx.h"
/** @addtogroup STM32H5xx_LL_Driver
* @{
*/
#if defined(CRS)
/** @defgroup CRS_LL CRS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup CRS_LL_Private_Constants CRS Private Constants
* @{
*/
/* Defines used for the bit position in the register and perform offsets*/
#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
* @{
*/
/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_CRS_ReadReg function
* @{
*/
#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
/**
* @}
*/
/** @defgroup CRS_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
* @{
*/
#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
* @{
*/
#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
* @{
*/
#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
/**
* @}
*/
/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
* @{
*/
#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
/**
* @}
*/
/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
* @{
*/
#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
/**
* @}
*/
/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
* @{
*/
/**
* @brief Reset value of the RELOAD field
* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
*/
#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
/**
* @brief Reset value of Frequency error limit.
*/
#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
/**
* @brief Reset value of the HSI48 Calibration field
* @note The default value is 32, which corresponds to the middle of the trimming interval.
* The trimming step is specified in the product datasheet.
* A higher TRIM value corresponds to a higher output frequency.
*/
#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
* @{
*/
/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
* @{
*/
/**
* @brief Write a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
/**
* @brief Read a value in CRS register
* @param __INSTANCE__ CRS Instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
/**
* @}
*/
/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
* @{
*/
/**
* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
* @note The RELOAD value should be selected according to the ratio between
* the target frequency and the frequency of the synchronization source after
* prescaling. It is then decreased by one in order to reach the expected
* synchronization on the zero value. The formula is the following:
* RELOAD = (fTARGET / fSYNC) -1
* @param __FTARGET__ Target frequency (value in Hz)
* @param __FSYNC__ Synchronization signal frequency (value in Hz)
* @retval Reload value (in Hz)
*/
#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
* @{
*/
/** @defgroup CRS_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable Frequency error counter
* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
{
SET_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Disable Frequency error counter
* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_CEN);
}
/**
* @brief Check if Frequency error counter is enabled or not
* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
}
/**
* @brief Enable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
{
SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Disable Automatic trimming counter
* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
}
/**
* @brief Check if Automatic trimming is enabled or not
* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
}
/**
* @brief Set HSI48 oscillator smooth trimming
* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
* @param Value a number between Min_Data = 0 and Max_Data = 63
* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
}
/**
* @brief Get HSI48 oscillator smooth trimming
* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
* @retval a number between Min_Data = 0 and Max_Data = 63
*/
__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
{
return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
}
/**
* @brief Set counter reload value
* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
}
/**
* @brief Get counter reload value
* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
}
/**
* @brief Set frequency error limit
* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
* @param Value a number between Min_Data = 0 and Max_Data = 255
* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
}
/**
* @brief Get frequency error limit
* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
* @retval A number between Min_Data = 0 and Max_Data = 255
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
}
/**
* @brief Set division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
* @param Divider This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
}
/**
* @brief Get division factor for SYNC signal
* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1
* @arg @ref LL_CRS_SYNC_DIV_2
* @arg @ref LL_CRS_SYNC_DIV_4
* @arg @ref LL_CRS_SYNC_DIV_8
* @arg @ref LL_CRS_SYNC_DIV_16
* @arg @ref LL_CRS_SYNC_DIV_32
* @arg @ref LL_CRS_SYNC_DIV_64
* @arg @ref LL_CRS_SYNC_DIV_128
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
}
/**
* @brief Set SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
* @param Source This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
}
/**
* @brief Get SYNC signal source
* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
* @arg @ref LL_CRS_SYNC_SOURCE_LSE
* @arg @ref LL_CRS_SYNC_SOURCE_USB
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
}
/**
* @brief Set input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
* @param Polarity This parameter can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
{
MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
}
/**
* @brief Get input polarity for the SYNC signal source
* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_SYNC_POLARITY_RISING
* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
*/
__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
{
return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
}
/**
* @brief Configure CRS for the synchronization
* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
* CFGR RELOAD LL_CRS_ConfigSynchronization\n
* CFGR FELIM LL_CRS_ConfigSynchronization\n
* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
* CFGR SYNCPOL LL_CRS_ConfigSynchronization
* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
* @param Settings This parameter can be a combination of the following values:
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64
* or @ref LL_CRS_SYNC_DIV_128
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
* @retval None
*/
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
uint32_t ReloadValue, uint32_t Settings)
{
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
MODIFY_REG(CRS->CFGR,
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
* @{
*/
/**
* @brief Generate software SYNC event
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
}
/**
* @brief Get the frequency error direction latched in the time of the last
* SYNC event
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
* @retval Returned value can be one of the following values:
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
}
/**
* @brief Get the frequency error counter value latched in the time of the last SYNC event
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
*/
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
{
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Check if SYNC event OK signal occurred or not
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC warning signal occurred or not
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
}
/**
* @brief Check if Synchronization or trimming error signal occurred or not
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Check if Expected SYNC signal occurred or not
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC error signal occurred or not
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
}
/**
* @brief Check if SYNC missed error signal occurred or not
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
}
/**
* @brief Check if Trimming overflow or underflow occurred or not
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
{
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
}
/**
* @brief Clear the SYNC event OK flag
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
}
/**
* @brief Clear the SYNC warning flag
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
}
/**
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
* the ERR flag
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
}
/**
* @brief Clear Expected SYNC flag
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
{
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
}
/**
* @}
*/
/** @defgroup CRS_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Disable SYNC event OK interrupt
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
}
/**
* @brief Check if SYNC event OK interrupt is enabled or not
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
}
/**
* @brief Enable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
{
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Disable SYNC warning interrupt
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
}
/**
* @brief Check if SYNC warning interrupt is enabled or not
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
{
SET_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Disable Synchronization or trimming error interrupt
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
}
/**
* @brief Check if Synchronization or trimming error interrupt is enabled or not
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
}
/**
* @brief Enable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
{
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Disable Expected SYNC interrupt
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
* @retval None
*/
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
{
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
}
/**
* @brief Check if Expected SYNC interrupt is enabled or not
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
{
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_CRS_DeInit(void);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
#endif /* defined(CRS) */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_LL_CRS_H */

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/**
******************************************************************************
* @file stm32h5xx_ll_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H5xx_LL_ICACHE_H
#define STM32H5xx_LL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h5xx.h"
/** @addtogroup STM32H5xx_LL_Driver
* @{
*/
#if defined(ICACHE)
/** @defgroup ICACHE_LL ICACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
* @{
*/
/**
* @brief LL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
uint32_t Size; /*!< Configures the region size.
This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
} LL_ICACHE_RegionTypeDef;
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
* @{
*/
#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
* @{
*/
#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
* @{
*/
#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
* @{
*/
#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
* @{
*/
#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_EC_Region Remapped Region number
* @{
*/
#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
* @{
*/
#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
* @{
*/
#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
* @{
*/
#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ICACHE register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
/**
* @brief Read a value in ICACHE register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Enable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Disable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Disable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Disable(void)
{
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Return if ICACHE is enabled or not.
* @rmtoll CR EN LL_ICACHE_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Select the ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_SetMode
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
}
/**
* @brief Get the selected ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_GetMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
{
return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
}
/**
* @brief Invalidate the ICACHE.
* @note Until the BSYEND flag is set, the cache is bypassed.
* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Invalidate(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_Monitors Monitors
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
{
SET_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
{
CLEAR_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Check if the monitor(s) is(are) enabled or disabled.
* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
{
return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the hit/miss monitor(s).
* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
{
/* Reset */
SET_BIT(ICACHE->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
}
/**
* @brief Get the Hit monitor.
* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Miss monitor.
* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Disable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Check if the BSYEND Interrupt is enabled or disabled.
* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Disable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Check if the ERR Interrupt is enabled or disabled.
* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicate the status of an ongoing operation flag.
* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an operation end flag.
* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an error flag.
* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear busy end of operation flag.
* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
}
/**
* @brief Clear error flag.
* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
}
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
* @{
*/
/**
* @brief Enable the remapped memory region.
* @note The region must have been already configured.
* @rmtoll CRRx REN LL_ICACHE_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
{
SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Disable the remapped memory region.
* @rmtoll CRRx REN LL_ICACHE_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
{
CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Return if remapped memory region is enabled or not.
* @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
}
/**
* @brief Select the memory remapped region base address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Alias address in the Code region
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U));
}
/**
* @brief Get the memory remapped region base address.
* @note The base address is the alias in the Code region.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Alias address in the Code region
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR) << 21U);
}
/**
* @brief Select the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Memory address to remap
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
}
/**
* @brief Get the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Remapped memory address
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
}
/**
* @brief Select the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Size This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
}
/**
* @brief Get the selected the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
}
/**
* @brief Select the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Type This parameter can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST, Type);
}
/**
* @brief Get the selected the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST));
}
/**
* @brief Select the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Port This parameter can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL, Port);
}
/**
* @brief Get the selected the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
* @{
*/
void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_LL_ICACHE_H */

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/**
******************************************************************************
* @file stm32h5xx_ll_utils.h
* @author MCD Application Team
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
The LL UTILS driver contains a set of generic APIs that can be
used by user:
(+) Device electronic signature
(+) Timing functions
(+) PLL configuration functions
@endverbatim
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32H5xx_LL_UTILS_H
#define __STM32H5xx_LL_UTILS_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx.h"
/** @addtogroup STM32H5xx_LL_Driver
* @{
*/
/** @defgroup UTILS_LL UTILS
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants
* @{
*/
/* Max delay can be used in LL_mDelay */
#define LL_MAX_DELAY 0xFFFFFFFFU
/**
* @brief Unique device ID register base address
*/
#define UID_BASE_ADDRESS UID_BASE
/**
* @brief Flash size data register base address
*/
#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE
/**
* @brief Package data register base address
*/
#define PACKAGE_BASE_ADDRESS PACKAGE_BASE
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures
* @{
*/
/**
* @brief UTILS PLL structure definition
*/
typedef struct
{
uint32_t PLLM; /*!< Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 1 and Max_Data = 63
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetM(). */
uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 4 and Max_Data = 512
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetN(). */
uint32_t PLLP; /*!< Division for the main system clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 128
odd division factors are not allowed
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetP(). */
uint32_t FRACN; /*!< Fractional part of the multiplication factor for PLL VCO.
This parameter can be a value between 0 and 8191
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetFRACN(). */
uint32_t VCO_Input; /*!< PLL clock Input range.
This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOInputRange(). */
uint32_t VCO_Output; /*!< PLL clock Output range.
This parameter can be a value of @ref RCC_LL_EC_PLLOUTPUTRANGE
This feature can be modified afterwards using unitary function
@ref LL_RCC_PLL1_SetVCOOutputRange(). */
} LL_UTILS_PLLInitTypeDef;
/**
* @brief UTILS System, AHB and APB buses clock configuration structure definition
*/
typedef struct
{
uint32_t SYSCLKDivider; /*!< The System clock (SYSCLK) divider. This clock is derived from the System clock.
This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAHBPrescaler(). */
uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB1_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB1Prescaler(). */
uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB2_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB2Prescaler(). */
uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).
This parameter can be a value of @ref RCC_LL_EC_APB3_DIV
This feature can be modified afterwards using unitary function
@ref LL_RCC_SetAPB3Prescaler(). */
} LL_UTILS_ClkInitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants
* @{
*/
/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation
* @{
*/
#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */
#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass Analog is enabled */
#define LL_UTILS_HSEBYPASS_DIGITAL_ON 0x00000002U /*!< HSE Bypass Digital is enabled */
/**
* @}
*/
/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE
* @{
*/
#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */
#define LL_UTILS_PACKAGETYPE_VFQFPN68 0x00000001U /*!< VFQFPN68 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176 0x00000003U /*!< UFBGA176+25 package type */
#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */
#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000006U /*!< UFBGA169 package type */
#define LL_UTILS_PACKAGETYPE_LQFP176 0x00000007U /*!< LQFP176 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN32 0x00000009U /*!< UFQFPN32 package type */
#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS 0x0000000BU /*!< UFBGA176+25 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS 0x0000000DU /*!< LQFP176 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000EU /*!< UFBGA169 with internal SMPS package type */
#define LL_UTILS_PACKAGETYPE_WLCSP25 0x0000000FU /*!< WLCSP25 package type */
#define LL_UTILS_PACKAGETYPE_UFQFPN48 0x00000010U /*!< UFQFPN48 package type */
#define LL_UTILS_PACKAGETYPE_WLCSP39 0x00000011U /*!< WLCSP39 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000014U /*!< UFBGA100 package type */
#define LL_UTILS_PACKAGETYPE_UFBGA144 0x00000015U /*!< UFBGA144 package type */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions
* @{
*/
/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE
* @{
*/
/**
* @brief Get Word0 of the unique device identifier (UID based on 96 bits)
* @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format
*/
__STATIC_INLINE uint32_t LL_GetUID_Word0(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));
}
/**
* @brief Get Word1 of the unique device identifier (UID based on 96 bits)
* @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40])
*/
__STATIC_INLINE uint32_t LL_GetUID_Word1(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));
}
/**
* @brief Get Word2 of the unique device identifier (UID based on 96 bits)
* @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24]
*/
__STATIC_INLINE uint32_t LL_GetUID_Word2(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));
}
/**
* @brief Get Flash memory size
* @note This bitfield indicates the size of the device Flash memory expressed in
* Kbytes. As an example, 0x040 corresponds to 64 Kbytes.
* @retval FLASH_SIZE[15:0]: Flash memory size
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
* @brief Get Package type
* @retval Returned value can be one of the following values:
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP64
* @arg @ref LL_UTILS_PACKAGETYPE_VFQFPN68
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP48
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN32
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP25
* @arg @ref LL_UTILS_PACKAGETYPE_UFQFPN48
* @arg @ref LL_UTILS_PACKAGETYPE_WLCSP39
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA100
* @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144
* @note Refer to product datasheet for availability of package on a specific device
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
return (uint32_t)(READ_REG(*((uint16_t *)PACKAGE_BASE_ADDRESS)));
}
/**
* @}
*/
/** @defgroup UTILS_LL_EF_DELAY DELAY
* @{
*/
/**
* @brief This function configures the Cortex-M SysTick source of the time base.
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
* configuration by calling this function, for a delay use rather osDelay RTOS service.
* @param Ticks Number of ticks
* @retval None
*/
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
{
/* Configure the SysTick to have interrupt in 1ms time base */
SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */
}
void LL_Init1msTick(uint32_t HCLKFrequency);
void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency);
void LL_Init1msTick_LSE(void);
void LL_Init1msTick_LSI(void);
void LL_mDelay(uint32_t Delay);
/**
* @}
*/
/** @defgroup UTILS_EF_SYSTEM SYSTEM
* @{
*/
void LL_SetSystemCoreClock(uint32_t HCLKFrequency);
ErrorStatus LL_PLL_ConfigSystemClock_CSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,
uint32_t HSEBypass,
LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,
LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);
ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32H5xx_LL_UTILS_H */