diff --git a/.mxproject b/.mxproject
index 192d707..9538cee 100644
--- a/.mxproject
+++ b/.mxproject
@@ -1,15 +1,15 @@
 [PreviousLibFiles]
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+SourceFiles#11=..\Core\Src\main.c
 SourceFolderListSize=2
 SourcePath#0=..\Core\Src
 SourcePath#1=..\AZURE_RTOS\App
diff --git a/AutoGuideStick.ioc b/AutoGuideStick.ioc
index 35e891e..d711c66 100644
--- a/AutoGuideStick.ioc
+++ b/AutoGuideStick.ioc
@@ -21,7 +21,7 @@ GPDMA1.REQUEST_GPDMACH5=GPDMA1_REQUEST_USART1_RX
 GPDMA1.SRCINC_GPDMACH4=DMA_SINC_INCREMENTED
 GPDMA1.TRANSFERALLOCATEDPORTDEST_GPDMACH5=DMA_DEST_ALLOCATED_PORT1
 GPDMA1.TRANSFERALLOCATEDPORTSRC_GPDMACH5=DMA_SRC_ALLOCATED_PORT1
-GPIO.groupedBy=
+GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
 MMTAppRegionsCount=0
 MMTConfigApplied=false
@@ -30,34 +30,46 @@ Mcu.ContextProject=TrustZoneDisabled
 Mcu.Family=STM32H5
 Mcu.IP0=BOOTPATH
 Mcu.IP1=CORTEX_M33_NS
-Mcu.IP10=USART2
-Mcu.IP2=GPDMA1
-Mcu.IP3=MEMORYMAP
-Mcu.IP4=NVIC
-Mcu.IP5=PWR
-Mcu.IP6=RCC
-Mcu.IP7=SYS
-Mcu.IP8=THREADX
-Mcu.IP9=USART1
-Mcu.IPNb=11
+Mcu.IP10=TIM2
+Mcu.IP11=UART5
+Mcu.IP12=USART1
+Mcu.IP13=USART2
+Mcu.IP2=DEBUG
+Mcu.IP3=GPDMA1
+Mcu.IP4=MEMORYMAP
+Mcu.IP5=NVIC
+Mcu.IP6=PWR
+Mcu.IP7=RCC
+Mcu.IP8=SYS
+Mcu.IP9=THREADX
+Mcu.IPNb=14
 Mcu.Name=STM32H563ZITx
 Mcu.Package=LQFP144
 Mcu.Pin0=PH0-OSC_IN(PH0)
-Mcu.Pin1=PA2
-Mcu.Pin10=VP_PWR_VS_LPOM
-Mcu.Pin11=VP_SYS_VS_tim1
-Mcu.Pin12=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault
-Mcu.Pin13=VP_BOOTPATH_VS_BOOTPATH
-Mcu.Pin14=VP_MEMORYMAP_VS_MEMORYMAP
-Mcu.Pin2=PA3
-Mcu.Pin3=PB14
-Mcu.Pin4=PB15
-Mcu.Pin5=VP_CORTEX_M33_NS_VS_Hclk
-Mcu.Pin6=VP_GPDMA1_VS_GPDMACH3
-Mcu.Pin7=VP_GPDMA1_VS_GPDMACH4
-Mcu.Pin8=VP_GPDMA1_VS_GPDMACH5
-Mcu.Pin9=VP_PWR_VS_SECSignals
-Mcu.PinsNb=15
+Mcu.Pin1=PA0
+Mcu.Pin10=PA14(JTCK/SWCLK)
+Mcu.Pin11=PD4
+Mcu.Pin12=PD5
+Mcu.Pin13=VP_CORTEX_M33_NS_VS_Hclk
+Mcu.Pin14=VP_GPDMA1_VS_GPDMACH3
+Mcu.Pin15=VP_GPDMA1_VS_GPDMACH4
+Mcu.Pin16=VP_GPDMA1_VS_GPDMACH5
+Mcu.Pin17=VP_PWR_VS_SECSignals
+Mcu.Pin18=VP_PWR_VS_LPOM
+Mcu.Pin19=VP_SYS_VS_tim1
+Mcu.Pin2=PA1
+Mcu.Pin20=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+Mcu.Pin21=VP_TIM2_VS_ClockSourceINT
+Mcu.Pin22=VP_BOOTPATH_VS_BOOTPATH
+Mcu.Pin23=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.Pin3=PA2
+Mcu.Pin4=PA3
+Mcu.Pin5=PB12
+Mcu.Pin6=PB13
+Mcu.Pin7=PB14
+Mcu.Pin8=PB15
+Mcu.Pin9=PA13(JTMS/SWDIO)
+Mcu.PinsNb=24
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32H563ZITx
@@ -80,19 +92,47 @@ NVIC.SavedSvcallIrqHandlerGenerated=true
 NVIC.SavedSystickIrqHandlerGenerated=true
 NVIC.SysTick_IRQn=true\:14\:0\:false\:false\:false\:false\:false\:true\:false
 NVIC.TIM1_UP_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true
+NVIC.TIM2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true
 NVIC.TimeBase=TIM1_UP_IRQn
 NVIC.TimeBaseIP=TIM1
+NVIC.UART5_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true
 NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true
 NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true
 NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+PA0.GPIOParameters=GPIO_Label
+PA0.GPIO_Label=HC_Trig
+PA0.Locked=true
+PA0.Signal=GPIO_Output
+PA1.GPIOParameters=GPIO_Label
+PA1.GPIO_Label=HC_Echo
+PA1.Locked=true
+PA1.Signal=S_TIM2_CH2
+PA13(JTMS/SWDIO).Mode=Serial_Wire
+PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
+PA14(JTCK/SWCLK).Mode=Serial_Wire
+PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
 PA2.Mode=Asynchronous
 PA2.Signal=USART2_TX
 PA3.Mode=Asynchronous
 PA3.Signal=USART2_RX
+PB12.Mode=Asynchronous
+PB12.Signal=UART5_RX
+PB13.Mode=Asynchronous
+PB13.Signal=UART5_TX
 PB14.Mode=Asynchronous
 PB14.Signal=USART1_TX
 PB15.Mode=Asynchronous
 PB15.Signal=USART1_RX
+PD4.GPIOParameters=GPIO_PuPd,GPIO_Label
+PD4.GPIO_Label=Shake_Motor
+PD4.GPIO_PuPd=GPIO_PULLDOWN
+PD4.Locked=true
+PD4.Signal=GPIO_Output
+PD5.GPIOParameters=GPIO_PuPd,GPIO_Label
+PD5.GPIO_Label=Buzzer
+PD5.GPIO_PuPd=GPIO_PULLDOWN
+PD5.Locked=true
+PD5.Signal=GPIO_Output
 PH0-OSC_IN(PH0).Mode=HSE-External-Clock-Source
 PH0-OSC_IN(PH0).Signal=RCC_OSC_IN
 PinOutPanel.RotationAngle=0
@@ -127,7 +167,7 @@ ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_GPDMA1_Init-GPDMA1-false-HAL-true,4-MX_USART1_UART_Init-USART1-false-HAL-true,5-MX_USART2_UART_Init-USART2-false-HAL-true,6-MX_TIM2_Init-TIM2-false-HAL-true,7-MX_UART5_Init-UART5-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true
 RCC.ADCFreq_Value=250000000
 RCC.AHBFreq_Value=250000000
 RCC.APB1Freq_Value=250000000
@@ -213,6 +253,15 @@ RCC.VCOInputFreq_Value=4000000
 RCC.VCOOutputFreq_Value=500000000
 RCC.VCOPLL2OutputFreq_Value=516000000
 RCC.VCOPLL3OutputFreq_Value=516000000
+SH.S_TIM2_CH2.0=TIM2_CH2,Input_Capture2_from_TI2
+SH.S_TIM2_CH2.ConfNb=1
+THREADX.IPParameters=TX_APP_GENERATE_INIT_CODE
+THREADX.TX_APP_GENERATE_INIT_CODE=false
+TIM2.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2
+TIM2.IPParameters=Channel-Input_Capture2_from_TI2,Prescaler
+TIM2.Prescaler=250 - 1
+UART5.BaudRate=9600
+UART5.IPParameters=BaudRate
 USART1.BaudRate=9600
 USART1.IPParameters=VirtualMode-Asynchronous,BaudRate
 USART1.VirtualMode-Asynchronous=VM_ASYNC
@@ -239,4 +288,6 @@ VP_SYS_VS_tim1.Mode=TIM1
 VP_SYS_VS_tim1.Signal=SYS_VS_tim1
 VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Mode=Core_Default
 VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault.Signal=THREADX_VS_RTOSJjThreadXJjCoreJjDefault
+VP_TIM2_VS_ClockSourceINT.Mode=Internal
+VP_TIM2_VS_ClockSourceINT.Signal=TIM2_VS_ClockSourceINT
 board=custom
diff --git a/Core/Inc/app_threadx.h b/Core/Inc/app_threadx.h
index c06ea0e..fd993c7 100644
--- a/Core/Inc/app_threadx.h
+++ b/Core/Inc/app_threadx.h
@@ -30,12 +30,13 @@ extern "C" {
 
 /* Private includes ----------------------------------------------------------*/
 /* USER CODE BEGIN Includes */
-
+#include "headfile.h"
 /* USER CODE END Includes */
 
 /* Exported types ------------------------------------------------------------*/
 /* USER CODE BEGIN ET */
 
+//extern MotorCommand current_motor_cmd;
 /* USER CODE END ET */
 
 /* Exported constants --------------------------------------------------------*/
@@ -46,7 +47,17 @@ extern "C" {
 /* Private defines -----------------------------------------------------------*/
 
 /* USER CODE BEGIN PD */
+// 新加入的define
+#define EVENT_OBSTACLE_DETECTED    0x01
+#define EVENT_GPS_DATA_READY       0x02
+#define EVENT_BLE_COMMAND_RECEIVED 0x04
+#define IMU_UPDATE_EVENT           0x08
+#define EVENT_LOCATION_UPDATED     0x10
 
+// 对于超声波事件 后续可能会加上去  0x20 ? 
+extern TX_QUEUE ble_tx_queue;
+extern TX_EVENT_FLAGS_GROUP system_events;
+extern MotorCommand current_motor_cmd;
 /* USER CODE END PD */
 
 /* Main thread defines -------------------------------------------------------*/
diff --git a/Core/Inc/main.h b/Core/Inc/main.h
index b6e9665..db2b7e5 100644
--- a/Core/Inc/main.h
+++ b/Core/Inc/main.h
@@ -57,6 +57,14 @@ void Error_Handler(void);
 /* USER CODE END EFP */
 
 /* Private defines -----------------------------------------------------------*/
+#define HC_Trig_Pin GPIO_PIN_0
+#define HC_Trig_GPIO_Port GPIOA
+#define HC_Echo_Pin GPIO_PIN_1
+#define HC_Echo_GPIO_Port GPIOA
+#define Shake_Motor_Pin GPIO_PIN_4
+#define Shake_Motor_GPIO_Port GPIOD
+#define Buzzer_Pin GPIO_PIN_5
+#define Buzzer_GPIO_Port GPIOD
 
 /* USER CODE BEGIN Private defines */
 
diff --git a/Core/Inc/stm32h5xx_it.h b/Core/Inc/stm32h5xx_it.h
index df6e5a0..5ef799a 100644
--- a/Core/Inc/stm32h5xx_it.h
+++ b/Core/Inc/stm32h5xx_it.h
@@ -56,8 +56,10 @@ void GPDMA1_Channel3_IRQHandler(void);
 void GPDMA1_Channel4_IRQHandler(void);
 void GPDMA1_Channel5_IRQHandler(void);
 void TIM1_UP_IRQHandler(void);
+void TIM2_IRQHandler(void);
 void USART1_IRQHandler(void);
 void USART2_IRQHandler(void);
+void UART5_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */
diff --git a/Core/Inc/tim.h b/Core/Inc/tim.h
new file mode 100644
index 0000000..f52bef6
--- /dev/null
+++ b/Core/Inc/tim.h
@@ -0,0 +1,52 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.h
+  * @brief   This file contains all the function prototypes for
+  *          the tim.c file
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __TIM_H__
+#define __TIM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "main.h"
+
+/* USER CODE BEGIN Includes */
+
+/* USER CODE END Includes */
+
+extern TIM_HandleTypeDef htim2;
+
+/* USER CODE BEGIN Private defines */
+
+/* USER CODE END Private defines */
+
+void MX_TIM2_Init(void);
+
+/* USER CODE BEGIN Prototypes */
+
+/* USER CODE END Prototypes */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __TIM_H__ */
+
diff --git a/Core/Inc/usart.h b/Core/Inc/usart.h
index 737091e..c3f7052 100644
--- a/Core/Inc/usart.h
+++ b/Core/Inc/usart.h
@@ -32,6 +32,8 @@ extern "C" {
 
 /* USER CODE END Includes */
 
+extern UART_HandleTypeDef huart5;
+
 extern UART_HandleTypeDef huart1;
 
 extern UART_HandleTypeDef huart2;
@@ -40,6 +42,7 @@ extern UART_HandleTypeDef huart2;
 
 /* USER CODE END Private defines */
 
+void MX_UART5_Init(void);
 void MX_USART1_UART_Init(void);
 void MX_USART2_UART_Init(void);
 
diff --git a/Core/Src/app_threadx.c b/Core/Src/app_threadx.c
index 61b33ba..8db9c28 100644
--- a/Core/Src/app_threadx.c
+++ b/Core/Src/app_threadx.c
@@ -43,6 +43,20 @@
 
 /* Private variables ---------------------------------------------------------*/
 /* USER CODE BEGIN PV */
+/* 全局变量定义 */
+TX_QUEUE ble_tx_queue;
+TX_EVENT_FLAGS_GROUP system_events;
+MotorCommand current_motor_cmd = {0,0};
+_GPSData gps_data;
+
+
+/* 消息队列数据类型 */
+typedef struct
+{
+	uint8_t msg_type;  // 1=GPS数据，2=报警信息，3=状态信息
+	char data[128];
+}BLE_Message;
+
 
 /* USER CODE END PV */
 
diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c
index e58d04a..d0a9936 100644
--- a/Core/Src/gpio.c
+++ b/Core/Src/gpio.c
@@ -34,14 +34,39 @@
 
 /** Configure pins
      PH0-OSC_IN(PH0)   ------> RCC_OSC_IN
+     PA13(JTMS/SWDIO)   ------> DEBUG_JTMS-SWDIO
+     PA14(JTCK/SWCLK)   ------> DEBUG_JTCK-SWCLK
 */
 void MX_GPIO_Init(void)
 {
 
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOH_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOD_CLK_ENABLE();
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(HC_Trig_GPIO_Port, HC_Trig_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin Output Level */
+  HAL_GPIO_WritePin(GPIOD, Shake_Motor_Pin|Buzzer_Pin, GPIO_PIN_RESET);
+
+  /*Configure GPIO pin : HC_Trig_Pin */
+  GPIO_InitStruct.Pin = HC_Trig_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(HC_Trig_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pins : Shake_Motor_Pin Buzzer_Pin */
+  GPIO_InitStruct.Pin = Shake_Motor_Pin|Buzzer_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+  GPIO_InitStruct.Pull = GPIO_PULLDOWN;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(GPIOD, &GPIO_InitStruct);
 
 }
 
diff --git a/Core/Src/main.c b/Core/Src/main.c
index f29348d..b51a831 100644
--- a/Core/Src/main.c
+++ b/Core/Src/main.c
@@ -21,6 +21,7 @@
 #include "main.h"
 #include "gpdma.h"
 #include "memorymap.h"
+#include "tim.h"
 #include "usart.h"
 #include "gpio.h"
 
@@ -93,6 +94,8 @@ int main(void)
   MX_GPDMA1_Init();
   MX_USART1_UART_Init();
   MX_USART2_UART_Init();
+  MX_TIM2_Init();
+  MX_UART5_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
diff --git a/Core/Src/stm32h5xx_it.c b/Core/Src/stm32h5xx_it.c
index 0b32369..c03f86d 100644
--- a/Core/Src/stm32h5xx_it.c
+++ b/Core/Src/stm32h5xx_it.c
@@ -56,6 +56,7 @@
 /* USER CODE END 0 */
 
 /* External variables --------------------------------------------------------*/
+extern TIM_HandleTypeDef htim2;
 extern DMA_NodeTypeDef Node_GPDMA1_Channel5;
 extern DMA_QListTypeDef List_GPDMA1_Channel5;
 extern DMA_HandleTypeDef handle_GPDMA1_Channel5;
@@ -63,6 +64,7 @@ extern DMA_HandleTypeDef handle_GPDMA1_Channel4;
 extern DMA_NodeTypeDef Node_GPDMA1_Channel3;
 extern DMA_QListTypeDef List_GPDMA1_Channel3;
 extern DMA_HandleTypeDef handle_GPDMA1_Channel3;
+extern UART_HandleTypeDef huart5;
 extern UART_HandleTypeDef huart1;
 extern UART_HandleTypeDef huart2;
 extern TIM_HandleTypeDef htim1;
@@ -225,6 +227,20 @@ void TIM1_UP_IRQHandler(void)
   /* USER CODE END TIM1_UP_IRQn 1 */
 }
 
+/**
+  * @brief This function handles TIM2 global interrupt.
+  */
+void TIM2_IRQHandler(void)
+{
+  /* USER CODE BEGIN TIM2_IRQn 0 */
+
+  /* USER CODE END TIM2_IRQn 0 */
+  HAL_TIM_IRQHandler(&htim2);
+  /* USER CODE BEGIN TIM2_IRQn 1 */
+
+  /* USER CODE END TIM2_IRQn 1 */
+}
+
 /**
   * @brief This function handles USART1 global interrupt.
   */
@@ -267,6 +283,20 @@ void USART2_IRQHandler(void)
   /* USER CODE END USART2_IRQn 1 */
 }
 
+/**
+  * @brief This function handles UART5 global interrupt.
+  */
+void UART5_IRQHandler(void)
+{
+  /* USER CODE BEGIN UART5_IRQn 0 */
+
+  /* USER CODE END UART5_IRQn 0 */
+  HAL_UART_IRQHandler(&huart5);
+  /* USER CODE BEGIN UART5_IRQn 1 */
+
+  /* USER CODE END UART5_IRQn 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/Core/Src/tim.c b/Core/Src/tim.c
new file mode 100644
index 0000000..fc0a22a
--- /dev/null
+++ b/Core/Src/tim.c
@@ -0,0 +1,141 @@
+/* USER CODE BEGIN Header */
+/**
+  ******************************************************************************
+  * @file    tim.c
+  * @brief   This file provides code for the configuration
+  *          of the TIM instances.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2025 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+/* USER CODE END Header */
+/* Includes ------------------------------------------------------------------*/
+#include "tim.h"
+
+/* USER CODE BEGIN 0 */
+
+/* USER CODE END 0 */
+
+TIM_HandleTypeDef htim2;
+
+/* TIM2 init function */
+void MX_TIM2_Init(void)
+{
+
+  /* USER CODE BEGIN TIM2_Init 0 */
+
+  /* USER CODE END TIM2_Init 0 */
+
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+  TIM_IC_InitTypeDef sConfigIC = {0};
+
+  /* USER CODE BEGIN TIM2_Init 1 */
+
+  /* USER CODE END TIM2_Init 1 */
+  htim2.Instance = TIM2;
+  htim2.Init.Prescaler = 250 - 1;
+  htim2.Init.CounterMode = TIM_COUNTERMODE_UP;
+  htim2.Init.Period = 4294967295;
+  htim2.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+  htim2.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+  if (HAL_TIM_Base_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+  if (HAL_TIM_ConfigClockSource(&htim2, &sClockSourceConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_TIM_IC_Init(&htim2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim2, &sMasterConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  sConfigIC.ICPolarity = TIM_INPUTCHANNELPOLARITY_RISING;
+  sConfigIC.ICSelection = TIM_ICSELECTION_DIRECTTI;
+  sConfigIC.ICPrescaler = TIM_ICPSC_DIV1;
+  sConfigIC.ICFilter = 0;
+  if (HAL_TIM_IC_ConfigChannel(&htim2, &sConfigIC, TIM_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN TIM2_Init 2 */
+
+  /* USER CODE END TIM2_Init 2 */
+
+}
+
+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(tim_baseHandle->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspInit 0 */
+
+  /* USER CODE END TIM2_MspInit 0 */
+    /* TIM2 clock enable */
+    __HAL_RCC_TIM2_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**TIM2 GPIO Configuration
+    PA1     ------> TIM2_CH2
+    */
+    GPIO_InitStruct.Pin = HC_Echo_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;
+    HAL_GPIO_Init(HC_Echo_GPIO_Port, &GPIO_InitStruct);
+
+    /* TIM2 interrupt Init */
+    HAL_NVIC_SetPriority(TIM2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspInit 1 */
+
+  /* USER CODE END TIM2_MspInit 1 */
+  }
+}
+
+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* tim_baseHandle)
+{
+
+  if(tim_baseHandle->Instance==TIM2)
+  {
+  /* USER CODE BEGIN TIM2_MspDeInit 0 */
+
+  /* USER CODE END TIM2_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_TIM2_CLK_DISABLE();
+
+    /**TIM2 GPIO Configuration
+    PA1     ------> TIM2_CH2
+    */
+    HAL_GPIO_DeInit(HC_Echo_GPIO_Port, HC_Echo_Pin);
+
+    /* TIM2 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(TIM2_IRQn);
+  /* USER CODE BEGIN TIM2_MspDeInit 1 */
+
+  /* USER CODE END TIM2_MspDeInit 1 */
+  }
+}
+
+/* USER CODE BEGIN 1 */
+
+/* USER CODE END 1 */
diff --git a/Core/Src/usart.c b/Core/Src/usart.c
index 661ca38..c6dcf04 100644
--- a/Core/Src/usart.c
+++ b/Core/Src/usart.c
@@ -24,6 +24,7 @@
 
 /* USER CODE END 0 */
 
+UART_HandleTypeDef huart5;
 UART_HandleTypeDef huart1;
 UART_HandleTypeDef huart2;
 DMA_NodeTypeDef Node_GPDMA1_Channel5;
@@ -34,6 +35,49 @@ DMA_NodeTypeDef Node_GPDMA1_Channel3;
 DMA_QListTypeDef List_GPDMA1_Channel3;
 DMA_HandleTypeDef handle_GPDMA1_Channel3;
 
+/* UART5 init function */
+void MX_UART5_Init(void)
+{
+
+  /* USER CODE BEGIN UART5_Init 0 */
+
+  /* USER CODE END UART5_Init 0 */
+
+  /* USER CODE BEGIN UART5_Init 1 */
+
+  /* USER CODE END UART5_Init 1 */
+  huart5.Instance = UART5;
+  huart5.Init.BaudRate = 9600;
+  huart5.Init.WordLength = UART_WORDLENGTH_8B;
+  huart5.Init.StopBits = UART_STOPBITS_1;
+  huart5.Init.Parity = UART_PARITY_NONE;
+  huart5.Init.Mode = UART_MODE_TX_RX;
+  huart5.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart5.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart5.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart5.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart5.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart5, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart5, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN UART5_Init 2 */
+
+  /* USER CODE END UART5_Init 2 */
+
+}
 /* USART1 init function */
 
 void MX_USART1_UART_Init(void)
@@ -129,7 +173,44 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
   GPIO_InitTypeDef GPIO_InitStruct = {0};
   DMA_NodeConfTypeDef NodeConfig= {0};
   RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
-  if(uartHandle->Instance==USART1)
+  if(uartHandle->Instance==UART5)
+  {
+  /* USER CODE BEGIN UART5_MspInit 0 */
+
+  /* USER CODE END UART5_MspInit 0 */
+
+  /** Initializes the peripherals clock
+  */
+    PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_UART5;
+    PeriphClkInitStruct.Uart5ClockSelection = RCC_UART5CLKSOURCE_PCLK1;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* UART5 clock enable */
+    __HAL_RCC_UART5_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**UART5 GPIO Configuration
+    PB12     ------> UART5_RX
+    PB13     ------> UART5_TX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_12|GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF14_UART5;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* UART5 interrupt Init */
+    HAL_NVIC_SetPriority(UART5_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(UART5_IRQn);
+  /* USER CODE BEGIN UART5_MspInit 1 */
+
+  /* USER CODE END UART5_MspInit 1 */
+  }
+  else if(uartHandle->Instance==USART1)
   {
   /* USER CODE BEGIN USART1_MspInit 0 */
 
@@ -347,7 +428,27 @@ void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle)
 void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle)
 {
 
-  if(uartHandle->Instance==USART1)
+  if(uartHandle->Instance==UART5)
+  {
+  /* USER CODE BEGIN UART5_MspDeInit 0 */
+
+  /* USER CODE END UART5_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_UART5_CLK_DISABLE();
+
+    /**UART5 GPIO Configuration
+    PB12     ------> UART5_RX
+    PB13     ------> UART5_TX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_12|GPIO_PIN_13);
+
+    /* UART5 interrupt Deinit */
+    HAL_NVIC_DisableIRQ(UART5_IRQn);
+  /* USER CODE BEGIN UART5_MspDeInit 1 */
+
+  /* USER CODE END UART5_MspDeInit 1 */
+  }
+  else if(uartHandle->Instance==USART1)
   {
   /* USER CODE BEGIN USART1_MspDeInit 0 */
 
diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h
new file mode 100644
index 0000000..5518f44
--- /dev/null
+++ b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_tim.h
@@ -0,0 +1,6571 @@
+/**
+  ******************************************************************************
+  * @file    stm32h5xx_ll_tim.h
+  * @author  MCD Application Team
+  * @brief   Header file of TIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2023 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32H5xx_LL_TIM_H
+#define __STM32H5xx_LL_TIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32h5xx.h"
+
+/** @addtogroup STM32H5xx_LL_Driver
+  * @{
+  */
+
+#if defined (TIM1)  \
+ || defined (TIM2)  \
+ || defined (TIM3)  \
+ || defined (TIM4)  \
+ || defined (TIM5)  \
+ || defined (TIM6)  \
+ || defined (TIM7)  \
+ || defined (TIM8)  \
+ || defined (TIM12) \
+ || defined (TIM13) \
+ || defined (TIM14) \
+ || defined (TIM15) \
+ || defined (TIM16) \
+ || defined (TIM17)
+
+/** @defgroup TIM_LL TIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Variables TIM Private Variables
+  * @{
+  */
+static const uint8_t OFFSET_TAB_CCMRx[] =
+{
+  0x00U,   /* 0: TIMx_CH1  */
+  0x00U,   /* 1: TIMx_CH1N */
+  0x00U,   /* 2: TIMx_CH2  */
+  0x00U,   /* 3: TIMx_CH2N */
+  0x04U,   /* 4: TIMx_CH3  */
+  0x04U,   /* 5: TIMx_CH3N */
+  0x04U,   /* 6: TIMx_CH4  */
+  0x04U,   /* 7: TIMx_CH4N */
+  0x38U,   /* 8: TIMx_CH5  */
+  0x38U    /* 9: TIMx_CH6  */
+
+};
+
+static const uint8_t SHIFT_TAB_OCxx[] =
+{
+  0U,            /* 0: OC1M, OC1FE, OC1PE */
+  0U,            /* 1: - NA */
+  8U,            /* 2: OC2M, OC2FE, OC2PE */
+  0U,            /* 3: - NA */
+  0U,            /* 4: OC3M, OC3FE, OC3PE */
+  0U,            /* 5: - NA */
+  8U,            /* 6: OC4M, OC4FE, OC4PE */
+  0U,            /* 7: - NA */
+  0U,            /* 8: OC5M, OC5FE, OC5PE */
+  8U             /* 9: OC6M, OC6FE, OC6PE */
+};
+
+static const uint8_t SHIFT_TAB_ICxx[] =
+{
+  0U,            /* 0: CC1S, IC1PSC, IC1F */
+  0U,            /* 1: - NA */
+  8U,            /* 2: CC2S, IC2PSC, IC2F */
+  0U,            /* 3: - NA */
+  0U,            /* 4: CC3S, IC3PSC, IC3F */
+  0U,            /* 5: - NA */
+  8U,            /* 6: CC4S, IC4PSC, IC4F */
+  0U,            /* 7: - NA */
+  0U,            /* 8: - NA */
+  0U             /* 9: - NA */
+};
+
+static const uint8_t SHIFT_TAB_CCxP[] =
+{
+  0U,            /* 0: CC1P */
+  2U,            /* 1: CC1NP */
+  4U,            /* 2: CC2P */
+  6U,            /* 3: CC2NP */
+  8U,            /* 4: CC3P */
+  10U,           /* 5: CC3NP */
+  12U,           /* 6: CC4P */
+  14U,           /* 7: CC4NP */
+  16U,           /* 8: CC5P */
+  20U            /* 9: CC6P */
+};
+
+static const uint8_t SHIFT_TAB_OISx[] =
+{
+  0U,            /* 0: OIS1 */
+  1U,            /* 1: OIS1N */
+  2U,            /* 2: OIS2 */
+  3U,            /* 3: OIS2N */
+  4U,            /* 4: OIS3 */
+  5U,            /* 5: OIS3N */
+  6U,            /* 6: OIS4 */
+  7U,            /* 7: OIS4N */
+  8U,            /* 8: OIS5 */
+  10U            /* 9: OIS6 */
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Constants TIM Private Constants
+  * @{
+  */
+
+/* Defines used for the bit position in the register and perform offsets */
+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)
+
+/* Generic bit definitions for TIMx_AF1 register */
+#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */
+#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */
+
+
+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
+#define DT_DELAY_1 ((uint8_t)0x7F)
+#define DT_DELAY_2 ((uint8_t)0x3F)
+#define DT_DELAY_3 ((uint8_t)0x1F)
+#define DT_DELAY_4 ((uint8_t)0x1F)
+
+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
+#define DT_RANGE_1 ((uint8_t)0x00)
+#define DT_RANGE_2 ((uint8_t)0x80)
+#define DT_RANGE_3 ((uint8_t)0xC0)
+#define DT_RANGE_4 ((uint8_t)0xE0)
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+/**
+@endcond
+  */
+
+#define OCREF_CLEAR_SELECT_POS (28U)
+#define OCREF_CLEAR_SELECT_MSK (0x1U << OCREF_CLEAR_SELECT_POS)                /*!< 0x10000000 */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Private_Macros TIM Private Macros
+  * @{
+  */
+/** @brief  Convert channel id into channel index.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval none
+  */
+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4N) ? 7U :\
+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 8U : 9U)
+
+/** @brief  Calculate the deadtime sampling period(in ps).
+  * @param  __TIMCLK__ timer input clock frequency (in Hz).
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval none
+  */
+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \
+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \
+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  TIM Time Base configuration structure definition.
+  */
+typedef struct
+{
+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetPrescaler().*/
+
+  uint32_t CounterMode;       /*!< Specifies the counter mode.
+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetCounterMode().*/
+
+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active
+                                   Auto-Reload Register at the next update event.
+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+                                   Some timer instances may support 32 bits counters. In that case this parameter must
+                                   be a number between 0x0000 and 0xFFFFFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetAutoReload().*/
+
+  uint32_t ClockDivision;     /*!< Specifies the clock division.
+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetClockDivision().*/
+
+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                   reaches zero, an update event is generated and counting restarts
+                                   from the RCR value (N).
+                                   This means in PWM mode that (N+1) corresponds to:
+                                      - the number of PWM periods in edge-aligned mode
+                                      - the number of half PWM period in center-aligned mode
+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and
+                                   Max_Data = 0xFF.
+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and
+                                   Max_Data = 0xFFFF.
+
+                                   This feature can be modified afterwards using unitary function
+                                   @ref LL_TIM_SetRepetitionCounter().*/
+} LL_TIM_InitTypeDef;
+
+/**
+  * @brief  TIM Output Compare configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t OCMode;        /*!< Specifies the output mode.
+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetMode().*/
+
+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
+
+                               This feature can be modified afterwards using unitary functions
+                               @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
+
+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
+
+                               This feature can be modified afterwards using unitary function
+                               LL_TIM_OC_SetCompareCHx (x=1..6).*/
+
+  uint32_t OCPolarity;    /*!< Specifies the output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.
+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetPolarity().*/
+
+
+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+
+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_OC_SetIdleState().*/
+} LL_TIM_OC_InitTypeDef;
+
+/**
+  * @brief  TIM Input Capture configuration structure definition.
+  */
+
+typedef struct
+{
+
+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t ICActiveInput; /*!< Specifies the input.
+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.
+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t ICFilter;      /*!< Specifies the input capture filter.
+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                               This feature can be modified afterwards using unitary function
+                               @ref LL_TIM_IC_SetFilter().*/
+} LL_TIM_IC_InitTypeDef;
+
+
+/**
+  * @brief  TIM Encoder interface configuration structure definition.
+  */
+typedef struct
+{
+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).
+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_SetEncoderMode().*/
+
+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source
+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetActiveInput().*/
+
+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.
+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.
+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
+
+                                 This feature can be modified afterwards using unitary function
+                                 @ref LL_TIM_IC_SetFilter().*/
+
+} LL_TIM_ENCODER_InitTypeDef;
+
+/**
+  * @brief  TIM Hall sensor interface configuration structure definition.
+  */
+typedef struct
+{
+
+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.
+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPolarity().*/
+
+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.
+                                    Prescaler must be set to get a maximum counter period longer than the
+                                    time interval between 2 consecutive changes on the Hall inputs.
+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetPrescaler().*/
+
+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.
+                                    This parameter can be a value of
+                                    @ref TIM_LL_EC_IC_FILTER.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_IC_SetFilter().*/
+
+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.
+                                    A positive pulse (TRGO event) is generated with a programmable delay every time
+                                    a change occurs on the Hall inputs.
+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
+
+                                    This feature can be modified afterwards using unitary function
+                                    @ref LL_TIM_OC_SetCompareCH2().*/
+} LL_TIM_HALLSENSOR_InitTypeDef;
+
+/**
+  * @brief  BDTR (Break and Dead Time) structure definition
+  */
+typedef struct
+{
+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                       programmed. */
+
+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_SetOffStates()
+
+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been
+                                      programmed. */
+
+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
+
+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR
+                                      register has been written, their content is frozen until the next reset.*/
+
+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_OC_SetDeadTime()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been
+                                       programmed. */
+
+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t BreakAFMode;           /*!< Specifies the alternate function mode of the break input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
+
+                                      This feature can be modified afterwards using unitary function
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t Break2AFMode;          /*!< Specifies the alternate function mode of the break2 input.
+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_AFMODE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_ConfigBRK2()
+
+                                      @note Bidirectional break input is only supported by advanced timers instances.
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+
+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
+
+                                      This feature can be modified afterwards using unitary functions
+                                      @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
+
+                                      @note This bit-field can not be modified as long as LOCK level 1 has been
+                                      programmed. */
+} LL_TIM_BDTR_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
+  * @{
+  */
+
+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.
+  * @{
+  */
+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */
+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */
+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */
+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */
+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */
+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */
+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */
+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */
+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */
+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */
+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */
+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */
+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */
+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */
+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */
+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */
+#define LL_TIM_SR_IDXF                         TIM_SR_IDXF          /*!< Index interrupt flag  */
+#define LL_TIM_SR_DIRF                         TIM_SR_DIRF          /*!< Direction Change interrupt flag  */
+#define LL_TIM_SR_IERRF                        TIM_SR_IERRF         /*!< Index Error flag  */
+#define LL_TIM_SR_TERRF                        TIM_SR_TERRF         /*!< Transition Error flag  */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
+  * @{
+  */
+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */
+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
+  * @{
+  */
+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */
+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
+  * @{
+  */
+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */
+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** @defgroup TIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.
+  * @{
+  */
+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */
+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */
+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */
+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */
+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */
+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */
+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */
+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */
+#define LL_TIM_DIER_IDXIE                      TIM_DIER_IDXIE       /*!< Index interrupt enable */
+#define LL_TIM_DIER_DIRIE                      TIM_DIER_DIRIE       /*!< Direction Change interrupt enable */
+#define LL_TIM_DIER_IERRIE                     TIM_DIER_IERRIE      /*!< Index Error interrupt enable */
+#define LL_TIM_DIER_TERRIE                     TIM_DIER_TERRIE      /*!< Transition Error interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
+  * @{
+  */
+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
+  * @{
+  */
+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter stops counting at the next update event */
+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter is not stopped at update event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
+  * @{
+  */
+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!< Counter used as upcounter */
+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */
+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */
+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_1        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */
+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
+  * @{
+  */
+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */
+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
+  * @{
+  */
+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */
+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source
+  * @{
+  */
+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */
+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
+  * @{
+  */
+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */
+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
+  * @{
+  */
+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */
+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */
+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */
+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CHANNEL Channel
+  * @{
+  */
+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */
+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */
+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */
+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */
+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */
+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */
+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */
+#define LL_TIM_CHANNEL_CH4N                    TIM_CCER_CC4NE     /*!< Timer complementary output channel 4 */
+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */
+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
+  * @{
+  */
+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */
+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
+/**
+@endcond
+  */
+
+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
+  * @{
+  */
+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/
+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/
+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/
+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/
+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/
+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/
+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/
+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/
+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
+#define LL_TIM_OCMODE_ASYMMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/
+#define LL_TIM_OCMODE_PULSE_ON_COMPARE         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1)                    /*!<Pulse on Compare mode */
+#define LL_TIM_OCMODE_DIRECTION_OUTPUT         (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!<Direction output mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
+  * @{
+  */
+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/
+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
+  * @{
+  */
+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
+  * @{
+  */
+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
+  * @{
+  */
+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
+  * @{
+  */
+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */
+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */
+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */
+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
+  * @{
+  */
+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
+  * @{
+  */
+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
+  * @{
+  */
+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */
+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/
+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
+  * @{
+  */
+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1)                                   /*!< Encoder mode: Clock plus direction - x2 mode */
+#define LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1     (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2       (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2)                                   /*!< Encoder mode: Directional Clock, x2 mode */
+#define LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12  (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */
+#define LL_TIM_ENCODERMODE_X1_TI1                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */
+#define LL_TIM_ENCODERMODE_X1_TI2                    (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO Trigger Output
+  * @{
+  */
+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */
+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */
+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */
+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */
+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */
+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
+#define LL_TIM_TRGO_ENCODERCLK                 TIM_CR2_MMS_3                                   /*!< Encoder clock signal is used as trigger output */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
+  * @{
+  */
+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */
+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
+  * @{
+  */
+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */
+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */
+#define LL_TIM_SLAVEMODE_COMBINED_GATEDRESET   (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0)   /*!< Combined gated + reset mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops and is reset) as soon as the trigger becomes low.Both startand stop of
+                                                                                        the counter are controlled. */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_SMS_PRELOAD_SOURCE SMS Preload Source
+  * @{
+  */
+#define LL_TIM_SMSPS_TIMUPDATE                 0x00000000U                         /*!< The SMS preload transfer is triggered by the Timer's Update event */
+#define LL_TIM_SMSPS_INDEX                     TIM_SMCR_SMSPS                      /*!< The SMS preload transfer is triggered by the Index event */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TS Trigger Selection
+  * @{
+  */
+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */
+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */
+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */
+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */
+#define LL_TIM_TS_ITR4                         TIM_SMCR_TS_3                                                   /*!< Internal Trigger 4 (ITR4) is used as trigger input */
+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_0)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */
+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */
+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */
+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_3 | TIM_SMCR_TS_2)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */
+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */
+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */
+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */
+#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */
+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
+  * @{
+  */
+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */
+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
+  * @{
+  */
+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */
+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */
+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */
+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
+  * @{
+  */
+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */
+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM1_ETRSOURCE External Trigger Source TIM1
+  * @{
+  */
+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#if defined(COMP1)
+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#endif /* COMP1 */
+#if defined(COMP2)
+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ADC1 analog watchdog 1 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   TIM1_AF1_ETRSEL_2                                           /*!< ADC1 analog watchdog 2 */
+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ADC1 analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_ETRSOURCE External Trigger Source TIM2
+  * @{
+  */
+#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#if defined(COMP1)
+#define LL_TIM_TIM2_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#endif /* COMP1 */
+#if defined(COMP2)
+#define LL_TIM_TIM2_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP2 */
+#define LL_TIM_TIM2_ETRSOURCE_LSE         (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to LSE */
+#if defined(SAI1)
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM1_AF1_ETRSEL_2                                           /*!< ETR input is connected to SAI1_FSA */
+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to SAI1_FSB */
+#endif /* SAI1 */
+#define LL_TIM_TIM2_ETRSOURCE_TIM3_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM3 ETR */
+#if defined(TIM4)
+#define LL_TIM_TIM2_ETRSOURCE_TIM4_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to TIM4 ETR */
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_TIM_TIM2_ETRSOURCE_TIM5_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#if defined(USB_DRD_FS)
+#define LL_TIM_TIM2_ETRSOURCE_USB_SOF     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */
+#elif defined(USB_OTG_HS)
+#define LL_TIM_TIM2_ETRSOURCE_USBHS_SOF   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ETR is connected to USBHS OTG SOF */
+#define LL_TIM_TIM2_ETRSOURCE_USBFS_SOF   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */
+#endif /* USB_DRD_FS */
+#if defined(ETH_NS)
+#define LL_TIM_TIM2_ETRSOURCE_ETH_PPS     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< ETR input is connected to ETH PPS */
+#endif /* ETH_NS */
+#if defined(PLAY1)
+#define LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0  TIM1_AF1_ETRSEL_Msk                                         /*!< ETR input is connected to PLAY1 output 0 */
+#endif /* PLAY1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_ETRSOURCE External Trigger Source TIM3
+  * @{
+  */
+#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#if defined(COMP1)
+#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#endif /* COMP1 */
+#if defined(COMP2)
+#define LL_TIM_TIM3_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP2 */
+#if defined(ADC2)
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2   TIM1_AF1_ETRSEL_2                                           /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ADC2 analog watchdog 3 */
+#endif /* ADC2 */
+#define LL_TIM_TIM3_ETRSOURCE_TIM2_ETR    TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
+#if defined(TIM4)
+#define LL_TIM_TIM3_ETRSOURCE_TIM4_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to TIM4 ETR */
+#endif /* TIM4 */
+#if defined(TIM5)
+#define LL_TIM_TIM3_ETRSOURCE_TIM5_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0)  /*!< ETR input is connected to TIM5 ETR */
+#endif /* TIM5 */
+#if defined(ETH_NS)
+#define LL_TIM_TIM3_ETRSOURCE_ETH_PPS     (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_3 ) /*!< ETR input is connected to ETH PPS */
+#endif /* ETH_NS */
+#if defined(PLAY1)
+#define LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0  TIM1_AF1_ETRSEL_Msk                                         /*!< ETR input is connected to PLAY1 output 0 */
+#endif /* PLAY1 */
+/**
+  * @}
+  */
+
+#if defined(TIM4)
+/** @defgroup TIM_LL_EC_TIM4_ETRSOURCE External Trigger Source TIM4
+  * @{
+  */
+#define LL_TIM_TIM4_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM4_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM4_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP1 && COMP2 */
+#define LL_TIM_TIM4_ETRSOURCE_TIM2_ETR    TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM3 ETR */
+#define LL_TIM_TIM4_ETRSOURCE_TIM3_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM4 ETR */
+#define LL_TIM_TIM4_ETRSOURCE_TIM5_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to TIM5 ETR */
+/**
+  * @}
+  */
+#endif /* TIM4 */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_ETRSOURCE External Trigger Source TIM5
+  * @{
+  */
+#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to SAI2_FSA */
+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to SAI2_FSB */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM5_ETRSOURCE_COMP1       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM5_ETRSOURCE_COMP2       (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP1 && COMP2 */
+#define LL_TIM_TIM5_ETRSOURCE_TIM2_ETR    TIM1_AF1_ETRSEL_3                                           /*!< ETR input is connected to TIM2 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM3_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0)                     /*!< ETR input is connected to TIM3 ETR */
+#define LL_TIM_TIM5_ETRSOURCE_TIM4_ETR    (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1)                     /*!< ETR input is connected to TIM4 ETR */
+#if defined(USB_DRD_FS)
+#define LL_TIM_TIM5_ETRSOURCE_USB_SOF     (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR input is connected to USB SOF */
+#elif defined(USB_OTG_HS)
+#define LL_TIM_TIM5_ETRSOURCE_USBHS_SOF   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2)                     /*!< ETR is connected to USBHS OTG SOF */
+#define LL_TIM_TIM5_ETRSOURCE_USBFS_SOF   (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< ETR is connected to USBFS OTG SOF */
+#endif /* USB_DRD_FS */
+/**
+  * @}
+  */
+#endif /* TIM5 */
+
+#if defined(TIM8)
+/** @defgroup TIM_LL_EC_TIM8_ETRSOURCE External Trigger Source TIM8
+  * @{
+  */
+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /*!< ETR input is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /*!< ETR input is connected to COMP1_OUT */
+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /*!< ETR input is connected to COMP2_OUT */
+#endif /* COMP1 && COMP2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /*!< ADC2 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   TIM1_AF1_ETRSEL_2                                           /*!< ADC2 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /*!< ADC2 analog watchdog 3 */
+#if defined(ADC3)
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /*!< ADC3 analog watchdog 1 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< ADC3 analog watchdog 2 */
+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /*!< ADC3 analog watchdog 3 */
+#endif /* ADC3 */
+/**
+  * @}
+  */
+#endif /* TIM8 */
+
+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
+  * @{
+  */
+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */
+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter
+  * @{
+  */
+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
+  * @{
+  */
+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */
+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
+  * @{
+  */
+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */
+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */
+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSI OSSI
+  * @{
+  */
+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_OSSR OSSR
+  * @{
+  */
+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */
+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
+  * @{
+  */
+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */
+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
+  * @{
+  */
+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */
+#if defined(COMP1)
+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */
+#endif /* COMP1 */
+#if defined(COMP2)
+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */
+#endif /* COMP2 */
+#if defined(PLAY1)
+#define LL_TIM_BKIN_SOURCE_PLAY1               TIM1_AF1_BKCMP3E    /*!< internal signal: PLAY1 output */
+#endif /* PLAY1 */
+#if defined(MDF1)
+#define LL_TIM_BKIN_SOURCE_MDF1                TIM1_AF1_BKDF1BK0E  /*!< internal signal: Digital filter break output */
+#endif /* MDF1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
+  * @{
+  */
+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */
+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK_AFMODE BREAK AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK_AFMODE_INPUT              0x00000000U              /*!< Break input BRK in input mode */
+#define LL_TIM_BREAK_AFMODE_BIDIRECTIONAL      TIM_BDTR_BKBID           /*!< Break input BRK in bidirectional mode */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_BREAK2_AFMODE BREAK2 AF MODE
+  * @{
+  */
+#define LL_TIM_BREAK2_AFMODE_INPUT             0x00000000U             /*!< Break2 input BRK2 in input mode */
+#define LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL     TIM_BDTR_BK2BID         /*!< Break2 input BRK2 in bidirectional mode */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_ReArmBRK(_PARAM_)
+#define LL_TIM_ReArmBRK2(_PARAM_)
+/**
+@endcond
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
+  * @{
+  */
+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2)                                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_DTR2          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_DTR2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_ECR           (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_ECR register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_TISEL register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */
+#define LL_TIM_DMABURST_BASEADDR_OR1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_OR1 register is the DMA base address for DMA burst */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
+  * @{
+  */
+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_19TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 19 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_20TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 20 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_21TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 21 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_22TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 22 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_23TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 23 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_24TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 24 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_25TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3)                                 /*!< Transfer is done to 25 registers starting from the DMA burst base address */
+#define LL_TIM_DMABURST_LENGTH_26TRANSFERS     (TIM_DCR_DBL_4 | TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 26 registers starting from the DMA burst base address */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_DMABURST_SOURCE DMA Burst Source
+  * @{
+  */
+#define LL_TIM_DMA_UPDATE                      TIM_DCR_DBSS_0                                                  /*!< Transfer source is update event */
+#define LL_TIM_DMA_CC1                         TIM_DCR_DBSS_1                                                  /*!< Transfer source is CC1 event */
+#define LL_TIM_DMA_CC2                         (TIM_DCR_DBSS_1 |  TIM_DCR_DBSS_0)                              /*!< Transfer source is CC2 event */
+#define LL_TIM_DMA_CC3                         TIM_DCR_DBSS_2                                                  /*!< Transfer source is CC3 event */
+#define LL_TIM_DMA_CC4                         (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0)                               /*!< Transfer source is CC4 event */
+#define LL_TIM_DMA_COM                         (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1)                               /*!< Transfer source is COM event */
+#define LL_TIM_DMA_TRIGGER                     (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0)              /*!< Transfer source is trigger event */
+/**
+  * @}
+  */
+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM1_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM1_TI1 is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM1_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM1_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM1_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM1_TI1 is connected to COMP2 output */
+#elif defined(COMP1)
+#define LL_TIM_TIM1_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_0                                  /*!< TIM1_TI1 is connected to COMP1 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI1_RMP  TIM2 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM2_TI1 is connected to GPIO */
+#if defined(STM32H503xx)
+#define LL_TIM_TIM2_TI1_RMP_LSI                TIM_TISEL_TI1SEL_0                                  /*!< TIM2_TI1 is connected to LSI */
+#define LL_TIM_TIM2_TI1_RMP_LSE                TIM_TISEL_TI1SEL_1                                  /*!< TIM2_TI1 is connected to LSE */
+#define LL_TIM_TIM2_TI1_RMP_RTC                (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM2_TI1 is connected to RTC */
+#define LL_TIM_TIM2_TI1_RMP_TIM3_TI1           TIM_TISEL_TI1SEL_2                                  /*!< TIM2_TI1 is connected to TIM3 TI1 */
+#endif /* STM32H503xx */
+#if defined(ETH_NS)
+#define LL_TIM_TIM2_TI1_RMP_ETH_PPS            TIM_TISEL_TI1SEL_0                                  /*!< TIM2_TI1 is connected to ETH PPS */
+#endif /* ETH_NS */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM2_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM2_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM2_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM2_TI1 is connected to COMP2 output */
+#define LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3         TIM_TISEL_TI1SEL_2                                  /*!< TIM2_TI1 is connected to PLAY1 output 3 */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI2_RMP  TIM2 External Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI2_RMP_GPIO               0x00000000UL                                        /*!< TIM2_TI2 is connected to GPIO */
+#if defined(STM32H503xx)
+#define LL_TIM_TIM2_TI2_RMP_HSI_1024           TIM_TISEL_TI2SEL_0                                  /*!< TIM2_TI2 is connected to HSI_1024 */
+#define LL_TIM_TIM2_TI2_RMP_CSI_128            TIM_TISEL_TI2SEL_1                                  /*!< TIM2_TI2 is connected to CSI_128 */
+#define LL_TIM_TIM2_TI2_RMP_MCO2               (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0)            /*!< TIM2_TI2 is connected to MCO2 */
+#define LL_TIM_TIM2_TI2_RMP_MCO1               TIM_TISEL_TI2SEL_2                                  /*!< TIM2_TI2 is connected to MCO1 */
+#endif /* STM32H503xx */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM2_TI2_RMP_COMP1              TIM_TISEL_TI2SEL_0                                  /*!< TIM2_TI2 is connected to COMP1 output */
+#define LL_TIM_TIM2_TI2_RMP_COMP2              TIM_TISEL_TI2SEL_1                                  /*!< TIM2_TI2 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 External Input Ch4 Remap
+  * @{
+  */
+#define LL_TIM_TIM2_TI4_RMP_GPIO               0x00000000UL                                        /*!< TIM2_TI4 is connected to GPIO */
+#if defined(STM32H503xx)
+#define LL_TIM_TIM2_TI4_RMP_COMP1              TIM_TISEL_TI4SEL_0                                  /*!< TIM2_TI4 is connected to COMP1 output */
+#endif /* STM32H503xx */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM3_TI1 is connected to GPIO */
+#if defined(STM32H503xx)
+#define LL_TIM_TIM3_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_0                                  /*!< TIM3_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM3_TI1_RMP_MCO1               TIM_TISEL_TI1SEL_1                                  /*!< TIM3_TI1 is connected to MCO1 */
+#define LL_TIM_TIM3_TI1_RMP_TIM2_TI1           (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM3_TI1 is connected to TIM2 TI1 */
+#define LL_TIM_TIM3_TI1_RMP_HSE_1MHZ           TIM_TISEL_TI1SEL_2                                  /*!< TIM3_TI1 is connected to HSE 1MHZ */
+#endif /* STM32H503xx */
+#if defined(ETH_NS)
+#define LL_TIM_TIM3_TI1_RMP_ETH_PPS            TIM_TISEL_TI1SEL_0                                  /*!< TIM3_TI1 is connected to ETH PPS */
+#endif /* ETH_NS */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM3_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM3_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM3_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM3_TI1 is connected to COMP2 output */
+#define LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3         TIM_TISEL_TI1SEL_2                                  /*!< TIM3_TI1 is connected to PLAY1 output 3 */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM3_TI2_RMP  TIM3 External Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM3_TI2_RMP_GPIO               0x00000000UL                                        /*!< TIM3_TI2 is connected to GPIO */
+#if defined(STM32H503xx)
+#define LL_TIM_TIM3_TI2_RMP_CSI_128            TIM_TISEL_TI2SEL_0                                  /*!< TIM3_TI2 is connected to CSI 128 */
+#define LL_TIM_TIM3_TI2_RMP_MCO2               TIM_TISEL_TI2SEL_1                                  /*!< TIM3_TI2 is connected to MCO2 */
+#define LL_TIM_TIM3_TI2_RMP_HSI_1024           (TIM_TISEL_TI2SEL_1 |TIM_TISEL_TI2SEL_0)            /*!< TIM3_TI2 is connected to HSI 1024 */
+#endif /* STM32H503xx */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM3_TI2_RMP_COMP1              TIM_TISEL_TI2SEL_0                                  /*!< TIM3_TI2 is connected to COMP1 output */
+#define LL_TIM_TIM3_TI2_RMP_COMP2              TIM_TISEL_TI2SEL_1                                  /*!< TIM3_TI2 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+#if defined(TIM4)
+/** @defgroup TIM_LL_EC_TIM4_TI1_RMP  TIM4 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM4_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM4_TI1 is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM4_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM4_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM4_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM4_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM4 */
+
+#if defined(TIM5)
+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM5_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM5_TI1 is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM5_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM5_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM5_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM5_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM5 */
+
+#if defined(TIM8)
+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM8_TI1_RMP_GPIO               0x00000000UL                                        /*!< TIM8_TI1 is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM8_TI1_RMP_COMP1              TIM_TISEL_TI1SEL_1                                  /*!< TIM8_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM8_TI1_RMP_COMP2              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM8_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM8 */
+
+#if defined(TIM12)
+/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM12_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM12_TI1 is connected to GPIO */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM12_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_1                                  /*!< TIM12_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM12_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM12_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+#define LL_TIM_TIM12_TI1_RMP_HSI_1024          TIM_TISEL_TI1SEL_2                                  /*!< TIM12_TI1 is connected to HSI 1024 */
+#define LL_TIM_TIM12_TI1_RMP_CSI_128           (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0)            /*!< TIM12_TI1 is connected to CSI 128 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM12_TI2_RMP  TIM12 External Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM12_TI2_RMP_GPIO              0x00000000UL                                        /*!< TIM12_TI2 is connected to GPIO */
+#if defined(COMP2)
+#define LL_TIM_TIM12_TI2_RMP_COMP2             TIM_TISEL_TI2SEL_0                                  /*!< TIM12_TI2 is connected to COMP2 output */
+#endif /* COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM12 */
+
+#if defined(TIM13)
+/** @defgroup TIM_LL_EC_TIM13_TI1_RMP  TIM13 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM13_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM13_TI1 is connected to GPIO */
+#if defined(I3C1)
+#define LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK       TIM_TISEL_TI1SEL_0                                  /*!< TIM13_TI1 is connected to I3C1 IBI ACK */
+#endif /* I3C1 */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM13_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_1                                  /*!< TIM13_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM13_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM13_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM13 */
+
+#if defined(TIM14)
+/** @defgroup TIM_LL_EC_TIM14_TI1_RMP  TIM14 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM14_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM14_TI1 is connected to GPIO */
+#if defined(I3C2)
+#define LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK       TIM_TISEL_TI1SEL_0                                  /*!< TIM14_TI1 is connected to I3C2 IBI ACK */
+#endif /* I3C1 */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM14_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_1                                  /*!< TIM14_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM14_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM14_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM14 */
+
+#if defined(TIM15)
+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM15_TI1 is connected to GPIO */
+#define LL_TIM_TIM15_TI1_RMP_TIM2              TIM_TISEL_TI1SEL_0                                  /*!< TIM15_TI1 is connected to TIM2 */
+#define LL_TIM_TIM15_TI1_RMP_TIM3              TIM_TISEL_TI1SEL_1                                  /*!< TIM15_TI1 is connected to TIM3 */
+#define LL_TIM_TIM15_TI1_RMP_TIM4              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM15_TI1 is connected to TIM4 */
+#define LL_TIM_TIM15_TI1_RMP_LSE               TIM_TISEL_TI1SEL_2                                  /*!< TIM15_TI1 is connected to LSE */
+#define LL_TIM_TIM15_TI1_RMP_CSI_128           (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_0)            /*!< TIM15_TI1 is connected to CSI 128*/
+#define LL_TIM_TIM15_TI1_RMP_MCO2              (TIM_TISEL_TI1SEL_2 |TIM_TISEL_TI1SEL_1)            /*!< TIM15_TI1 is connected to MCO2 */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM15_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_3                                  /*!< TIM15_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM15_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)           /*!< TIM15_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 External Input Ch2 Remap
+  * @{
+  */
+#define LL_TIM_TIM15_TI2_RMP_GPIO              0x00000000UL                                        /*!< TIM15_TI1 is connected to GPIO */
+#define LL_TIM_TIM15_TI2_RMP_TIM2              TIM_TISEL_TI2SEL_0                                  /*!< TIM15_TI2 is connected to TIM2 */
+#define LL_TIM_TIM15_TI2_RMP_TIM3              TIM_TISEL_TI2SEL_1                                  /*!< TIM15_TI2 is connected to TIM3 */
+#define LL_TIM_TIM15_TI2_RMP_TIM4              (TIM_TISEL_TI2SEL_1 | TIM_TISEL_TI2SEL_0)           /*!< TIM15_TI2 is connected to TIM4 */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM15_TI2_RMP_COMP1             TIM_TISEL_TI2SEL_2                                  /*!< TIM15_TI2 is connected to COMP1 output */
+#define LL_TIM_TIM15_TI2_RMP_COMP2             (TIM_TISEL_TI2SEL_2 | TIM_TISEL_TI2SEL_0)           /*!< TIM15_TI2 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM15 */
+
+#if defined(TIM16)
+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM16_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM16_TI1 is connected to GPIO */
+#define LL_TIM_TIM16_TI1_RMP_LSI               TIM_TISEL_TI1SEL_0                                  /*!< TIM16_TI1 is connected to LSI */
+#define LL_TIM_TIM16_TI1_RMP_LSE               TIM_TISEL_TI1SEL_1                                  /*!< TIM16_TI1 is connected to LSE */
+#define LL_TIM_TIM16_TI1_RMP_RTC_WKUP          (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM16_TI1 is connected to RTC */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM16_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_3                                  /*!< TIM16_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM16_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0)           /*!< TIM16_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM16 */
+
+#if defined(TIM17)
+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 External Input Ch1 Remap
+  * @{
+  */
+#define LL_TIM_TIM17_TI1_RMP_GPIO              0x00000000UL                                        /*!< TIM17_TI1 is connected to GPIO */
+#define LL_TIM_TIM17_TI1_RMP_HSE_1MHZ          TIM_TISEL_TI1SEL_1                                  /*!< TIM17_TI1 is connected to HSE 1MHZ */
+#define LL_TIM_TIM17_TI1_RMP_MCO1              (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0)           /*!< TIM17_TI1 is connected to MCO1 */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_TIM17_TI1_RMP_COMP1             TIM_TISEL_TI1SEL_2                                  /*!< TIM17_TI1 is connected to COMP1 output */
+#define LL_TIM_TIM17_TI1_RMP_COMP2             (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0)           /*!< TIM17_TI1 is connected to COMP2 output */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+#endif /* TIM17 */
+
+/** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection
+  * @{
+  */
+#define LL_TIM_OCREF_CLR_INT_ETR         OCREF_CLEAR_SELECT_MSK                   /*!< OCREF_CLR_INT is connected to ETRF */
+#if defined(COMP1) && defined(COMP2)
+#define LL_TIM_OCREF_CLR_INT_COMP1       0x00000000U                              /*!< OCREF clear input is connected to COMP1_OUT */
+#define LL_TIM_OCREF_CLR_INT_COMP2       TIM1_AF2_OCRSEL_0                        /*!< OCREF clear input is connected to COMP2_OUT */
+#endif /* COMP1 && COMP2 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_DIR index direction selection
+  * @{
+  */
+#define LL_TIM_INDEX_UP_DOWN     0x00000000U         /*!< Index resets the counter whatever the direction */
+#define LL_TIM_INDEX_UP          TIM_ECR_IDIR_0      /*!< Index resets the counter when up-counting only */
+#define LL_TIM_INDEX_DOWN        TIM_ECR_IDIR_1      /*!< Index resets the counter when down-counting only */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_BLANK index blanking selection
+  * @{
+  */
+#define LL_TIM_INDEX_BLANK_ALWAYS     0x00000000U         /*!< Index always active */
+#define LL_TIM_INDEX_BLANK_TI3        TIM_ECR_IBLK_0      /*!< Index disabled when TI3 input is active, as per CC3P bitfield */
+#define LL_TIM_INDEX_BLANK_TI4        TIM_ECR_IBLK_1      /*!< Index disabled when TI4 input is active, as per CC4P bitfield */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_INDEX_POSITION index positioning selection
+  * @{
+  */
+#define LL_TIM_INDEX_POSITION_DOWN_DOWN    0x00000000U                           /*!< Index resets the counter when AB = 00 */
+#define LL_TIM_INDEX_POSITION_DOWN_UP      TIM_ECR_IPOS_0                        /*!< Index resets the counter when AB = 01 */
+#define LL_TIM_INDEX_POSITION_UP_DOWN      TIM_ECR_IPOS_1                        /*!< Index resets the counter when AB = 10 */
+#define LL_TIM_INDEX_POSITION_UP_UP        (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0)     /*!< Index resets the counter when AB = 11 */
+#define LL_TIM_INDEX_POSITION_DOWN         0x00000000U                           /*!< Index resets the counter when clock is 0 */
+#define LL_TIM_INDEX_POSITION_UP           TIM_ECR_IPOS_0                        /*!< Index resets the counter when clock is 1 */
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EC_FIRST_INDEX first index selection
+  * @{
+  */
+#define LL_TIM_INDEX_ALL           0x00000000U                           /*!< Index is always active */
+#define LL_TIM_INDEX_FIRST_ONLY    TIM_ECR_FIDX                          /*!< The first Index only resets the counter */
+/**
+  * @}
+  */
+/** @defgroup TIM_LL_EC_PWPRSC Pulse on compare pulse width prescaler
+  * @{
+  */
+#define LL_TIM_PWPRSC_X1     0x00000000U                                              /*!< Pulse on compare pulse width prescaler 1 */
+#define LL_TIM_PWPRSC_X2     TIM_ECR_PWPRSC_0                                         /*!< Pulse on compare pulse width prescaler 2 */
+#define LL_TIM_PWPRSC_X4     TIM_ECR_PWPRSC_1                                         /*!< Pulse on compare pulse width prescaler 4 */
+#define LL_TIM_PWPRSC_X8     (TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 8 */
+#define LL_TIM_PWPRSC_X16    TIM_ECR_PWPRSC_2                                         /*!< Pulse on compare pulse width prescaler 16 */
+#define LL_TIM_PWPRSC_X32    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_0)                    /*!< Pulse on compare pulse width prescaler 32 */
+#define LL_TIM_PWPRSC_X64    (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1)                    /*!< Pulse on compare pulse width prescaler 64 */
+#define LL_TIM_PWPRSC_X128   (TIM_ECR_PWPRSC_2 | TIM_ECR_PWPRSC_1 | TIM_ECR_PWPRSC_0) /*!< Pulse on compare pulse width prescaler 128 */
+/**
+  * @}
+  */
+
+/** Legacy definitions for compatibility purpose
+@cond 0
+  */
+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK
+/**
+@endcond
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
+  * @{
+  */
+
+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+/**
+  * @brief  Write a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in TIM register.
+  * @param  __INSTANCE__ TIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/**
+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.
+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied
+  *        to TIMx_CNT register bit 31)
+  * @param  __CNT__ Counter value
+  * @retval UIF status bit
+  */
+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \
+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
+
+/**
+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CKD__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @param  __DT__ deadtime duration (in ns)
+  * @retval DTG[0:7]
+  */
+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \
+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ?  \
+    (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :      \
+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),   \
+                                                 (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ?  \
+    (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\
+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ?  \
+    (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__),  \
+                                                 (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\
+    0U)
+
+/**
+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __CNTCLK__ counter clock frequency (in Hz)
+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \
+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((((__TIMCLK__) + (__CNTCLK__)/2U)/(__CNTCLK__)) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         output signal frequency.
+  * @note ex: @ref __LL_TIM_CALC_ARR_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10000);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __FREQ__ output signal frequency (in Hz)
+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_ARR_DITHER(__TIMCLK__, __PSC__, __FREQ__) \
+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \
+   (uint32_t)((((uint64_t)(__TIMCLK__) * 16U/((__FREQ__) * ((__PSC__) + 1U))) - 16U)) : 0U)
+
+/**
+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare
+  *         active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer
+  *         output compare active/inactive delay.
+  * @note ex: @ref __LL_TIM_CALC_DELAY_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_DELAY_DITHER(__TIMCLK__, __PSC__, __DELAY__)  \
+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \
+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration
+  *         (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required
+  *         pulse duration (when the timer operates in one pulse mode).
+  * @note ex: @ref __LL_TIM_CALC_PULSE_DITHER (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
+  * @param  __TIMCLK__ timer input clock frequency (in Hz)
+  * @param  __PSC__ prescaler
+  * @param  __DELAY__ timer output compare active/inactive delay (in us)
+  * @param  __PULSE__ pulse duration (in us)
+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)
+  */
+#define __LL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \
+  ((uint32_t)(__LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \
+              + __LL_TIM_CALC_DELAY_DITHER((__TIMCLK__), (__PSC__), (__DELAY__))))
+
+/**
+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler
+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
+  * @param  __ICPSC__ This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)
+  */
+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \
+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
+
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
+  * @{
+  */
+
+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration
+  * @{
+  */
+/**
+  * @brief  Enable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Disable timer counter.
+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
+}
+
+/**
+  * @brief  Indicates whether the timer counter is enabled.
+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Disable update event generation.
+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+}
+
+/**
+  * @brief  Indicates whether update event generation is enabled.
+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent
+  * @param  TIMx Timer instance
+  * @retval Inverted state of bit (0 or 1).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set update event source
+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
+  *       generate an update interrupt or DMA request if enabled:
+  *        - Counter overflow/underflow
+  *        - Setting the UG bit
+  *        - Update generation through the slave mode controller
+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
+  *       overflow/underflow generates an update interrupt or DMA request if enabled.
+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource
+  * @param  TIMx Timer instance
+  * @param  UpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
+}
+
+/**
+  * @brief  Get actual event update source
+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR
+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
+}
+
+/**
+  * @brief  Set one pulse mode (one shot v.s. repetitive).
+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode
+  * @param  TIMx Timer instance
+  * @param  OnePulseMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
+}
+
+/**
+  * @brief  Get actual one pulse mode.
+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
+}
+
+/**
+  * @brief  Set the timer counter counting mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
+  *       requires a timer reset to avoid unexpected direction
+  *       due to DIR bit readonly in center aligned mode.
+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n
+  *         CR1          CMS           LL_TIM_SetCounterMode
+  * @param  TIMx Timer instance
+  * @param  CounterMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
+{
+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);
+}
+
+/**
+  * @brief  Get actual counter mode.
+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
+  *       check whether or not the counter mode selection feature is supported
+  *       by a timer instance.
+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n
+  *         CR1          CMS           LL_TIM_GetCounterMode
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERMODE_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(const TIM_TypeDef *TIMx)
+{
+  uint32_t counter_mode;
+
+  counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CMS));
+
+  if (counter_mode == 0U)
+  {
+    counter_mode = (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+  }
+
+  return counter_mode;
+}
+
+/**
+  * @brief  Enable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Disable auto-reload (ARR) preload.
+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
+}
+
+/**
+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.
+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators
+  *         (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision
+  * @param  TIMx Timer instance
+  * @param  ClockDivision This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
+{
+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
+}
+
+/**
+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time
+  *         generators (when supported) and the digital filters.
+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
+  *       whether or not the clock division feature is supported by the timer
+  *       instance.
+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2
+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
+}
+
+/**
+  * @brief  Set the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_SetCounter
+  * @param  TIMx Timer instance
+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
+{
+  WRITE_REG(TIMx->CNT, Counter);
+}
+
+/**
+  * @brief  Get the counter value.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the Counter value interpretation
+  * @rmtoll CNT          CNT           LL_TIM_GetCounter
+  * @param  TIMx Timer instance
+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CNT));
+}
+
+/**
+  * @brief  Get the current direction of the counter
+  * @rmtoll CR1          DIR           LL_TIM_GetDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP
+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
+}
+
+/**
+  * @brief  Set the prescaler value.
+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
+  * @note The prescaler can be changed on the fly as this control register is buffered. The new
+  *       prescaler ratio is taken into account at the next update event.
+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Prescaler between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
+{
+  WRITE_REG(TIMx->PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the prescaler value.
+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler
+  * @param  TIMx Timer instance
+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->PSC));
+}
+
+/**
+  * @brief  Set the auto-reload value.
+  * @note The counter is blocked while the auto-reload value is null.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
+  *       In case dithering is activated,macro __LL_TIM_CALC_ARR_DITHER can be used instead, to calculate the AutoReload
+  *       parameter.
+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload
+  * @param  TIMx Timer instance
+  * @param  AutoReload between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
+{
+  WRITE_REG(TIMx->ARR, AutoReload);
+}
+
+/**
+  * @brief  Get the auto-reload value.
+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note If dithering is activated, pay attention to the returned value interpretation
+  * @param  TIMx Timer instance
+  * @retval Auto-reload value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->ARR));
+}
+
+/**
+  * @brief  Set the repetition counter value.
+  * @note For advanced timer instances RepetitionCounter can be up to 65535.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
+{
+  WRITE_REG(TIMx->RCR, RepetitionCounter);
+}
+
+/**
+  * @brief  Get the repetition counter value.
+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a repetition counter.
+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter
+  * @param  TIMx Timer instance
+  * @retval Repetition counter value
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->RCR));
+}
+
+/**
+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read
+  *       in an atomic way.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Disable update interrupt flag (UIF) remapping.
+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.
+  * @param  Counter Counter value
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(const uint32_t Counter)
+{
+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_EnableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDithering(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Disable dithering.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_DisableDithering
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDithering(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR1, TIM_CR1_DITHEN);
+}
+
+/**
+  * @brief  Indicates whether dithering is activated.
+  * @note Macro IS_TIM_DITHERING_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides dithering.
+  * @rmtoll CR1          DITHEN          LL_TIM_IsEnabledDithering
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDithering(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR1, TIM_CR1_DITHEN) == (TIM_CR1_DITHEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
+  * @{
+  */
+/**
+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
+  *       they are updated only when a commutation event (COM) occurs.
+  * @note Only on channels that have a complementary output.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
+  * @rmtoll CR2          CCPC          LL_TIM_CC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance is able to generate a commutation event.
+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate
+  * @param  TIMx Timer instance
+  * @param  CCUpdateSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
+}
+
+/**
+  * @brief  Set the trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @param  DMAReqTrigger This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
+}
+
+/**
+  * @brief  Get actual trigger of the capture/compare DMA request.
+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC
+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
+}
+
+/**
+  * @brief  Set the lock level to freeze the
+  *         configuration of several capture/compare parameters.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       the lock mechanism is supported by a timer instance.
+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel
+  * @param  TIMx Timer instance
+  * @param  LockLevel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF
+  *         @arg @ref LL_TIM_LOCKLEVEL_1
+  *         @arg @ref LL_TIM_LOCKLEVEL_2
+  *         @arg @ref LL_TIM_LOCKLEVEL_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
+}
+
+/**
+  * @brief  Enable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_EnableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_EnableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  SET_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Disable capture/compare channels.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_DisableChannel\n
+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n
+  *         CCER         CC6E          LL_TIM_CC_DisableChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  CLEAR_BIT(TIMx->CCER, Channels);
+}
+
+/**
+  * @brief  Indicate whether channel(s) is(are) enabled.
+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC4NE         LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n
+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel
+  * @param  TIMx Timer instance
+  * @param  Channels This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
+{
+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure an output channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n
+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n
+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n
+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Define the behavior of the output reference signal OCxREF from which
+  *         OCx and OCxN (when relevant) are derived.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_SetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Get the output compare mode of an output channel.
+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n
+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n
+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n
+  *         CCMR3        OC6M          LL_TIM_OC_GetMode
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCMODE_FROZEN
+  *         @arg @ref LL_TIM_OCMODE_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_TOGGLE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
+  *         @arg @ref LL_TIM_OCMODE_PWM1
+  *         @arg @ref LL_TIM_OCMODE_PWM2
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
+  *         @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
+  *         @arg @ref LL_TIM_OCMODE_PULSE_ON_COMPARE   (for channel 3 or channel 4 only)
+  *         @arg @ref LL_TIM_OCMODE_DIRECTION_OUTPUT   (for channel 3 or channel 4 only)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
+}
+
+/**
+  * @brief  Set the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_SetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the polarity of an output channel.
+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_OC_GetPolarity\n
+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n
+  *         CCER         CC6P          LL_TIM_OC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH
+  *         @arg @ref LL_TIM_OCPOLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the IDLE state of an output channel
+  * @note This function is significant only for the timer instances
+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)
+  *       can be used to check whether or not a timer instance provides
+  *       a break input.
+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_SetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @param  IdleState This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Get the IDLE state of an output channel
+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS4N         LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n
+  *         CR2         OIS6          LL_TIM_OC_GetIdleState
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH1N
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH2N
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH3N
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH4N
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW
+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
+}
+
+/**
+  * @brief  Enable fast mode for the output channel.
+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Disable fast mode for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
+
+}
+
+/**
+  * @brief  Indicates whether fast mode is enabled for the output channel.
+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n
+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n
+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Disable clearing the output channel on an external event.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
+}
+
+/**
+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.
+  * @note This function enables clearing the output channel on an external event.
+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance can clear the OCxREF signal on an external event.
+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n
+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  *         @arg @ref LL_TIM_CHANNEL_CH5
+  *         @arg @ref LL_TIM_CHANNEL_CH6
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of
+  *         the Ocx and OCxN signals).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
+}
+
+/**
+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR1, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR2, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR3, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).
+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR4, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);
+}
+
+/**
+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, CompareValue can be calculated with macro @ref __LL_TIM_CALC_DELAY_DITHER .
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6
+  * @param  TIMx Timer instance
+  * @param  CompareValue between Min_Data=0 and Max_Data=65535
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
+{
+  WRITE_REG(TIMx->CCR6, CompareValue);
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.
+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.
+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 5 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));
+}
+
+/**
+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.
+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
+  *       output channel 6 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6
+  * @param  TIMx Timer instance
+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR6));
+}
+
+/**
+  * @brief  Select on which reference signal the OC5REF is combined to.
+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the combined 3-phase PWM mode.
+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n
+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels
+  * @param  TIMx Timer instance
+  * @param  GroupCH5 This parameter can be a combination of the following values:
+  *         @arg @ref LL_TIM_GROUPCH5_NONE
+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC
+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
+{
+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_SetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @param  PulseWidthPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidthPrescaler(TIM_TypeDef *TIMx, uint32_t PulseWidthPrescaler)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PWPRSC, PulseWidthPrescaler);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width prescaler.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PWPRSC           LL_TIM_OC_GetPulseWidthPrescaler
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_PWPRSC_X1
+  *         @arg @ref LL_TIM_PWPRSC_X2
+  *         @arg @ref LL_TIM_PWPRSC_X4
+  *         @arg @ref LL_TIM_PWPRSC_X8
+  *         @arg @ref LL_TIM_PWPRSC_X16
+  *         @arg @ref LL_TIM_PWPRSC_X32
+  *         @arg @ref LL_TIM_PWPRSC_X64
+  *         @arg @ref LL_TIM_PWPRSC_X128
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidthPrescaler(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PWPRSC));
+}
+
+/**
+  * @brief  Set the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_SetPulseWidth
+  * @param  TIMx Timer instance
+  * @param  PulseWidth This parameter can be between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_OC_SetPulseWidth(TIM_TypeDef *TIMx, uint32_t PulseWidth)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_PW, PulseWidth << TIM_ECR_PW_Pos);
+}
+
+/**
+  * @brief  Get the pulse on compare pulse width duration.
+  * @note Macro IS_TIM_PULSEONCOMPARE_INSTANCE(TIMx) can be used to check
+  *       whether or not the pulse on compare feature is supported by the timer
+  *       instance.
+  * @rmtoll ECR          PW           LL_TIM_OC_GetPulseWidth
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_OC_GetPulseWidth(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_PW));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
+  * @{
+  */
+/**
+  * @brief  Configure input channel.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n
+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC1F          LL_TIM_IC_Config\n
+  *         CCMR1        CC2S          LL_TIM_IC_Config\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n
+  *         CCMR1        IC2F          LL_TIM_IC_Config\n
+  *         CCMR2        CC3S          LL_TIM_IC_Config\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC3F          LL_TIM_IC_Config\n
+  *         CCMR2        CC4S          LL_TIM_IC_Config\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n
+  *         CCMR2        IC4F          LL_TIM_IC_Config\n
+  *         CCER         CC1P          LL_TIM_IC_Config\n
+  *         CCER         CC1NP         LL_TIM_IC_Config\n
+  *         CCER         CC2P          LL_TIM_IC_Config\n
+  *         CCER         CC2NP         LL_TIM_IC_Config\n
+  *         CCER         CC3P          LL_TIM_IC_Config\n
+  *         CCER         CC3NP         LL_TIM_IC_Config\n
+  *         CCER         CC4P          LL_TIM_IC_Config\n
+  *         CCER         CC4NP         LL_TIM_IC_Config
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))                \
+             << SHIFT_TAB_ICxx[iChannel]);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Set the active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICActiveInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current active input.
+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n
+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the prescaler of input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the current prescaler value acting on an  input channel.
+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n
+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_ICPSC_DIV1
+  *         @arg @ref LL_TIM_ICPSC_DIV2
+  *         @arg @ref LL_TIM_ICPSC_DIV4
+  *         @arg @ref LL_TIM_ICPSC_DIV8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
+}
+
+/**
+  * @brief  Get the input filter duration.
+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n
+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n
+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
+}
+
+/**
+  * @brief  Set the input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @param  ICPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Get the current input channel polarity.
+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n
+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity
+  * @param  TIMx Timer instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CHANNEL_CH1
+  *         @arg @ref LL_TIM_CHANNEL_CH2
+  *         @arg @ref LL_TIM_CHANNEL_CH3
+  *         @arg @ref LL_TIM_CHANNEL_CH4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_IC_POLARITY_RISING
+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING
+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(const TIM_TypeDef *TIMx, uint32_t Channel)
+{
+  uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
+          SHIFT_TAB_CCxP[iChannel]);
+}
+
+/**
+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
+}
+
+/**
+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance provides an XOR input.
+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get captured value for input channel 1.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 1 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR1));
+}
+
+/**
+  * @brief  Get captured value for input channel 2.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 2 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR2));
+}
+
+/**
+  * @brief  Get captured value for input channel 3.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 3 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR3));
+}
+
+/**
+  * @brief  Get captured value for input channel 4.
+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports a 32 bits counter.
+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
+  *       input channel 4 is supported by a timer instance.
+  * @note If dithering is activated, pay attention to the returned value interpretation.
+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4
+  * @param  TIMx Timer instance
+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
+  */
+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_REG(TIMx->CCR4));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
+  * @{
+  */
+/**
+  * @brief  Enable external clock mode 2.
+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Disable external clock mode 2.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
+}
+
+/**
+  * @brief  Indicate whether external clock mode 2 is enabled.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the clock source of the counter clock.
+  * @note when selected clock source is external clock mode 1, the timer input
+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
+  *       function. This timer input must be configured by calling
+  *       the @ref LL_TIM_IC_Config() function.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode1.
+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports external clock mode2.
+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n
+  *         SMCR         ECE           LL_TIM_SetClockSource
+  * @param  TIMx Timer instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
+}
+
+/**
+  * @brief  Set the encoder interface mode.
+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the encoder mode.
+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode
+  * @param  TIMx Timer instance
+  * @param  EncoderMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2
+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X2
+  *         @arg @ref LL_TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI1
+  *         @arg @ref LL_TIM_ENCODERMODE_X1_TI2
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
+  * @{
+  */
+/**
+  * @brief  Set the trigger output (TRGO) used for timer synchronization .
+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can operate as a master timer.
+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput
+  * @param  TIMx Timer instance
+  * @param  TimerSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO_RESET
+  *         @arg @ref LL_TIM_TRGO_ENABLE
+  *         @arg @ref LL_TIM_TRGO_UPDATE
+  *         @arg @ref LL_TIM_TRGO_CC1IF
+  *         @arg @ref LL_TIM_TRGO_OC1REF
+  *         @arg @ref LL_TIM_TRGO_OC2REF
+  *         @arg @ref LL_TIM_TRGO_OC3REF
+  *         @arg @ref LL_TIM_TRGO_OC4REF
+  *         @arg @ref LL_TIM_TRGO_ENCODERCLK
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
+}
+
+/**
+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .
+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance can be used for ADC synchronization.
+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2
+  * @param  TIMx Timer Instance
+  * @param  ADCSynchronization This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TRGO2_RESET
+  *         @arg @ref LL_TIM_TRGO2_ENABLE
+  *         @arg @ref LL_TIM_TRGO2_UPDATE
+  *         @arg @ref LL_TIM_TRGO2_CC1F
+  *         @arg @ref LL_TIM_TRGO2_OC1
+  *         @arg @ref LL_TIM_TRGO2_OC2
+  *         @arg @ref LL_TIM_TRGO2_OC3
+  *         @arg @ref LL_TIM_TRGO2_OC4
+  *         @arg @ref LL_TIM_TRGO2_OC5
+  *         @arg @ref LL_TIM_TRGO2_OC6
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
+{
+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
+}
+
+/**
+  * @brief  Set the synchronization mode of a slave timer.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode
+  * @param  TIMx Timer instance
+  * @param  SlaveMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED
+  *         @arg @ref LL_TIM_SLAVEMODE_RESET
+  *         @arg @ref LL_TIM_SLAVEMODE_GATED
+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_GATEDRESET
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
+}
+
+/**
+  * @brief  Set the selects the trigger input to be used to synchronize the counter.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput
+  * @param  TIMx Timer instance
+  * @param  TriggerInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_TS_ITR0
+  *         @arg @ref LL_TIM_TS_ITR1
+  *         @arg @ref LL_TIM_TS_ITR2
+  *         @arg @ref LL_TIM_TS_ITR3
+  *         @arg @ref LL_TIM_TS_ITR4
+  *         @arg @ref LL_TIM_TS_ITR5
+  *         @arg @ref LL_TIM_TS_ITR6
+  *         @arg @ref LL_TIM_TS_ITR7
+  *         @arg @ref LL_TIM_TS_ITR8
+  *         @arg @ref LL_TIM_TS_ITR9
+  *         @arg @ref LL_TIM_TS_ITR10
+  *         @arg @ref LL_TIM_TS_ITR11
+  *         @arg @ref LL_TIM_TS_ITR12
+  *         @arg @ref LL_TIM_TS_TI1F_ED
+  *         @arg @ref LL_TIM_TS_TI1FP1
+  *         @arg @ref LL_TIM_TS_TI2FP2
+  *         @arg @ref LL_TIM_TS_ETRF
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
+}
+
+/**
+  * @brief  Enable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief  Disable the Master/Slave mode.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
+}
+
+/**
+  * @brief Indicates whether the Master/Slave mode is enabled.
+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
+  * a timer instance can operate as a slave timer.
+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure the external trigger (ETR) input.
+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an external trigger input.
+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n
+  *         SMCR         ETPS          LL_TIM_ConfigETR\n
+  *         SMCR         ETF           LL_TIM_ConfigETR
+  * @param  TIMx Timer instance
+  * @param  ETRPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED
+  * @param  ETRPrescaler This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4
+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8
+  * @param  ETRFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
+                                      uint32_t ETRFilter)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
+}
+
+/**
+  * @brief  Select the external trigger (ETR) input source.
+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports ETR source selection.
+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource
+  * @param  TIMx Timer instance
+  * @param  ETRSource This parameter can be one of the following values:
+  *
+  *         TIM1: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2
+  *            @arg @ref LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3
+  *
+  *         TIM2: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_LSE
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSA   (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_SAI1_FSB   (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM3_ETR
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM4_ETR   (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_TIM5_ETR   (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_USB_SOF    (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_USBHS_SOF  (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_USBFS_SOF  (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_ETH_PPS    (*)
+  *            @arg @ref LL_TIM_TIM2_ETRSOURCE_PLAY1_OUT0 (*)
+  *
+  *         TIM3: any combination of ETR_RMP where
+  *
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD1  (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD2  (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ADC2_AWD3  (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM2_ETR
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM4_ETR   (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_TIM5_ETR   (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_ETH_PPS    (*)
+  *            @arg @ref LL_TIM_TIM3_ETRSOURCE_PLAY1_OUT0 (*)
+  *
+  *         TIM4: any combination of ETR_RMP where     (**)
+  *
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM2_ETR
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM3_ETR
+  *            @arg @ref LL_TIM_TIM4_ETRSOURCE_TIM5_ETR
+  *
+  *         TIM5: any combination of ETR_RMP where   (**)
+  *
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSA
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_SAI2_FSB
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM2_ETR
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM3_ETR
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_TIM4_ETR
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_USB_SOF    (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_USBHS_SOF  (*)
+  *            @arg @ref LL_TIM_TIM5_ETRSOURCE_USBFS_SOF  (*)
+  *
+  *         TIM8: any combination of ETR_RMP where  (**)
+  *
+  *            . . ETR_RMP can be one of the following values
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_GPIO
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP1      (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_COMP2      (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1  (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2  (*)
+  *            @arg @ref LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3  (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Timer instance not available on all devices. \n
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)
+{
+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);
+}
+
+/**
+  * @brief  Enable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_EnableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableSMSPreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Disable SMS preload.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_DisableSMSPreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableSMSPreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_SMSPE);
+}
+
+/**
+  * @brief  Indicate whether  SMS preload is enabled.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPE           LL_TIM_IsEnabledSMSPreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledSMSPreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPE) == (TIM_SMCR_SMSPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_SetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @param  PreloadSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetSMSPreloadSource(TIM_TypeDef *TIMx, uint32_t PreloadSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMSPS, PreloadSource);
+}
+
+/**
+  * @brief  Get the preload source of SMS.
+  * @note Macro IS_TIM_SMS_PRELOAD_INSTANCE(TIMx) can be used to check
+  *       whether or not a timer instance supports the preload of SMS field in SMCR register.
+  * @rmtoll SMCR         SMSPS        LL_TIM_GetSMSPreloadSource\n
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_SMSPS_TIMUPDATE
+  *         @arg @ref LL_TIM_SMSPS_INDEX
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetSMSPreloadSource(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->SMCR, TIM_SMCR_SMSPS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Break_Function Break function configuration
+  * @{
+  */
+/**
+  * @brief  Enable the break function.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Disable the break function.
+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK
+  * @param  TIMx Timer instance
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
+}
+
+/**
+  * @brief  Configure the break input.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BKBID bit set), the Break input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, BreakAFMode must be set to
+  *       LL_TIM_BREAK_AFMODE_INPUT.
+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n
+  *         BDTR         BKF           LL_TIM_ConfigBRK\n
+  *         BDTR         BKBID         LL_TIM_ConfigBRK
+  * @param  TIMx Timer instance
+  * @param  BreakPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH
+  * @param  BreakFilter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
+  * @param  BreakAFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter,
+                                      uint32_t BreakAFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF | TIM_BDTR_BKBID, BreakPolarity | BreakFilter | BreakAFMode);
+}
+
+/**
+  * @brief  Disarm the break input (when it operates in bidirectional mode).
+  * @note  The break input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output .
+  * @rmtoll BDTR         BKDSRM        LL_TIM_DisarmBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
+}
+
+/**
+  * @brief  Enable the break 2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Disable the break  2 function.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
+}
+
+/**
+  * @brief  Configure the break 2 input.
+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a second break input.
+  * @note Bidirectional mode is only supported by advanced timer instances.
+  *       Macro IS_TIM_ADVANCED_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance is an advanced-control timer.
+  * @note In bidirectional mode (BK2BID bit set), the Break 2 input is configured both
+  *        in input mode and in open drain output mode. Any active Break event will
+  *        assert a low logic level on the Break 2 input to indicate an internal break
+  *        event to external devices.
+  * @note When bidirectional mode isn't supported, Break2AFMode must be set to
+  *       LL_TIM_BREAK2_AFMODE_INPUT.
+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2F          LL_TIM_ConfigBRK2\n
+  *         BDTR         BK2BID        LL_TIM_ConfigBRK2
+  * @param  TIMx Timer instance
+  * @param  Break2Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW
+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
+  * @param  Break2Filter This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
+  * @param  Break2AFMode This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_INPUT
+  *         @arg @ref LL_TIM_BREAK2_AFMODE_BIDIRECTIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter,
+                                       uint32_t Break2AFMode)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F | TIM_BDTR_BK2BID, Break2Polarity | Break2Filter | Break2AFMode);
+}
+
+/**
+  * @brief  Disarm the break 2 input (when it operates in bidirectional mode).
+  * @note  The break 2 input can be disarmed only when it is configured in
+  *        bidirectional mode and when when MOE is reset.
+  * @note  Purpose is to be able to have the input voltage back to high-state,
+  *        whatever the time constant on the output.
+  * @rmtoll BDTR         BK2DSRM       LL_TIM_DisarmBRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
+}
+
+/**
+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n
+  *         BDTR         OSSR          LL_TIM_SetOffStates
+  * @param  TIMx Timer instance
+  * @param  OffStateIdle This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSI_DISABLE
+  *         @arg @ref LL_TIM_OSSI_ENABLE
+  * @param  OffStateRun This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OSSR_DISABLE
+  *         @arg @ref LL_TIM_OSSR_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
+{
+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
+}
+
+/**
+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Disable automatic output (MOE can be set only by software).
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
+}
+
+/**
+  * @brief  Indicate whether automatic output is enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).
+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
+  *       software and is reset in case of break or break2 event.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
+}
+
+/**
+  * @brief  Indicates whether outputs are enabled.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides a break input.
+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKCMP3E       LL_TIM_EnableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2CMP3E      LL_TIM_EnableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_PLAY1      (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_MDF1       (*)
+  *
+  *         (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  SET_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Disable the signals connected to the designated timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKCMP3E       LL_TIM_DisableBreakInputSource\n
+  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2CMP3E      LL_TIM_DisableBreakInputSource\n
+  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_PLAY1      (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_MDF1       (*)
+  *
+  *         (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  CLEAR_BIT(*pReg, Source);
+}
+
+/**
+  * @brief  Set the polarity of the break signal for the timer break input.
+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
+  *       or not a timer instance allows for break input selection.
+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF1          BKCMP3P       LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity\n
+  *         AF2          BK2CMP3P      LL_TIM_SetBreakInputSourcePolarity
+  * @param  TIMx Timer instance
+  * @param  BreakInput This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN
+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2
+  * @param  Source This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2    (*)
+  *         @arg @ref LL_TIM_BKIN_SOURCE_PLAY1      (*)
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW
+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH
+  *
+  *         (*)  Value not defined in all devices.
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
+                                                        uint32_t Polarity)
+{
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));
+}
+/**
+  * @brief  Enable asymmetrical deadtime.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_EnableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Disable asymmetrical dead-time.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_DisableAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableAsymmetricalDeadTime(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTAE);
+}
+
+/**
+  * @brief  Indicates whether asymmetrical deadtime is activated.
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides asymmetrical deadtime.
+  * @rmtoll DTR2          DTAE          LL_TIM_IsEnabledAsymmetricalDeadTime
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAsymmetricalDeadTime(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTAE) == (TIM_DTR2_DTAE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and the
+  *         rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2         DTGF           LL_TIM_SetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @param  DeadTime between Min_Data=0 and Max_Data=255
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetFallingDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
+{
+  MODIFY_REG(TIMx->DTR2, TIM_DTR2_DTGF, DeadTime);
+}
+
+/**
+  * @brief  Get the falling edge dead-time delay (delay inserted between the falling edge of the OCxREF signal and
+  *         the rising edge of OCxN signals).
+  * @note Macro IS_TIM_DEADTIME_ASYMMETRICAL_INSTANCE(TIMx) can be used to check whether or not
+  *       asymmetrical dead-time insertion feature is supported by a timer instance.
+  * @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed
+  *       (LOCK bits in TIMx_BDTR register).
+  * @rmtoll DTR2          DTGF           LL_TIM_GetFallingDeadTime
+  * @param  TIMx Timer instance
+  * @retval Returned value can be between Min_Data=0 and Max_Data=255:
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetFallingDeadTime(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->DTR2, TIM_DTR2_DTGF));
+}
+
+/**
+  * @brief  Enable deadtime preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_EnableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Disable dead-time preload.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_DisableDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDeadTimePreload(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DTR2, TIM_DTR2_DTPE);
+}
+
+/**
+  * @brief  Indicates whether deadtime preload is activated.
+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides deadtime preload.
+  * @rmtoll DTR2          DTPE          LL_TIM_IsEnabledDeadTimePreload
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDeadTimePreload(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DTR2, TIM_DTR2_DTPE) == (TIM_DTR2_DTPE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
+  * @{
+  */
+/**
+  * @brief  Configures the timer DMA burst feature.
+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
+  *       not a timer instance supports the DMA burst mode.
+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n
+  *         DCR          DBA           LL_TIM_ConfigDMABurst
+  * @param  TIMx Timer instance
+  * @param  DMABurstBaseAddress This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DTR2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ECR
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_OR1
+  * @param  DMABurstLength This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_19TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_20TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_21TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_22TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_23TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_24TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_25TRANSFERS
+  *         @arg @ref LL_TIM_DMABURST_LENGTH_26TRANSFERS
+  * @param  DMABurstSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_DMA_UPDATE
+  *         @arg @ref LL_TIM_DMA_CC1
+  *         @arg @ref LL_TIM_DMA_CC2
+  *         @arg @ref LL_TIM_DMA_CC3
+  *         @arg @ref LL_TIM_DMA_CC4
+  *         @arg @ref LL_TIM_DMA_COM
+  *         @arg @ref LL_TIM_DMA_TRIGGER
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength,
+                                           uint32_t DMABurstSource)
+{
+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA | TIM_DCR_DBSS),
+             (DMABurstBaseAddress | DMABurstLength | DMABurstSource));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Encoder Encoder configuration
+  * @{
+  */
+
+/**
+  * @brief  Enable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_EnableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Disable encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_DisableEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableEncoderIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_IE);
+}
+
+/**
+  * @brief  Indicate whether encoder index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR         IE           LL_TIM_IsEnabledEncoderIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledEncoderIndex(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_IE) == (TIM_ECR_IE)) ? 1U : 0U);
+}
+
+/**
+  * @brief  Set index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_SetIndexDirection
+  * @param  TIMx Timer instance
+  * @param  IndexDirection This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexDirection(TIM_TypeDef *TIMx, uint32_t IndexDirection)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR, IndexDirection);
+}
+
+/**
+  * @brief  Get actual index direction
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR           LL_TIM_GetIndexDirection
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_UP
+  *         @arg @ref LL_TIM_INDEX_DOWN
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexDirection(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IDIR));
+}
+
+/**
+  * @brief  Set index blanking
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IBLK           LL_TIM_SetIndexblanking
+  * @param  TIMx Timer instance
+  * @param  Indexblanking This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI3
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI4
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexblanking(TIM_TypeDef *TIMx, uint32_t Indexblanking)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IBLK, Indexblanking);
+}
+
+/**
+  * @brief  Get actual index blanking
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IBLK           LL_TIM_GetIndexblanking
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI3
+  *         @arg @ref LL_TIM_INDEX_BLANK_TI4
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexblanking(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IBLK));
+}
+
+
+/**
+  * @brief  Enable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_EnableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableFirstIndex(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Disable first index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_DisableFirstIndex
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableFirstIndex(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->ECR, TIM_ECR_FIDX);
+}
+
+/**
+  * @brief  Indicates whether first index is enabled.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          FIDX          LL_TIM_IsEnabledFirstIndex
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledFirstIndex(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->ECR, TIM_ECR_FIDX) == (TIM_ECR_FIDX)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_SetIndexPositionning
+  * @param  TIMx Timer instance
+  * @param  IndexPositionning This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetIndexPositionning(TIM_TypeDef *TIMx, uint32_t IndexPositionning)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IPOS, IndexPositionning);
+}
+
+/**
+  * @brief  Get actual index positioning
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IPOS           LL_TIM_GetIndexPositionning
+  * @param  TIMx Timer instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP_UP
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN
+  *         @arg @ref LL_TIM_INDEX_POSITION_UP
+  */
+__STATIC_INLINE uint32_t LL_TIM_GetIndexPositionning(const TIM_TypeDef *TIMx)
+{
+  return (uint32_t)(READ_BIT(TIMx->ECR, TIM_ECR_IPOS));
+}
+
+/**
+  * @brief  Configure encoder index.
+  * @note Macro IS_TIM_INDEX_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides an index input.
+  * @rmtoll ECR          IDIR          LL_TIM_ConfigIDX\n
+  *         ECR          IBLK          LL_TIM_ConfigIDX\n
+  *         ECR          FIDX          LL_TIM_ConfigIDX\n
+  *         ECR          IPOS          LL_TIM_ConfigIDX
+  * @param  TIMx Timer instance
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_TIM_INDEX_UP or @ref LL_TIM_INDEX_DOWN or @ref LL_TIM_INDEX_UP_DOWN
+  *         @arg @ref LL_TIM_INDEX_BLANK_ALWAYS or @ref LL_TIM_INDEX_BLANK_TI3 or @ref LL_TIM_INDEX_BLANK_TI4
+  *         @arg @ref LL_TIM_INDEX_ALL or @ref LL_TIM_INDEX_FIRST_ONLY
+  *         @arg @ref LL_TIM_INDEX_POSITION_DOWN_DOWN or ... or @ref LL_TIM_INDEX_POSITION_UP
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ConfigIDX(TIM_TypeDef *TIMx, uint32_t Configuration)
+{
+  MODIFY_REG(TIMx->ECR, TIM_ECR_IDIR | TIM_ECR_IBLK | TIM_ECR_FIDX | TIM_ECR_IPOS, Configuration);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
+  * @{
+  */
+/**
+  * @brief  Remap TIM inputs (input channel, internal/external triggers).
+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
+  *       a some timer inputs can be remapped.
+  * @rmtoll TIM1_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM2_TISEL    TI4SEL      LL_TIM_SetRemap\n
+  *         TIM3_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM3_TISEL    TI2SEL      LL_TIM_SetRemap\n
+  *         TIM4_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM5_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM8_TISEL    TI1SEL      LL_TIM_SetRemap\n
+  *         TIM12_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM12_TISEL   TI2SEL      LL_TIM_SetRemap\n
+  *         TIM13_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM14_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM15_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM15_TISEL   TI2SEL      LL_TIM_SetRemap\n
+  *         TIM16_TISEL   TI1SEL      LL_TIM_SetRemap\n
+  *         TIM17_TISEL   TI1SEL      LL_TIM_SetRemap
+  *
+  * @param  TIMx Timer instance
+  * @param  Remap Remap param depends on the TIMx. Description available only
+  *         in CHM version of the User Manual (not in .pdf).
+  *         Otherwise see Reference Manual description of TISEL registers.
+  *
+  *         Below description summarizes "Timer Instance" and "Remap" param combinations:
+  *
+  *         TIM1: one of the following values:
+  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM1_TI1_RMP_COMP2:               TIM1 TI1 is connected to COMP2 output    (*)
+  *
+  *         TIM2: one of the following values:
+  *            @arg LL_TIM_TIM2_TI1_RMP_GPIO:                TIM2 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM2_TI1_RMP_LSI:                 TIM2 TI1 is connected to LSI             (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_LSE:                 TIM2 TI1 is connected to LSE             (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_RTC:                 TIM2 TI1 is connected to RTC             (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_TIM3_TI1:            TIM2 TI1 is connected to TIM3 TI1        (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_ETH_PPS:             TIM2 TI1 is connected to ETH PPS         (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_COMP1:               TIM2 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_COMP2:               TIM2 TI1 is connected to COMP2 output    (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_PLAY1_OUT3:          TIM2 TI1 is connected to PLAY1 output 3  (*)
+  *            @arg LL_TIM_TIM2_TI2_RMP_GPIO:                TIM2 TI2 is connected to GPIO
+  *            @arg LL_TIM_TIM2_TI2_RMP_HSI_1024:            TIM2 TI2 is connected to HSI 1024        (*)
+  *            @arg LL_TIM_TIM2_TI2_RMP_CSI_128:             TIM2 TI2 is connected to CSI 128         (*)
+  *            @arg LL_TIM_TIM2_TI2_RMP_MCO2:                TIM2 TI2 is connected to MCO2            (*)
+  *            @arg LL_TIM_TIM2_TI2_RMP_MCO1:                TIM2 TI2 is connected to MCO1            (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_COMP1:               TIM2 TI2 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM2_TI1_RMP_COMP2:               TIM2 TI2 is connected to COMP2 output    (*)
+  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO
+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1           (*)
+  *
+  *         TIM3: one of the following values:
+  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output    (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_MCO1:                TIM3 TI1 is connected to MCO1            (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_TIM2_TI1:            TIM3 TI1 is connected to TIM2 TI1        (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_HSE_1MHZ:            TIM3 TI1 is connected to HSE_1MHZ        (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_ETH_PPS:             TIM3 TI1 is connected to ETH PPS         (*)
+  *            @arg LL_TIM_TIM3_TI1_RMP_PLAY1_OUT3:          TIM3 TI1 is connected to PLAY1 output 3  (*)
+  *            @arg LL_TIM_TIM3_TI2_RMP_GPIO:                TIM3 TI2 is connected to GPIO
+  *            @arg LL_TIM_TIM3_TI2_RMP_CSI_128:             TIM3 TI2 is connected to CSI_128         (*)
+  *            @arg LL_TIM_TIM3_TI2_RMP_MCO2:                TIM3 TI2 is connected to MCO2            (*)
+  *            @arg LL_TIM_TIM3_TI2_RMP_HSI_1024:            TIM3 TI2 is connected to HSI_1024        (*)
+  *            @arg LL_TIM_TIM3_TI2_RMP_COMP1:               TIM3 TI2 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM3_TI2_RMP_COMP2:               TIM3 TI2 is connected to COMP2 output    (*)
+  *
+  *         TIM4: one of the following values: (**)
+  *            @arg LL_TIM_TIM4_TI1_RMP_GPIO:                TIM4 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM4_TI1_RMP_COMP1:               TIM4 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM4_TI1_RMP_COMP2:               TIM4 TI1 is connected to COMP2 output    (*)
+  *
+  *         TIM5: one of the following values: (**)
+  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM5_TI1_RMP_COMP1:               TIM5 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM5_TI1_RMP_COMP2:               TIM5 TI1 is connected to COMP2 output    (*)
+  *
+  *         TIM8: one of the following values: (**)
+  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:                TIM8 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM8_TI1_RMP_COMP1:               TIM8 TI1 is connected to COMP1 output    (*)
+  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:               TIM8 TI1 is connected to COMP2 output    (*)
+  *
+  *         TIM12: one of the following values: (**)
+  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:               TIM12 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM12_TI1_RMP_COMP1:              TIM12 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM12_TI1_RMP_COMP2:              TIM12 TI1 is connected to COMP2 output   (*)
+  *            @arg LL_TIM_TIM12_TI1_RMP_HSI_1024:           TIM12 TI1 is connected to HSI 1024
+  *            @arg LL_TIM_TIM12_TI1_RMP_CSI_128:            TIM12 TI1 is connected to CSI 128
+  *
+  *         TIM13: one of the following values: (**)
+  *            @arg LL_TIM_TIM13_TI1_RMP_GPIO:               TIM13 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM13_TI1_RMP_I3C1_IBIACK:        TIM13 TI1 is connected to I3C1 IBI ACK   (*)
+  *            @arg LL_TIM_TIM13_TI1_RMP_COMP1:              TIM13 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM13_TI1_RMP_COMP2:              TIM13 TI1 is connected to COMP2 output   (*)
+  *
+  *         TIM14: one of the following values: (**)
+  *            @arg LL_TIM_TIM14_TI1_RMP_GPIO:               TIM14 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM14_TI1_RMP_I3C2_IBIACK:        TIM14 TI1 is connected to I3C2 IBI ACK   (*)
+  *            @arg LL_TIM_TIM14_TI1_RMP_COMP1:              TIM14 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM14_TI1_RMP_COMP2:              TIM14 TI1 is connected to COMP2 output   (*)
+  *
+  *         TIM15: one of the following values: (**)
+  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:               TIM15 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:               TIM15 TI1 is connected to TIM2
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:               TIM15 TI1 is connected to TIM3
+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:               TIM15 TI1 is connected to TIM4
+  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:                TIM15 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM15_TI1_RMP_CSI_128:            TIM15 TI1 is connected to CSI/128
+  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:               TIM15 TI1 is connected to MCO2
+  *            @arg LL_TIM_TIM15_TI1_RMP_COMP1:              TIM15 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM15_TI1_RMP_COMP2:              TIM15 TI1 is connected to COMP2 output   (*)
+  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:               TIM15 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:               TIM15 TI1 is connected to TIM2
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:               TIM15 TI1 is connected to TIM3
+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:               TIM15 TI1 is connected to TIM4
+  *            @arg LL_TIM_TIM15_TI2_RMP_COMP1:              TIM15 TI2 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM15_TI2_RMP_COMP2:              TIM15 TI2 is connected to COMP2 output   (*)
+  *
+  *         TIM16: one of the following values: (**)
+  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:               TIM16 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:                TIM16 TI1 is connected to LSI
+  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:                TIM16 TI1 is connected to LSE
+  *            @arg LL_TIM_TIM16_TI1_RMP_RTC_WKUP:           TIM16 TI1 is connected to RTC_WKUP
+  *            @arg LL_TIM_TIM16_TI1_RMP_COMP1:              TIM16 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM16_TI1_RMP_COMP2:              TIM16 TI1 is connected to COMP2 output   (*)
+  *
+  *         TIM17: one of the following values: (**)
+  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:               TIM17 TI1 is connected to GPIO
+  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:           TIM17 TI1 is connected to HSE_1MHZ
+  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:               TIM17 TI1 is connected to MCO1
+  *            @arg LL_TIM_TIM17_TI1_RMP_COMP1:              TIM17 TI1 is connected to COMP1 output   (*)
+  *            @arg LL_TIM_TIM17_TI1_RMP_COMP2:              TIM17 TI1 is connected to COMP2 output   (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  *         (**) Timer instance not available on all devices. \n
+  *
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
+{
+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);
+}
+
+/**
+  * @brief  Enable request for HSE 1MHz clock used for TISEL remap.
+  * @note Only TIM17 support HSE 1MHz remap
+  * @rmtoll OR1         RTCPREEN           LL_TIM_EnableRTCPRE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableRTCPRE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->OR1, TIM_OR1_RTCPREEN);
+}
+
+/**
+  * @brief  Disable request for HSE 1MHz clock used for TISEL remap.
+  * @note Only TIM17 support HSE 1MHz remap
+  * @rmtoll OR1         RTCPREEN           LL_TIM_DisableRTCPRE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableRTCPRE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->OR1, TIM_OR1_RTCPREEN);
+}
+
+/**
+  * @brief  Indicate whether request for HSE 1MHz clock is enabled.
+  * @note Only TIM17 support HSE 1MHz remap
+  * @rmtoll OR1         RTCPREEN           LL_TIM_IsEnabledRTCPRE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledRTCPRE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->OR1, TIM_OR1_RTCPREEN) == (TIM_OR1_RTCPREEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management
+  * @{
+  */
+/**
+  * @brief  Set the OCREF clear input source
+  * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT
+  * @note This function can only be used in Output compare and PWM modes.
+  * @rmtoll SMCR          OCCS                LL_TIM_SetOCRefClearInputSource
+  * @rmtoll AF2           OCRSEL              LL_TIM_SetOCRefClearInputSource
+  * @param  TIMx Timer instance
+  * @param  OCRefClearInputSource This parameter can be one of the following values:
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_ETR
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP1 (*)
+  *         @arg @ref LL_TIM_OCREF_CLR_INT_COMP2 (*)
+  *
+  *         (*)  Value not defined in all devices. \n
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource)
+{
+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS,
+             ((OCRefClearInputSource & OCREF_CLEAR_SELECT_MSK) >> OCREF_CLEAR_SELECT_POS) << TIM_SMCR_OCCS_Pos);
+  MODIFY_REG(TIMx->AF2, TIM1_AF2_OCRSEL, OCRefClearInputSource);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
+  * @{
+  */
+/**
+  * @brief  Clear the update interrupt flag (UIF).
+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
+}
+
+/**
+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).
+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).
+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).
+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).
+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).
+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).
+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the commutation interrupt flag (COMIF).
+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
+}
+
+/**
+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the trigger interrupt flag (TIF).
+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
+}
+
+/**
+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break interrupt flag (BIF).
+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
+}
+
+/**
+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the break 2 interrupt flag (B2IF).
+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
+}
+
+/**
+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set
+  *         (Capture/Compare 1 interrupt is pending).
+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set
+  *         (Capture/Compare 2 over-capture interrupt is pending).
+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set
+  *         (Capture/Compare 3 over-capture interrupt is pending).
+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
+}
+
+/**
+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set
+  *         (Capture/Compare 4 over-capture interrupt is pending).
+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the system break interrupt flag (SBIF).
+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
+}
+
+/**
+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the transition error interrupt flag (TERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_ClearFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_TERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_TERRF));
+}
+
+/**
+  * @brief  Indicate whether transition error interrupt flag (TERRF) is set (transition error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           TERRF           LL_TIM_IsActiveFlag_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_TERRF) == (TIM_SR_TERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index error interrupt flag (IERRF).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_ClearFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IERR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IERRF));
+}
+
+/**
+  * @brief  Indicate whether index error interrupt flag (IERRF) is set (index error interrupt is pending).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll SR           IERRF           LL_TIM_IsActiveFlag_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IERRF) == (TIM_SR_IERRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the direction change interrupt flag (DIRF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_ClearFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_DIR(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_DIRF));
+}
+
+/**
+  * @brief  Indicate whether direction change interrupt flag (DIRF) is set (direction change interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           DIRF           LL_TIM_IsActiveFlag_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_DIR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_DIRF) == (TIM_SR_DIRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the index interrupt flag (IDXF).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_ClearFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_ClearFlag_IDX(TIM_TypeDef *TIMx)
+{
+  WRITE_REG(TIMx->SR, ~(TIM_SR_IDXF));
+}
+
+/**
+  * @brief  Indicate whether index interrupt flag (IDXF) is set (index interrupt is pending).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll SR           IDXF           LL_TIM_IsActiveFlag_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_IDX(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->SR, TIM_SR_IDXF) == (TIM_SR_IDXF)) ? 1UL : 0UL);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_IT_Management IT-Management
+  * @{
+  */
+/**
+  * @brief  Enable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Disable update interrupt (UIE).
+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
+}
+
+/**
+  * @brief  Indicates whether the update interrupt (UIE) is enabled.
+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  interrupt (CC1IE).
+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  interrupt (CC2IE).
+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  interrupt (CC3IE).
+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  interrupt (CC4IE).
+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Disable commutation interrupt (COMIE).
+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
+}
+
+/**
+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.
+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TIE).
+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.
+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Disable break interrupt (BIE).
+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
+}
+
+/**
+  * @brief  Indicates whether the break interrupt (BIE) is enabled.
+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_EnableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_TERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Disable transition error interrupt (TERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_DisableIT_TERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_TERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TERRIE);
+}
+
+/**
+  * @brief  Indicates whether the transition error interrupt (TERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         TERRIE           LL_TIM_IsEnabledIT_TERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TERRIE) == (TIM_DIER_TERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_EnableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IERR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Disable index error interrupt (IERRIE).
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_DisableIT_IERR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IERR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IERRIE);
+}
+
+/**
+  * @brief  Indicates whether the index error interrupt (IERRIE) is enabled.
+  * @note Macro IS_TIM_ENCODER_ERROR_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder error management.
+  * @rmtoll DIER         IERRIE           LL_TIM_IsEnabledIT_IERR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IERR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IERRIE) == (TIM_DIER_IERRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_EnableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_DIR(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Disable direction change interrupt (DIRIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_DisableIT_DIR
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_DIR(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_DIRIE);
+}
+
+/**
+  * @brief  Indicates whether the direction change interrupt (DIRIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         DIRIE           LL_TIM_IsEnabledIT_DIR
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_DIR(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_DIRIE) == (TIM_DIER_DIRIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_EnableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableIT_IDX(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Disable index interrupt (IDXIE).
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_DisableIT_IDX
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableIT_IDX(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_IDXIE);
+}
+
+/**
+  * @brief  Indicates whether the index interrupt (IDXIE) is enabled.
+  * @note Macro IS_TIM_FUNCTINONAL_ENCODER_INTERRUPT_INSTANCE(TIMx) can be used to check whether or not
+  *       a timer instance provides encoder interrupt management.
+  * @rmtoll DIER         IDXIE           LL_TIM_IsEnabledIT_IDX
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_IDX(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_IDXIE) == (TIM_DIER_IDXIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+/**
+  * @brief  Enable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Disable update DMA request (UDE).
+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
+}
+
+/**
+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.
+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 1 DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Disable capture/compare 1  DMA request (CC1DE).
+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 2 DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Disable capture/compare 2  DMA request (CC2DE).
+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 3 DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Disable capture/compare 3  DMA request (CC3DE).
+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable capture/compare 4 DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Disable capture/compare 4  DMA request (CC4DE).
+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
+}
+
+/**
+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Disable commutation DMA request (COMDE).
+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
+}
+
+/**
+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.
+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Disable trigger interrupt (TDE).
+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
+{
+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
+}
+
+/**
+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.
+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG
+  * @param  TIMx Timer instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(const TIM_TypeDef *TIMx)
+{
+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
+  * @{
+  */
+/**
+  * @brief  Generate an update event.
+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_UG);
+}
+
+/**
+  * @brief  Generate Capture/Compare 1 event.
+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 2 event.
+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 3 event.
+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
+}
+
+/**
+  * @brief  Generate Capture/Compare 4 event.
+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
+}
+
+/**
+  * @brief  Generate commutation event.
+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);
+}
+
+/**
+  * @brief  Generate trigger event.
+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_TG);
+}
+
+/**
+  * @brief  Generate break event.
+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_BG);
+}
+
+/**
+  * @brief  Generate break 2 event.
+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2
+  * @param  TIMx Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
+{
+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
+  * @{
+  */
+
+ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32H5xx_LL_TIM_H */
diff --git a/MDK-ARM/AutoGuideStick.uvguix.madao b/MDK-ARM/AutoGuideStick.uvguix.madao
index 98783ef..dd1ddbd 100644
--- a/MDK-ARM/AutoGuideStick.uvguix.madao
+++ b/MDK-ARM/AutoGuideStick.uvguix.madao
@@ -93,25 +93,25 @@
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diff --git a/MDK-ARM/AutoGuideStick.uvoptx b/MDK-ARM/AutoGuideStick.uvoptx
index 10fb4b5..79fbda5 100644
--- a/MDK-ARM/AutoGuideStick.uvoptx
+++ b/MDK-ARM/AutoGuideStick.uvoptx
@@ -117,6 +117,11 @@
         <pMon>STLink\ST-LINKIII-KEIL_SWO.dll</pMon>
       </DebugOpt>
       <TargetDriverDllRegistry>
+        <SetRegEntry>
+          <Number>0</Number>
+          <Key>CMSIS_AGDI_V8M</Key>
+          <Name>-X"" -O206 -S8 -C0 -P00000001 -N00("") -D00(00000000) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD20000000 -FC8000 -FN2 -FF0STM32H5xx_2M_0800.FLM -FS08000000 -FL0200000 -FP0($$Device:STM32H563ZITx$CMSIS\Flash\STM32H5xx_2M_0800.FLM) -FF1STM32H5xx_2M_0C00.FLM -FS1C000000 -FL1200000 -FP1($$Device:STM32H563ZITx$CMSIS\Flash\STM32H5xx_2M_0C00.FLM)</Name>
+        </SetRegEntry>
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@@ -286,6 +291,18 @@
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@@ -961,7 +978,7 @@
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@@ -973,7 +990,7 @@
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@@ -985,7 +1002,7 @@
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@@ -997,7 +1014,7 @@
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@@ -1009,7 +1026,7 @@
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@@ -1021,7 +1038,7 @@
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@@ -1033,7 +1050,7 @@
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@@ -1045,7 +1062,7 @@
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@@ -1057,7 +1074,7 @@
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@@ -1069,7 +1086,7 @@
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@@ -1081,7 +1098,7 @@
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@@ -1093,7 +1110,7 @@
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@@ -1105,7 +1122,7 @@
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@@ -1117,7 +1134,7 @@
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@@ -1129,7 +1146,7 @@
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@@ -1141,7 +1158,7 @@
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@@ -1153,7 +1170,7 @@
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@@ -1165,7 +1182,7 @@
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@@ -1177,7 +1194,7 @@
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@@ -1189,7 +1206,7 @@
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@@ -1201,7 +1218,7 @@
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@@ -1213,7 +1230,7 @@
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@@ -1237,7 +1254,7 @@
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@@ -1249,7 +1266,7 @@
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@@ -1273,7 +1290,7 @@
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@@ -1285,7 +1302,7 @@
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@@ -1297,7 +1314,7 @@
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@@ -1309,7 +1326,7 @@
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@@ -1321,7 +1338,7 @@
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@@ -1333,7 +1350,7 @@
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@@ -1345,7 +1362,7 @@
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@@ -1357,7 +1374,7 @@
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@@ -1369,7 +1386,7 @@
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@@ -1381,7 +1398,7 @@
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@@ -1405,7 +1422,7 @@
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@@ -1417,7 +1434,7 @@
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@@ -1429,7 +1446,7 @@
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@@ -1441,7 +1458,7 @@
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@@ -1453,7 +1470,7 @@
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@@ -1465,7 +1482,7 @@
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@@ -1477,7 +1494,7 @@
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@@ -1489,7 +1506,7 @@
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@@ -1501,7 +1518,7 @@
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@@ -1513,7 +1530,7 @@
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@@ -1537,7 +1554,7 @@
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@@ -1549,7 +1566,7 @@
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@@ -1561,7 +1578,7 @@
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@@ -1573,7 +1590,7 @@
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@@ -1645,7 +1662,7 @@
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@@ -1657,7 +1674,7 @@
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@@ -1669,7 +1686,7 @@
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@@ -1681,7 +1698,7 @@
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@@ -1693,7 +1710,7 @@
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@@ -1705,7 +1722,7 @@
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@@ -1717,7 +1734,7 @@
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@@ -1729,7 +1746,7 @@
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@@ -1741,7 +1758,7 @@
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@@ -1765,7 +1782,7 @@
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@@ -1777,7 +1794,7 @@
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@@ -1789,7 +1806,7 @@
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@@ -1801,7 +1818,7 @@
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@@ -1813,7 +1830,7 @@
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@@ -1825,7 +1842,7 @@
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@@ -1849,7 +1866,7 @@
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@@ -1861,7 +1878,7 @@
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@@ -1873,7 +1890,7 @@
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@@ -1897,7 +1914,7 @@
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-      <FileNumber>140</FileNumber>
+      <FileNumber>141</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1909,7 +1926,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>141</FileNumber>
+      <FileNumber>142</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1921,7 +1938,7 @@
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     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>142</FileNumber>
+      <FileNumber>143</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1933,7 +1950,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>143</FileNumber>
+      <FileNumber>144</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1945,7 +1962,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>144</FileNumber>
+      <FileNumber>145</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1957,7 +1974,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>145</FileNumber>
+      <FileNumber>146</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1969,7 +1986,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>146</FileNumber>
+      <FileNumber>147</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1981,7 +1998,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>147</FileNumber>
+      <FileNumber>148</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -1993,7 +2010,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>148</FileNumber>
+      <FileNumber>149</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2005,7 +2022,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>149</FileNumber>
+      <FileNumber>150</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2017,7 +2034,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>150</FileNumber>
+      <FileNumber>151</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2029,7 +2046,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>151</FileNumber>
+      <FileNumber>152</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2041,7 +2058,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>152</FileNumber>
+      <FileNumber>153</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2053,7 +2070,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>153</FileNumber>
+      <FileNumber>154</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2065,7 +2082,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>154</FileNumber>
+      <FileNumber>155</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2077,7 +2094,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>155</FileNumber>
+      <FileNumber>156</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2089,7 +2106,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>156</FileNumber>
+      <FileNumber>157</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2101,7 +2118,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>157</FileNumber>
+      <FileNumber>158</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2113,7 +2130,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>158</FileNumber>
+      <FileNumber>159</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2125,7 +2142,7 @@
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     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>159</FileNumber>
+      <FileNumber>160</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2137,7 +2154,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>160</FileNumber>
+      <FileNumber>161</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2149,7 +2166,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>161</FileNumber>
+      <FileNumber>162</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2161,7 +2178,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>162</FileNumber>
+      <FileNumber>163</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2173,7 +2190,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>163</FileNumber>
+      <FileNumber>164</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2185,7 +2202,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>164</FileNumber>
+      <FileNumber>165</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2197,7 +2214,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>165</FileNumber>
+      <FileNumber>166</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2209,7 +2226,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>166</FileNumber>
+      <FileNumber>167</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2221,7 +2238,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>167</FileNumber>
+      <FileNumber>168</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2233,7 +2250,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>168</FileNumber>
+      <FileNumber>169</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2245,7 +2262,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>169</FileNumber>
+      <FileNumber>170</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2257,7 +2274,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>170</FileNumber>
+      <FileNumber>171</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2269,7 +2286,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>171</FileNumber>
+      <FileNumber>172</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2281,7 +2298,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>172</FileNumber>
+      <FileNumber>173</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2293,7 +2310,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>173</FileNumber>
+      <FileNumber>174</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2305,7 +2322,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>174</FileNumber>
+      <FileNumber>175</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2317,7 +2334,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>175</FileNumber>
+      <FileNumber>176</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2329,7 +2346,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>176</FileNumber>
+      <FileNumber>177</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2341,7 +2358,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>177</FileNumber>
+      <FileNumber>178</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2353,7 +2370,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>178</FileNumber>
+      <FileNumber>179</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2365,7 +2382,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>179</FileNumber>
+      <FileNumber>180</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2377,7 +2394,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>180</FileNumber>
+      <FileNumber>181</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2389,7 +2406,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>181</FileNumber>
+      <FileNumber>182</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2401,7 +2418,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>182</FileNumber>
+      <FileNumber>183</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2413,7 +2430,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>183</FileNumber>
+      <FileNumber>184</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2425,7 +2442,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>184</FileNumber>
+      <FileNumber>185</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2437,7 +2454,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>185</FileNumber>
+      <FileNumber>186</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2449,7 +2466,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>186</FileNumber>
+      <FileNumber>187</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2461,7 +2478,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>187</FileNumber>
+      <FileNumber>188</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2473,7 +2490,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>188</FileNumber>
+      <FileNumber>189</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2485,7 +2502,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>189</FileNumber>
+      <FileNumber>190</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2497,7 +2514,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>190</FileNumber>
+      <FileNumber>191</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2509,7 +2526,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>191</FileNumber>
+      <FileNumber>192</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2521,7 +2538,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>192</FileNumber>
+      <FileNumber>193</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2533,7 +2550,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>193</FileNumber>
+      <FileNumber>194</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2545,7 +2562,7 @@
     </File>
     <File>
       <GroupNumber>6</GroupNumber>
-      <FileNumber>194</FileNumber>
+      <FileNumber>195</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2559,13 +2576,13 @@
 
   <Group>
     <GroupName>fun</GroupName>
-    <tvExp>1</tvExp>
+    <tvExp>0</tvExp>
     <tvExpOptDlg>0</tvExpOptDlg>
     <cbSel>0</cbSel>
     <RteFlg>0</RteFlg>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>195</FileNumber>
+      <FileNumber>196</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2577,7 +2594,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>196</FileNumber>
+      <FileNumber>197</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2589,7 +2606,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>197</FileNumber>
+      <FileNumber>198</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2601,7 +2618,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>198</FileNumber>
+      <FileNumber>199</FileNumber>
       <FileType>1</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2613,7 +2630,7 @@
     </File>
     <File>
       <GroupNumber>7</GroupNumber>
-      <FileNumber>199</FileNumber>
+      <FileNumber>200</FileNumber>
       <FileType>5</FileType>
       <tvExp>0</tvExp>
       <tvExpOptDlg>0</tvExpOptDlg>
@@ -2623,6 +2640,78 @@
       <RteFlg>0</RteFlg>
       <bShared>0</bShared>
     </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>201</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Buzzer.c</PathWithFileName>
+      <FilenameWithoutPath>Buzzer.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>202</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Buzzer.h</PathWithFileName>
+      <FilenameWithoutPath>Buzzer.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>203</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Shake_Motor.c</PathWithFileName>
+      <FilenameWithoutPath>Shake_Motor.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>204</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Shake_Motor.h</PathWithFileName>
+      <FilenameWithoutPath>Shake_Motor.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>205</FileNumber>
+      <FileType>1</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Ultrasound.c</PathWithFileName>
+      <FilenameWithoutPath>Ultrasound.c</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
+    <File>
+      <GroupNumber>7</GroupNumber>
+      <FileNumber>206</FileNumber>
+      <FileType>5</FileType>
+      <tvExp>0</tvExp>
+      <tvExpOptDlg>0</tvExpOptDlg>
+      <bDave2>0</bDave2>
+      <PathWithFileName>..\fun\Ultrasound.h</PathWithFileName>
+      <FilenameWithoutPath>Ultrasound.h</FilenameWithoutPath>
+      <RteFlg>0</RteFlg>
+      <bShared>0</bShared>
+    </File>
   </Group>
 
   <Group>
diff --git a/MDK-ARM/AutoGuideStick.uvprojx b/MDK-ARM/AutoGuideStick.uvprojx
index 77b00b0..aaa7981 100644
--- a/MDK-ARM/AutoGuideStick.uvprojx
+++ b/MDK-ARM/AutoGuideStick.uvprojx
@@ -475,6 +475,62 @@
               <FileType>1</FileType>
               <FilePath>../Core/Src/app_threadx.c</FilePath>
             </File>
+            <File>
+              <FileName>tim.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Core/Src/tim.c</FilePath>
+              <FileOption>
+                <CommonProperty>
+                  <UseCPPCompiler>2</UseCPPCompiler>
+                  <RVCTCodeConst>0</RVCTCodeConst>
+                  <RVCTZI>0</RVCTZI>
+                  <RVCTOtherData>0</RVCTOtherData>
+                  <ModuleSelection>0</ModuleSelection>
+                  <IncludeInBuild>1</IncludeInBuild>
+                  <AlwaysBuild>2</AlwaysBuild>
+                  <GenerateAssemblyFile>2</GenerateAssemblyFile>
+                  <AssembleAssemblyFile>2</AssembleAssemblyFile>
+                  <PublicsOnly>2</PublicsOnly>
+                  <StopOnExitCode>11</StopOnExitCode>
+                  <CustomArgument></CustomArgument>
+                  <IncludeLibraryModules></IncludeLibraryModules>
+                  <ComprImg>1</ComprImg>
+                </CommonProperty>
+                <FileArmAds>
+                  <Cads>
+                    <interw>2</interw>
+                    <Optim>0</Optim>
+                    <oTime>2</oTime>
+                    <SplitLS>2</SplitLS>
+                    <OneElfS>2</OneElfS>
+                    <Strict>2</Strict>
+                    <EnumInt>2</EnumInt>
+                    <PlainCh>2</PlainCh>
+                    <Ropi>2</Ropi>
+                    <Rwpi>2</Rwpi>
+                    <wLevel>0</wLevel>
+                    <uThumb>2</uThumb>
+                    <uSurpInc>2</uSurpInc>
+                    <uC99>2</uC99>
+                    <uGnu>2</uGnu>
+                    <useXO>2</useXO>
+                    <v6Lang>0</v6Lang>
+                    <v6LangP>0</v6LangP>
+                    <vShortEn>2</vShortEn>
+                    <vShortWch>2</vShortWch>
+                    <v6Lto>2</v6Lto>
+                    <v6WtE>2</v6WtE>
+                    <v6Rtti>2</v6Rtti>
+                    <VariousControls>
+                      <MiscControls></MiscControls>
+                      <Define></Define>
+                      <Undefine></Undefine>
+                      <IncludePath></IncludePath>
+                    </VariousControls>
+                  </Cads>
+                </FileArmAds>
+              </FileOption>
+            </File>
             <File>
               <FileName>usart.c</FileName>
               <FileType>1</FileType>
@@ -576,16 +632,6 @@
               <FileType>1</FileType>
               <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_cortex.c</FilePath>
             </File>
-            <File>
-              <FileName>stm32h5xx_hal_dma.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c</FilePath>
-            </File>
-            <File>
-              <FileName>stm32h5xx_hal_dma_ex.c</FileName>
-              <FileType>1</FileType>
-              <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c</FilePath>
-            </File>
             <File>
               <FileName>stm32h5xx_hal_rcc.c</FileName>
               <FileType>1</FileType>
@@ -611,6 +657,16 @@
               <FileType>1</FileType>
               <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_gpio.c</FilePath>
             </File>
+            <File>
+              <FileName>stm32h5xx_hal_dma.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c</FilePath>
+            </File>
+            <File>
+              <FileName>stm32h5xx_hal_dma_ex.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c</FilePath>
+            </File>
             <File>
               <FileName>stm32h5xx_hal_pwr.c</FileName>
               <FileType>1</FileType>
@@ -1613,6 +1669,36 @@
               <FileType>5</FileType>
               <FilePath>..\fun\gps.h</FilePath>
             </File>
+            <File>
+              <FileName>Buzzer.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\fun\Buzzer.c</FilePath>
+            </File>
+            <File>
+              <FileName>Buzzer.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\fun\Buzzer.h</FilePath>
+            </File>
+            <File>
+              <FileName>Shake_Motor.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\fun\Shake_Motor.c</FilePath>
+            </File>
+            <File>
+              <FileName>Shake_Motor.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\fun\Shake_Motor.h</FilePath>
+            </File>
+            <File>
+              <FileName>Ultrasound.c</FileName>
+              <FileType>1</FileType>
+              <FilePath>..\fun\Ultrasound.c</FilePath>
+            </File>
+            <File>
+              <FileName>Ultrasound.h</FileName>
+              <FileType>5</FileType>
+              <FilePath>..\fun\Ultrasound.h</FilePath>
+            </File>
           </Files>
         </Group>
         <Group>
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.axf b/MDK-ARM/AutoGuideStick/AutoGuideStick.axf
index 00de0ad..89f9f7c 100644
Binary files a/MDK-ARM/AutoGuideStick/AutoGuideStick.axf and b/MDK-ARM/AutoGuideStick/AutoGuideStick.axf differ
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm b/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm
index cde30f5..a543c34 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm
@@ -22,17 +22,11 @@ Dialog DLL:      TCM.DLL V1.56.4.0
  
 <h2>Project:</h2>
 D:\advance_stick\AutoGuideStick\MDK-ARM\AutoGuideStick.uvprojx
-Project File Date:  06/10/2025
+Project File Date:  06/24/2025
 
 <h2>Output:</h2>
 *** Using Compiler 'V6.21', folder: 'D:\keil5\ARM\ARMCLANG\Bin'
 Build target 'AutoGuideStick'
-compiling stm32h5xx_it.c...
-compiling HCBle.c...
-compiling gps.c...
-linking...
-Program Size: Code=55862 RO-data=726 RW-data=16 ZI-data=5952  
-FromELF: creating hex file...
 "AutoGuideStick\AutoGuideStick.axf" - 0 Error(s), 0 Warning(s).
 
 <h2>Software Packages used:</h2>
@@ -57,7 +51,7 @@ Package Vendor: Keil
 
    * Component: ARM::CMSIS:CORE@5.6.0
       Include file:  CMSIS/Core/Include/tz_context.h
-Build Time Elapsed:  00:00:02
+Build Time Elapsed:  00:00:01
 </pre>
 </body>
 </html>
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.hex b/MDK-ARM/AutoGuideStick/AutoGuideStick.hex
index 320a46b..c35f1e8 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick.hex
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.hex
@@ -1,6 +1,6 @@
 :020000040800F2
-:10000000501700201903000805A7000815A50008CF
-:1000100001A70008A908000859C900082B03000817
+:10000000381800201903000895B10008C5AD000894
+:1000100091B10008A90800080DD800082B030008BA
 :100020000000000000000000000000002D03000898
 :10003000F91900080000000001040008AD030008E1
 :1000400035030008350300083503000835030008B0
@@ -13,12 +13,12 @@
 :1000B0003503000835030008051A0008151A000862
 :1000C000251A000835030008350300083503000829
 :1000D0000000000035030008350300083503000860
-:1000E00035030008350300084DAC0008350300084F
-:1000F0003503000835030008350300083503000800
+:1000E0003503000835030008DDB6000835030008B5
+:1000F00035030008EDB60008350300083503000895
 :1001000035030008350300083503000835030008EF
 :1001100035030008350300083503000835030008DF
-:100120003503000835030008A9C8000849C90008BC
-:1001300035030008350300083503000835030008BF
+:1001200035030008350300085DD70008FDD7000837
+:1001300035030008350300085DBE000835030008DC
 :1001400035030008350300083503000835030008AF
 :10015000350300083503000835030008350300089F
 :10016000350300083503000835030008350300088F
@@ -41,18 +41,18 @@
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 :100280004FEA15154FEA3414A4F10104AC4201D32E
 :1002900000F032F813F0010F18BFFB1A43F001030E
-:1002A00000F001F8DBE7184744DA000064DA0000E8
+:1002A00000F001F8DBE7184700E9000020E9000052
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-:1002E000520728BF30C148BF0B6070471FB50DF0E3
-:1002F000BBFC1FBD10B510BD00F098FA1146FFF70A
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@@ -82,8 +82,8 @@
 :10050000010018601D490868026822B11C4B4FF0B9
 :1005100001021A6008E000F104001A4B1A689042C8
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 :1005700034040020E80800209803002090030020A5
@@ -415,16 +415,16 @@
 :1019D00000100844039909688864039801684FF46B
 :1019E000FE40C860029803990968C8640198039989
 :1019F0000968086504B070477047000072B6FFE7D9
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 :101A300091FD80BD80B584B002900191029818B1EB
 :101A4000FFE7019820B9FFE701208DF80F001AE0A9
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-:101A900080B584B0029001F08FFA0190029820B9CD
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 :101AC0000298016801205022C5F202029142009062
@@ -475,7 +475,7 @@
 :101D900008B1FFE7FFE7FFE70299002081F84C0058
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@@ -566,12 +566,12 @@
 :102340008865FFE70499002081F84C00FFE7012031
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@@ -642,7 +642,7 @@
 :1028000001200873FFE7FFE70399002081F84C00DF
 :10281000FFE70398806E20B1FFE70398816E884739
 :10282000FFE7FFE704B080BD80B584B0029000F000
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@@ -696,7 +696,7 @@
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@@ -762,2780 +762,3016 @@
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+:10E8C000EFF31080179017980B9072B60B98099081
+:10E8D00075E740F29430C2F200000068D8B9FFE753
+:10E8E00040F23840C2F20000019001990320086311
+:10E8F00001990120886340F2FC21C2F200010868FE
+:10E900000130086009981090109880F310880198E1
+:10E91000FFF7E2FB05E009980F900F9880F310884D
+:10E92000FFE704E718B080BD80B592B0DDF850C0B5
+:10E93000099008910792069300200490099818B94D
+:10E94000FFE7022004909BE01498342803D0FFE7EF
+:10E950000220049093E0EFF31080109010980B9039
+:10E9600072B60B98059040F2FC21C2F200010868D3
+:10E970000130086005980D900D9880F3108840F2E2
+:10E98000BC20C2F200000068029000200390FFE764
+:10E99000039840F2B821C2F20001096888420FD200
+:10E9A000FFE709980299884201D1FFE708E0029841
+:10E9B000C06A0290FFE7FFE7039801300390E7E7A2
+:10E9C000EFF31080119011980A9072B60A98059092
+:10E9D00040F2FC21C2F20001086801380860059885
+:10E9E0000C900C9880F31088FFF71AFA0998029996
+:10E9F000884203D1FFE7022004903FE0079818B94E
+:10EA0000FFE70320049038E00698632803D8FFE767
+:10EA10000520049030E040F2EC20C2F200000068D3
+:10EA20000190019840F23841C2F20001884203D1BE
+:10EA3000FFE713200490FFE740F20400C2F2000059
+:10EA40000068EFF305810F910F99084398B1FFE734
+:10EA500040F20400C2F200000068EFF305810E915D
+:10EA60000E9908430009B0F10F3F03D2FFE71320CE
+:10EA70000490FFE7FFE7FFE7FFE7FFE7FFE7FFE7B8
+:10EA8000049840B9FFE709980899079A069BFEF792
+:10EA90001FFF0490FFE7049812B080BD80B582B0DC
+:10EAA00000200190F4F7B2FAFCF718FDFCF7BCF96E
+:10EAB000FCF78AF9FCF7DCFAFCF722FBFCF728FAF2
+:10EAC000FCF78EFAFCF788FAFFE7FEE780B584B022
+:10EAD00003900020029069463420086040F6C05040
+:10EAE000C2F200004EF67E31C0F6000140F6F4524C
+:10EAF000C2F200024FF48063FFF716FF08B1FFE790
+:10EB00000EE040F6C050C2F2000001900198F1F70B
+:10EB1000C3FE0290029810B1FFE7FFE7FEE7FFE7B0
+:10EB200004B080BDF1EE100A4FF6FF71C0F2C031A3
+:10EB300020EA010040F04070E1EE100A704700004A
+:10EB4000000000000000010203040607080900009D
+:10EB5000000001020304080402040801010101018C
+:10EB60000103070100000100020004000600080084
+:10EB70000A000C00100020004000800000015478C2
+:10EB800020417070206D656D6F727920706F6F6CB1
+:10EB90000053797374656D2054696D6572205468F3
+:10EBA0007265616400000000C8EB000800000020EE
+:10EBB00010000000B0020008D8EB00081000002090
+:10EBC00028180000D00200080090D003F0F0F0F008
+:08EBD00001000000100000002C
 :040000050800024DA0
 :00000001FF
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.htm b/MDK-ARM/AutoGuideStick/AutoGuideStick.htm
index 1444f53..baea0a3 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick.htm
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.htm
@@ -3,25 +3,25 @@
 <title>Static Call Graph - [AutoGuideStick\AutoGuideStick.axf]</title></head>
 <body><HR>
 <H1>Static Call Graph for image AutoGuideStick\AutoGuideStick.axf</H1><HR>
-<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 6210000: Last Updated: Tue Jun 10 14:48:55 2025
+<BR><P>#&#060CALLGRAPH&#062# ARM Linker, 6210000: Last Updated: Tue Jun 24 17:48:44 2025
 <BR><P>
-<H3>Maximum Stack Usage =        704 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
+<H3>Maximum Stack Usage =        720 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)</H3><H3>
 Call chain for Maximum Stack Depth:</H3>
-__rt_entry_main &rArr; main &rArr; MX_USART2_UART_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
+__rt_entry_main &rArr; main &rArr; MX_UART5_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 <P>
 <H3>
 Functions with no stack information
 </H3><UL>
- <LI><a href="#[127]">_tx_initialize_low_level</a>
+ <LI><a href="#[139]">_tx_initialize_low_level</a>
  <LI><a href="#[a8]">__tx_BadHandler</a>
- <LI><a href="#[158]">__tx_IntHandler</a>
+ <LI><a href="#[169]">__tx_IntHandler</a>
  <LI><a href="#[a]">SysTick_Handler</a>
  <LI><a href="#[aa]">__tx_NMIHandler</a>
  <LI><a href="#[ab]">__tx_DBGHandler</a>
- <LI><a href="#[129]">_tx_thread_schedule</a>
+ <LI><a href="#[13b]">_tx_thread_schedule</a>
  <LI><a href="#[9]">PendSV_Handler</a>
- <LI><a href="#[159]">_tx_vfp_access</a>
- <LI><a href="#[12b]">_tx_thread_stack_build</a>
+ <LI><a href="#[16a]">_tx_vfp_access</a>
+ <LI><a href="#[13d]">_tx_thread_stack_build</a>
  <LI><a href="#[a9]">_tx_timer_interrupt</a>
 </UL>
 </UL>
@@ -149,7 +149,7 @@ Function Pointers
  <LI><a href="#[36]">TIM1_CC_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[35]">TIM1_TRG_COM_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[34]">TIM1_UP_IRQHandler</a> from stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) referenced from startup_stm32h563xx.o(RESET)
- <LI><a href="#[37]">TIM2_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
+ <LI><a href="#[37]">TIM2_IRQHandler</a> from stm32h5xx_it.o(.text.TIM2_IRQHandler) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[38]">TIM3_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[39]">TIM4_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[3a]">TIM5_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
@@ -161,7 +161,7 @@ Function Pointers
  <LI><a href="#[4c]">TIM8_UP_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[6f]">UART12_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[47]">UART4_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
- <LI><a href="#[48]">UART5_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
+ <LI><a href="#[48]">UART5_IRQHandler</a> from stm32h5xx_it.o(.text.UART5_IRQHandler) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[6c]">UART7_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[6d]">UART8_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
  <LI><a href="#[6e]">UART9_IRQHandler</a> from startup_stm32h563xx.o(.text) referenced from startup_stm32h563xx.o(RESET)
@@ -208,9 +208,9 @@ Global Symbols
 <BR><BR>[Calls]<UL><LI><a href="#[98]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry
 </UL>
 
-<P><STRONG><a name="[134]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+<P><STRONG><a name="[145]"></a>__scatterload_rt2_thumb_only</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
 
-<P><STRONG><a name="[135]"></a>__scatterload_loop</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
+<P><STRONG><a name="[146]"></a>__scatterload_loop</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED)
 
 <P><STRONG><a name="[9a]"></a>__scatterload_copy</STRONG> (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED)
 <BR><BR>[Calls]<UL><LI><a href="#[9a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
@@ -218,9 +218,9 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[9a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_copy
 </UL>
 
-<P><STRONG><a name="[136]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, __scatter.o(!!handler_null), UNUSED)
+<P><STRONG><a name="[147]"></a>__scatterload_null</STRONG> (Thumb, 2 bytes, Stack size unknown bytes, __scatter.o(!!handler_null), UNUSED)
 
-<P><STRONG><a name="[137]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
+<P><STRONG><a name="[148]"></a>__scatterload_zeroinit</STRONG> (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED)
 
 <P><STRONG><a name="[a0]"></a>__rt_lib_init</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000))
 <BR><BR>[Called By]<UL><LI><a href="#[9f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_li
@@ -230,72 +230,72 @@ Global Symbols
 <BR><BR>[Calls]<UL><LI><a href="#[9c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_fp_init
 </UL>
 
-<P><STRONG><a name="[138]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
+<P><STRONG><a name="[149]"></a>__rt_lib_init_alloca_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030))
 
-<P><STRONG><a name="[139]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
+<P><STRONG><a name="[14a]"></a>__rt_lib_init_argv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E))
 
-<P><STRONG><a name="[13a]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
+<P><STRONG><a name="[14b]"></a>__rt_lib_init_atexit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D))
 
-<P><STRONG><a name="[13b]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
+<P><STRONG><a name="[14c]"></a>__rt_lib_init_clock_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023))
 
-<P><STRONG><a name="[13c]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000034))
+<P><STRONG><a name="[14d]"></a>__rt_lib_init_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000034))
 
-<P><STRONG><a name="[13d]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
+<P><STRONG><a name="[14e]"></a>__rt_lib_init_exceptions_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032))
 
-<P><STRONG><a name="[13e]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
+<P><STRONG><a name="[14f]"></a>__rt_lib_init_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021))
 
-<P><STRONG><a name="[13f]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
+<P><STRONG><a name="[150]"></a>__rt_lib_init_getenv_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025))
 
-<P><STRONG><a name="[140]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
+<P><STRONG><a name="[151]"></a>__rt_lib_init_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C))
 
-<P><STRONG><a name="[141]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
+<P><STRONG><a name="[152]"></a>__rt_lib_init_lc_collate_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013))
 
-<P><STRONG><a name="[142]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
+<P><STRONG><a name="[153]"></a>__rt_lib_init_lc_ctype_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015))
 
-<P><STRONG><a name="[143]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
+<P><STRONG><a name="[154]"></a>__rt_lib_init_lc_monetary_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017))
 
-<P><STRONG><a name="[144]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
+<P><STRONG><a name="[155]"></a>__rt_lib_init_lc_numeric_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019))
 
-<P><STRONG><a name="[145]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
+<P><STRONG><a name="[156]"></a>__rt_lib_init_lc_time_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B))
 
-<P><STRONG><a name="[146]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000006))
+<P><STRONG><a name="[157]"></a>__rt_lib_init_preinit_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000006))
 
-<P><STRONG><a name="[147]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000010))
+<P><STRONG><a name="[158]"></a>__rt_lib_init_rand_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000010))
 
-<P><STRONG><a name="[148]"></a>__rt_lib_init_relocate_pie_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
+<P><STRONG><a name="[159]"></a>__rt_lib_init_relocate_pie_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004))
 
-<P><STRONG><a name="[149]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000035))
+<P><STRONG><a name="[15a]"></a>__rt_lib_init_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000035))
 
-<P><STRONG><a name="[14a]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
+<P><STRONG><a name="[15b]"></a>__rt_lib_init_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F))
 
-<P><STRONG><a name="[14b]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000027))
+<P><STRONG><a name="[15c]"></a>__rt_lib_init_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000027))
 
-<P><STRONG><a name="[14c]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
+<P><STRONG><a name="[15d]"></a>__rt_lib_init_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E))
 
 <P><STRONG><a name="[a5]"></a>__rt_lib_shutdown</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000))
 <BR><BR>[Called By]<UL><LI><a href="#[a4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_ls
 </UL>
 
-<P><STRONG><a name="[14d]"></a>__rt_lib_shutdown_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
+<P><STRONG><a name="[15e]"></a>__rt_lib_shutdown_cpp_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002))
 
-<P><STRONG><a name="[14e]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007))
+<P><STRONG><a name="[15f]"></a>__rt_lib_shutdown_fp_trap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007))
 
-<P><STRONG><a name="[14f]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
+<P><STRONG><a name="[160]"></a>__rt_lib_shutdown_heap_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F))
 
-<P><STRONG><a name="[150]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010))
+<P><STRONG><a name="[161]"></a>__rt_lib_shutdown_return</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010))
 
-<P><STRONG><a name="[151]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A))
+<P><STRONG><a name="[162]"></a>__rt_lib_shutdown_signal_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A))
 
-<P><STRONG><a name="[152]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
+<P><STRONG><a name="[163]"></a>__rt_lib_shutdown_stdio_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004))
 
-<P><STRONG><a name="[153]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
+<P><STRONG><a name="[164]"></a>__rt_lib_shutdown_user_alloc_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C))
 
 <P><STRONG><a name="[98]"></a>__rt_entry</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000))
 <BR><BR>[Called By]<UL><LI><a href="#[8b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__main
 <LI><a href="#[99]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__scatterload_rt2
 </UL>
 
-<P><STRONG><a name="[154]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
+<P><STRONG><a name="[165]"></a>__rt_entry_presh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002))
 
 <P><STRONG><a name="[9d]"></a>__rt_entry_sh</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004))
 <BR><BR>[Stack]<UL><LI>Max Depth = 8 + Unknown Stack Size
@@ -308,17 +308,17 @@ Global Symbols
 <BR><BR>[Calls]<UL><LI><a href="#[a0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init
 </UL>
 
-<P><STRONG><a name="[155]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
+<P><STRONG><a name="[166]"></a>__rt_entry_postsh_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009))
 
 <P><STRONG><a name="[a1]"></a>__rt_entry_main</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D))
-<BR><BR>[Stack]<UL><LI>Max Depth = 704 + Unknown Stack Size
-<LI>Call Chain = __rt_entry_main &rArr; main &rArr; MX_USART2_UART_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
+<BR><BR>[Stack]<UL><LI>Max Depth = 720 + Unknown Stack Size
+<LI>Call Chain = __rt_entry_main &rArr; main &rArr; MX_UART5_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
 <BR>[Calls]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 <LI><a href="#[a3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
 </UL>
 
-<P><STRONG><a name="[156]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
+<P><STRONG><a name="[167]"></a>__rt_entry_postli_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C))
 
 <P><STRONG><a name="[b5]"></a>__rt_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000))
 <BR><BR>[Called By]<UL><LI><a href="#[a3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;exit
@@ -328,7 +328,7 @@ Global Symbols
 <BR><BR>[Calls]<UL><LI><a href="#[a5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_shutdown
 </UL>
 
-<P><STRONG><a name="[157]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
+<P><STRONG><a name="[168]"></a>__rt_exit_prels_1</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002))
 
 <P><STRONG><a name="[a6]"></a>__rt_exit_exit</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004))
 <BR><BR>[Calls]<UL><LI><a href="#[a7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_sys_exit
@@ -649,9 +649,6 @@ Global Symbols
 <P><STRONG><a name="[35]"></a>TIM1_TRG_COM_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[37]"></a>TIM2_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
-</UL>
 <P><STRONG><a name="[38]"></a>TIM3_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
@@ -685,9 +682,6 @@ Global Symbols
 <P><STRONG><a name="[47]"></a>UART4_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[48]"></a>UART5_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
-<BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
-</UL>
 <P><STRONG><a name="[6c]"></a>UART7_IRQHandler</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
@@ -722,8 +716,8 @@ Global Symbols
 <BR><BR>[Called By]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
 </UL>
 
-<P><STRONG><a name="[127]"></a>_tx_initialize_low_level</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
+<P><STRONG><a name="[139]"></a>_tx_initialize_low_level</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
 </UL>
 
 <P><STRONG><a name="[a8]"></a>__tx_BadHandler</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED)
@@ -732,7 +726,7 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[a8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__tx_BadHandler
 </UL>
 
-<P><STRONG><a name="[158]"></a>__tx_IntHandler</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED)
+<P><STRONG><a name="[169]"></a>__tx_IntHandler</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED)
 
 <P><STRONG><a name="[a]"></a>SysTick_Handler</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 136 + Unknown Stack Size
@@ -754,17 +748,17 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[ab]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__tx_DBGHandler
 </UL>
 
-<P><STRONG><a name="[129]"></a>_tx_thread_schedule</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
+<P><STRONG><a name="[13b]"></a>_tx_thread_schedule</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
 </UL>
 
 <P><STRONG><a name="[9]"></a>PendSV_Handler</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[159]"></a>_tx_vfp_access</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text), UNUSED)
+<P><STRONG><a name="[16a]"></a>_tx_vfp_access</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text), UNUSED)
 
-<P><STRONG><a name="[12b]"></a>_tx_thread_stack_build</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_stack_build.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<P><STRONG><a name="[13d]"></a>_tx_thread_stack_build</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_stack_build.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
 </UL>
 
 <P><STRONG><a name="[a9]"></a>_tx_timer_interrupt</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, tx_timer_interrupt.o(.text))
@@ -777,37 +771,37 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SysTick_Handler
 </UL>
 
-<P><STRONG><a name="[122]"></a>__aeabi_uldivmod</STRONG> (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text))
+<P><STRONG><a name="[134]"></a>__aeabi_uldivmod</STRONG> (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = __aeabi_uldivmod
 </UL>
-<BR>[Called By]<UL><LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
+<BR>[Called By]<UL><LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
 </UL>
 
-<P><STRONG><a name="[15a]"></a>_ll_udiv</STRONG> (Thumb, 240 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED)
+<P><STRONG><a name="[16b]"></a>_ll_udiv</STRONG> (Thumb, 240 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED)
 
-<P><STRONG><a name="[f8]"></a>__aeabi_memcpy</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<P><STRONG><a name="[106]"></a>__aeabi_memcpy</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
 </UL>
 
 <P><STRONG><a name="[ae]"></a>__rt_memcpy</STRONG> (Thumb, 138 bytes, Stack size 0 bytes, rt_memcpy_v6.o(.text), UNUSED)
 <BR><BR>[Calls]<UL><LI><a href="#[af]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memcpy4
 </UL>
 
-<P><STRONG><a name="[15b]"></a>_memcpy_lastbytes</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED)
+<P><STRONG><a name="[16c]"></a>_memcpy_lastbytes</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_v6.o(.text), UNUSED)
 
 <P><STRONG><a name="[b0]"></a>__aeabi_memset</STRONG> (Thumb, 16 bytes, Stack size 0 bytes, aeabi_memset.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = __aeabi_memset &rArr; _memset &rArr; _memset_w
 </UL>
 <BR>[Calls]<UL><LI><a href="#[b1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_memset
 </UL>
-<BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<BR>[Called By]<UL><LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
 </UL>
 
-<P><STRONG><a name="[115]"></a>__aeabi_memclr</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<P><STRONG><a name="[122]"></a>__aeabi_memclr</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 
-<P><STRONG><a name="[15c]"></a>__rt_memclr</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text), UNUSED)
+<P><STRONG><a name="[16d]"></a>__rt_memclr</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text), UNUSED)
 
 <P><STRONG><a name="[b1]"></a>_memset</STRONG> (Thumb, 64 bytes, Stack size 0 bytes, rt_memclr.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = _memset &rArr; _memset_w
@@ -817,20 +811,20 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[b0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memset
 </UL>
 
-<P><STRONG><a name="[10b]"></a>__aeabi_memclr4</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
-<LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
-<LI><a href="#[123]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_byte_pool_create
-<LI><a href="#[126]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
-<LI><a href="#[125]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_initialize
-<LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<P><STRONG><a name="[119]"></a>__aeabi_memclr4</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
+<LI><a href="#[135]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_byte_pool_create
+<LI><a href="#[138]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
+<LI><a href="#[137]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_initialize
+<LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
 </UL>
 
-<P><STRONG><a name="[10c]"></a>__aeabi_memclr8</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text))
-<BR><BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<P><STRONG><a name="[11a]"></a>__aeabi_memclr8</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text))
+<BR><BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
-<P><STRONG><a name="[15d]"></a>__rt_memclr_w</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED)
+<P><STRONG><a name="[16e]"></a>__rt_memclr_w</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED)
 
 <P><STRONG><a name="[b2]"></a>_memset_w</STRONG> (Thumb, 74 bytes, Stack size 4 bytes, rt_memclr_w.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = _memset_w
@@ -838,29 +832,29 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[b1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_memset
 </UL>
 
-<P><STRONG><a name="[15e]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+<P><STRONG><a name="[16f]"></a>__use_two_region_memory</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
 
-<P><STRONG><a name="[15f]"></a>__rt_heap_escrow$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+<P><STRONG><a name="[170]"></a>__rt_heap_escrow$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
 
-<P><STRONG><a name="[160]"></a>__rt_heap_expand$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
+<P><STRONG><a name="[171]"></a>__rt_heap_expand$2region</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED)
 
 <P><STRONG><a name="[af]"></a>__aeabi_memcpy4</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
 <BR><BR>[Called By]<UL><LI><a href="#[ae]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_memcpy
 </UL>
 
-<P><STRONG><a name="[161]"></a>__aeabi_memcpy8</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+<P><STRONG><a name="[172]"></a>__aeabi_memcpy8</STRONG> (Thumb, 0 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
 
-<P><STRONG><a name="[162]"></a>__rt_memcpy_w</STRONG> (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
+<P><STRONG><a name="[173]"></a>__rt_memcpy_w</STRONG> (Thumb, 100 bytes, Stack size 8 bytes, rt_memcpy_w.o(.text), UNUSED)
 
-<P><STRONG><a name="[163]"></a>_memcpy_lastbytes_aligned</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED)
+<P><STRONG><a name="[174]"></a>_memcpy_lastbytes_aligned</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, rt_memcpy_w.o(.text), UNUSED)
 
-<P><STRONG><a name="[164]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+<P><STRONG><a name="[175]"></a>__user_libspace</STRONG> (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
 
 <P><STRONG><a name="[b3]"></a>__user_perproc_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text))
 <BR><BR>[Called By]<UL><LI><a href="#[9e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__user_setup_stackheap
 </UL>
 
-<P><STRONG><a name="[165]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
+<P><STRONG><a name="[176]"></a>__user_perthread_libspace</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED)
 
 <P><STRONG><a name="[9e]"></a>__user_setup_stackheap</STRONG> (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text))
 <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = __user_setup_stackheap
@@ -884,16 +878,16 @@ Global Symbols
 <BR><BR>[Called By]<UL><LI><a href="#[a6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_exit_exit
 </UL>
 
-<P><STRONG><a name="[166]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+<P><STRONG><a name="[177]"></a>__I$use$semihosting</STRONG> (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
 
-<P><STRONG><a name="[167]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
+<P><STRONG><a name="[178]"></a>__use_no_semihosting_swi</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED)
 
-<P><STRONG><a name="[168]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
+<P><STRONG><a name="[179]"></a>__semihosting_library_function</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED)
 
-<P><STRONG><a name="[133]"></a>App_ThreadX_Init</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, app_threadx.o(.text.App_ThreadX_Init))
+<P><STRONG><a name="[144]"></a>App_ThreadX_Init</STRONG> (Thumb, 14 bytes, Stack size 8 bytes, app_threadx.o(.text.App_ThreadX_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = App_ThreadX_Init
 </UL>
-<BR>[Called By]<UL><LI><a href="#[128]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
+<BR>[Called By]<UL><LI><a href="#[13a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
 </UL>
 
 <P><STRONG><a name="[4]"></a>BusFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.BusFault_Handler))
@@ -902,11 +896,13 @@ Global Symbols
 <P><STRONG><a name="[8]"></a>DebugMon_Handler</STRONG> (Thumb, 2 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.DebugMon_Handler))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[10d]"></a>Error_Handler</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, main.o(.text.Error_Handler))
-<BR><BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
-<LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
-<LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
+<P><STRONG><a name="[11b]"></a>Error_Handler</STRONG> (Thumb, 6 bytes, Stack size 0 bytes, main.o(.text.Error_Handler))
+<BR><BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
 </UL>
 
 <P><STRONG><a name="[29]"></a>GPDMA1_Channel3_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.GPDMA1_Channel3_IRQHandler))
@@ -935,16 +931,16 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[b8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_BuildNode
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[b9]"></a>HAL_DMAEx_List_Init</STRONG> (Thumb, 898 bytes, Stack size 24 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_DMAEx_List_Init &rArr; DMA_List_Init
 </UL>
-<BR>[Calls]<UL><LI><a href="#[bb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_Init
-<LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+<LI><a href="#[bb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_Init
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[bc]"></a>HAL_DMAEx_List_InsertNode</STRONG> (Thumb, 410 bytes, Stack size 56 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode))
@@ -955,13 +951,13 @@ Global Symbols
 <LI><a href="#[bd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_CheckNodesBaseAddresses
 <LI><a href="#[bf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_GetCLLRNodeInfo
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
-<P><STRONG><a name="[10f]"></a>HAL_DMAEx_List_LinkQ</STRONG> (Thumb, 418 bytes, Stack size 20 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ))
+<P><STRONG><a name="[11c]"></a>HAL_DMAEx_List_LinkQ</STRONG> (Thumb, 418 bytes, Stack size 20 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = HAL_DMAEx_List_LinkQ
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[c1]"></a>HAL_DMAEx_List_SetCircularMode</STRONG> (Thumb, 202 bytes, Stack size 48 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode))
@@ -970,7 +966,7 @@ Global Symbols
 <BR>[Calls]<UL><LI><a href="#[c0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_FindNode
 <LI><a href="#[bf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_GetCLLRNodeInfo
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[c2]"></a>HAL_DMAEx_List_Start_IT</STRONG> (Thumb, 326 bytes, Stack size 32 bytes, stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT))
@@ -978,7 +974,7 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[bf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_List_GetCLLRNodeInfo
 </UL>
-<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
+<BR>[Called By]<UL><LI><a href="#[104]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
 </UL>
 
 <P><STRONG><a name="[c3]"></a>HAL_DMA_Abort</STRONG> (Thumb, 278 bytes, Stack size 24 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort))
@@ -986,26 +982,26 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
-<LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
+<LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[100]"></a>HAL_DMA_Abort_IT</STRONG> (Thumb, 84 bytes, Stack size 8 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT))
+<P><STRONG><a name="[10e]"></a>HAL_DMA_Abort_IT</STRONG> (Thumb, 84 bytes, Stack size 8 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT))
 <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HAL_DMA_Abort_IT
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[110]"></a>HAL_DMA_ConfigChannelAttributes</STRONG> (Thumb, 114 bytes, Stack size 20 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes))
+<P><STRONG><a name="[11d]"></a>HAL_DMA_ConfigChannelAttributes</STRONG> (Thumb, 114 bytes, Stack size 20 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = HAL_DMA_ConfigChannelAttributes
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
-<P><STRONG><a name="[fd]"></a>HAL_DMA_GetError</STRONG> (Thumb, 12 bytes, Stack size 4 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError))
+<P><STRONG><a name="[10b]"></a>HAL_DMA_GetError</STRONG> (Thumb, 12 bytes, Stack size 4 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_DMA_GetError
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
+<BR>[Called By]<UL><LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
 </UL>
 
 <P><STRONG><a name="[b6]"></a>HAL_DMA_IRQHandler</STRONG> (Thumb, 724 bytes, Stack size 24 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_IRQHandler))
@@ -1019,10 +1015,10 @@ Global Symbols
 <P><STRONG><a name="[c4]"></a>HAL_DMA_Init</STRONG> (Thumb, 960 bytes, Stack size 24 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 44<LI>Call Chain = HAL_DMA_Init &rArr; DMA_Init
 </UL>
-<BR>[Calls]<UL><LI><a href="#[c5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_Init
-<LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+<LI><a href="#[c5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_Init
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[c6]"></a>HAL_DMA_Start_IT</STRONG> (Thumb, 226 bytes, Stack size 32 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT))
@@ -1030,34 +1026,42 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[c7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;DMA_SetConfig
 </UL>
-<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
+<BR>[Called By]<UL><LI><a href="#[104]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
 </UL>
 
-<P><STRONG><a name="[10e]"></a>HAL_GPIO_Init</STRONG> (Thumb, 746 bytes, Stack size 20 bytes, stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init))
+<P><STRONG><a name="[e7]"></a>HAL_GPIO_Init</STRONG> (Thumb, 746 bytes, Stack size 20 bytes, stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = HAL_GPIO_Init
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_MspInit
+<LI><a href="#[125]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
+</UL>
+
+<P><STRONG><a name="[126]"></a>HAL_GPIO_WritePin</STRONG> (Thumb, 44 bytes, Stack size 8 bytes, stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin))
+<BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = HAL_GPIO_WritePin
+</UL>
+<BR>[Called By]<UL><LI><a href="#[125]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
 </UL>
 
 <P><STRONG><a name="[ba]"></a>HAL_GetTick</STRONG> (Thumb, 12 bytes, Stack size 0 bytes, stm32h5xx_hal.o(.text.HAL_GetTick))
 <BR><BR>[Called By]<UL><LI><a href="#[e2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCCEx_PLL3_Config
 <LI><a href="#[e1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCCEx_PLL2_Config
-<LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort
 <LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Init
 <LI><a href="#[b9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_Init
 <LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
 <LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
 <LI><a href="#[e4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_OscConfig
-<LI><a href="#[11e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
-<LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
+<LI><a href="#[130]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
+<LI><a href="#[118]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
+<LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort
 </UL>
 
-<P><STRONG><a name="[f4]"></a>HAL_IncTick</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32h5xx_hal.o(.text.HAL_IncTick))
-<BR><BR>[Called By]<UL><LI><a href="#[eb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PeriodElapsedCallback
+<P><STRONG><a name="[102]"></a>HAL_IncTick</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, stm32h5xx_hal.o(.text.HAL_IncTick))
+<BR><BR>[Called By]<UL><LI><a href="#[f9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PeriodElapsedCallback
 </UL>
 
 <P><STRONG><a name="[c8]"></a>HAL_Init</STRONG> (Thumb, 94 bytes, Stack size 16 bytes, stm32h5xx_hal.o(.text.HAL_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = HAL_Init &rArr; HAL_InitTick &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+<BR><BR>[Stack]<UL><LI>Max Depth = 200<LI>Call Chain = HAL_Init &rArr; HAL_InitTick &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
 <LI><a href="#[cb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_SYSTICK_CLKSourceConfig
@@ -1069,12 +1073,12 @@ Global Symbols
 </UL>
 
 <P><STRONG><a name="[cc]"></a>HAL_InitTick</STRONG> (Thumb, 206 bytes, Stack size 56 bytes, stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick))
-<BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = HAL_InitTick &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+<BR><BR>[Stack]<UL><LI>Max Depth = 184<LI>Call Chain = HAL_InitTick &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[d1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Start_IT
-<LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
 <LI><a href="#[cf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK2Freq
 <LI><a href="#[ce]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetClockConfig
+<LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
 <LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_EnableIRQ
 <LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriority
 </UL>
@@ -1093,8 +1097,9 @@ Global Symbols
 <BR>[Calls]<UL><LI><a href="#[d4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__NVIC_EnableIRQ
 </UL>
 <BR>[Called By]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
-<LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
-<LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
+<LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_MspInit
+<LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
 </UL>
 
 <P><STRONG><a name="[d2]"></a>HAL_NVIC_SetPriority</STRONG> (Thumb, 46 bytes, Stack size 32 bytes, stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority))
@@ -1105,8 +1110,9 @@ Global Symbols
 <LI><a href="#[d5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__NVIC_GetPriorityGrouping
 </UL>
 <BR>[Called By]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
-<LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
-<LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
+<LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_MspInit
+<LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
 </UL>
 
 <P><STRONG><a name="[c9]"></a>HAL_NVIC_SetPriorityGrouping</STRONG> (Thumb, 16 bytes, Stack size 16 bytes, stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping))
@@ -1138,16 +1144,16 @@ Global Symbols
 <P><STRONG><a name="[d9]"></a>HAL_RCCEx_GetPeriphCLKFreq</STRONG> (Thumb, 10488 bytes, Stack size 120 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq))
 <BR><BR>[Stack]<UL><LI>Max Depth = 172<LI>Call Chain = HAL_RCCEx_GetPeriphCLKFreq &rArr; HAL_RCC_GetPCLK3Freq &rArr; HAL_RCC_GetHCLKFreq &rArr; HAL_RCC_GetSysClockFreq
 </UL>
-<BR>[Calls]<UL><LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK3Freq
+<BR>[Calls]<UL><LI><a href="#[dc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL3ClockFreq
+<LI><a href="#[db]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL2ClockFreq
+<LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL1ClockFreq
+<LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK3Freq
 <LI><a href="#[dd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK1Freq
 <LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
 <LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetHCLKFreq
 <LI><a href="#[cf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK2Freq
-<LI><a href="#[dc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL3ClockFreq
-<LI><a href="#[db]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL2ClockFreq
-<LI><a href="#[da]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPLL1ClockFreq
 </UL>
-<BR>[Called By]<UL><LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
+<BR>[Called By]<UL><LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
 </UL>
 
 <P><STRONG><a name="[e0]"></a>HAL_RCCEx_PeriphCLKConfig</STRONG> (Thumb, 6382 bytes, Stack size 184 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig))
@@ -1157,17 +1163,17 @@ Global Symbols
 <LI><a href="#[e1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;RCCEx_PLL2_Config
 <LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
 </UL>
-<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<BR>[Called By]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
 </UL>
 
 <P><STRONG><a name="[e3]"></a>HAL_RCC_ClockConfig</STRONG> (Thumb, 1172 bytes, Stack size 32 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig))
-<BR><BR>[Stack]<UL><LI>Max Depth = 152<LI>Call Chain = HAL_RCC_ClockConfig &rArr; HAL_InitTick &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+<BR><BR>[Stack]<UL><LI>Max Depth = 216<LI>Call Chain = HAL_RCC_ClockConfig &rArr; HAL_InitTick &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
 <LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
 <LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
+<BR>[Called By]<UL><LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
 </UL>
 
 <P><STRONG><a name="[ce]"></a>HAL_RCC_GetClockConfig</STRONG> (Thumb, 108 bytes, Stack size 12 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig))
@@ -1181,11 +1187,11 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ca]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetSysClockFreq
 </UL>
-<BR>[Called By]<UL><LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK3Freq
+<BR>[Called By]<UL><LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
+<LI><a href="#[de]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK3Freq
 <LI><a href="#[dd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK1Freq
 <LI><a href="#[cf]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetPCLK2Freq
 <LI><a href="#[e4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_OscConfig
-<LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
 </UL>
 
 <P><STRONG><a name="[dd]"></a>HAL_RCC_GetPCLK1Freq</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq))
@@ -1201,8 +1207,8 @@ Global Symbols
 </UL>
 <BR>[Calls]<UL><LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetHCLKFreq
 </UL>
-<BR>[Called By]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
-<LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
+<BR>[Called By]<UL><LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
+<LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
 </UL>
 
 <P><STRONG><a name="[de]"></a>HAL_RCC_GetPCLK3Freq</STRONG> (Thumb, 38 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq))
@@ -1216,20 +1222,20 @@ Global Symbols
 <P><STRONG><a name="[ca]"></a>HAL_RCC_GetSysClockFreq</STRONG> (Thumb, 700 bytes, Stack size 36 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq))
 <BR><BR>[Stack]<UL><LI>Max Depth = 36<LI>Call Chain = HAL_RCC_GetSysClockFreq
 </UL>
-<BR>[Called By]<UL><LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetHCLKFreq
+<BR>[Called By]<UL><LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
+<LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetHCLKFreq
 <LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
 <LI><a href="#[c8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
-<LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
 </UL>
 
 <P><STRONG><a name="[e4]"></a>HAL_RCC_OscConfig</STRONG> (Thumb, 2556 bytes, Stack size 40 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig))
-<BR><BR>[Stack]<UL><LI>Max Depth = 160<LI>Call Chain = HAL_RCC_OscConfig &rArr; HAL_InitTick &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+<BR><BR>[Stack]<UL><LI>Max Depth = 224<LI>Call Chain = HAL_RCC_OscConfig &rArr; HAL_InitTick &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[df]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_GetHCLKFreq
 <LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
 <LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
+<BR>[Called By]<UL><LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
 </UL>
 
 <P><STRONG><a name="[cb]"></a>HAL_SYSTICK_CLKSourceConfig</STRONG> (Thumb, 154 bytes, Stack size 8 bytes, stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig))
@@ -1238,59 +1244,70 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[c8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
 </UL>
 
-<P><STRONG><a name="[ed]"></a>HAL_TIMEx_Break2Callback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback))
+<P><STRONG><a name="[fb]"></a>HAL_TIMEx_Break2Callback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_Break2Callback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[ec]"></a>HAL_TIMEx_BreakCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback))
+<P><STRONG><a name="[fa]"></a>HAL_TIMEx_BreakCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_BreakCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[ef]"></a>HAL_TIMEx_CommutCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback))
+<P><STRONG><a name="[fd]"></a>HAL_TIMEx_CommutCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_CommutCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[f1]"></a>HAL_TIMEx_DirectionChangeCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback))
+<P><STRONG><a name="[ff]"></a>HAL_TIMEx_DirectionChangeCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_DirectionChangeCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[f0]"></a>HAL_TIMEx_EncoderIndexCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback))
+<P><STRONG><a name="[fe]"></a>HAL_TIMEx_EncoderIndexCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_EncoderIndexCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[f2]"></a>HAL_TIMEx_IndexErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback))
+<P><STRONG><a name="[100]"></a>HAL_TIMEx_IndexErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_IndexErrorCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[f3]"></a>HAL_TIMEx_TransitionErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback))
+<P><STRONG><a name="[128]"></a>HAL_TIMEx_MasterConfigSynchronization</STRONG> (Thumb, 530 bytes, Stack size 20 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization))
+<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = HAL_TIMEx_MasterConfigSynchronization
+</UL>
+<BR>[Called By]<UL><LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
+</UL>
+
+<P><STRONG><a name="[101]"></a>HAL_TIMEx_TransitionErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIMEx_TransitionErrorCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
 <P><STRONG><a name="[d0]"></a>HAL_TIM_Base_Init</STRONG> (Thumb, 168 bytes, Stack size 16 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = HAL_TIM_Base_Init &rArr; TIM_Base_SetConfig
+<BR><BR>[Stack]<UL><LI>Max Depth = 128<LI>Call Chain = HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[e6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_Base_SetConfig
 <LI><a href="#[e5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_MspInit
 </UL>
 <BR>[Called By]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
+<LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
 </UL>
 
-<P><STRONG><a name="[e5]"></a>HAL_TIM_Base_MspInit</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_Base_MspInit
+<P><STRONG><a name="[e5]"></a>HAL_TIM_Base_MspInit</STRONG> (Thumb, 144 bytes, Stack size 48 bytes, tim.o(.text.HAL_TIM_Base_MspInit))
+<BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+</UL>
+<BR>[Calls]<UL><LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_EnableIRQ
+<LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriority
+<LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
 </UL>
 <BR>[Called By]<UL><LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
 </UL>
@@ -1301,79 +1318,126 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[cc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_InitTick
 </UL>
 
-<P><STRONG><a name="[e8]"></a>HAL_TIM_IC_CaptureCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback))
-<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_IC_CaptureCallback
+<P><STRONG><a name="[e8]"></a>HAL_TIM_ConfigClockSource</STRONG> (Thumb, 520 bytes, Stack size 32 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource))
+<BR><BR>[Stack]<UL><LI>Max Depth = 52<LI>Call Chain = HAL_TIM_ConfigClockSource &rArr; TIM_ETR_SetConfig
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Calls]<UL><LI><a href="#[e9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_ETR_SetConfig
+<LI><a href="#[ec]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI2_ConfigInputStage
+<LI><a href="#[eb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_ITRx_SetConfig
+<LI><a href="#[ea]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI1_ConfigInputStage
+</UL>
+<BR>[Called By]<UL><LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
 </UL>
 
-<P><STRONG><a name="[e7]"></a>HAL_TIM_IRQHandler</STRONG> (Thumb, 768 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_TIM_IRQHandler &rArr; HAL_TIM_PeriodElapsedCallback
+<P><STRONG><a name="[ed]"></a>HAL_TIM_IC_CaptureCallback</STRONG> (Thumb, 266 bytes, Stack size 24 bytes, ultrasound.o(.text.HAL_TIM_IC_CaptureCallback))
+<BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = HAL_TIM_IC_CaptureCallback &rArr; HAL_TIM_ReadCapturedValue
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_TransitionErrorCallback
-<LI><a href="#[f2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_IndexErrorCallback
-<LI><a href="#[f1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_DirectionChangeCallback
-<LI><a href="#[f0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_EncoderIndexCallback
-<LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_CommutCallback
-<LI><a href="#[ee]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_TriggerCallback
-<LI><a href="#[ed]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_Break2Callback
-<LI><a href="#[ec]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_BreakCallback
-<LI><a href="#[e9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_OC_DelayElapsedCallback
-<LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_CaptureCallback
-<LI><a href="#[ea]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PWM_PulseFinishedCallback
-<LI><a href="#[eb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PeriodElapsedCallback
+<BR>[Calls]<UL><LI><a href="#[ee]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ReadCapturedValue
 </UL>
-<BR>[Called By]<UL><LI><a href="#[34]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM1_UP_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[e9]"></a>HAL_TIM_OC_DelayElapsedCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback))
+<P><STRONG><a name="[ef]"></a>HAL_TIM_IC_ConfigChannel</STRONG> (Thumb, 304 bytes, Stack size 32 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel))
+<BR><BR>[Stack]<UL><LI>Max Depth = 60<LI>Call Chain = HAL_TIM_IC_ConfigChannel &rArr; TIM_TI1_SetConfig
+</UL>
+<BR>[Calls]<UL><LI><a href="#[f0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI1_SetConfig
+<LI><a href="#[f3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI4_SetConfig
+<LI><a href="#[f2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI3_SetConfig
+<LI><a href="#[f1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_TI2_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
+</UL>
+
+<P><STRONG><a name="[f4]"></a>HAL_TIM_IC_Init</STRONG> (Thumb, 168 bytes, Stack size 16 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = HAL_TIM_IC_Init &rArr; TIM_Base_SetConfig
+</UL>
+<BR>[Calls]<UL><LI><a href="#[f5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_MspInit
+<LI><a href="#[e6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM_Base_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
+</UL>
+
+<P><STRONG><a name="[f5]"></a>HAL_TIM_IC_MspInit</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit))
+<BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_IC_MspInit
+</UL>
+<BR>[Called By]<UL><LI><a href="#[f4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_Init
+</UL>
+
+<P><STRONG><a name="[f6]"></a>HAL_TIM_IRQHandler</STRONG> (Thumb, 768 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler))
+<BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = HAL_TIM_IRQHandler &rArr; HAL_TIM_IC_CaptureCallback &rArr; HAL_TIM_ReadCapturedValue
+</UL>
+<BR>[Calls]<UL><LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_TransitionErrorCallback
+<LI><a href="#[100]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_IndexErrorCallback
+<LI><a href="#[ff]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_DirectionChangeCallback
+<LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_EncoderIndexCallback
+<LI><a href="#[fd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_CommutCallback
+<LI><a href="#[fc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_TriggerCallback
+<LI><a href="#[fb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_Break2Callback
+<LI><a href="#[fa]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_BreakCallback
+<LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_OC_DelayElapsedCallback
+<LI><a href="#[f8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PWM_PulseFinishedCallback
+<LI><a href="#[f9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_PeriodElapsedCallback
+<LI><a href="#[ed]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_CaptureCallback
+</UL>
+<BR>[Called By]<UL><LI><a href="#[37]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM2_IRQHandler
+<LI><a href="#[34]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;TIM1_UP_IRQHandler
+</UL>
+
+<P><STRONG><a name="[f7]"></a>HAL_TIM_OC_DelayElapsedCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_OC_DelayElapsedCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[ea]"></a>HAL_TIM_PWM_PulseFinishedCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback))
+<P><STRONG><a name="[f8]"></a>HAL_TIM_PWM_PulseFinishedCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_PWM_PulseFinishedCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[eb]"></a>HAL_TIM_PeriodElapsedCallback</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, main.o(.text.HAL_TIM_PeriodElapsedCallback))
+<P><STRONG><a name="[f9]"></a>HAL_TIM_PeriodElapsedCallback</STRONG> (Thumb, 34 bytes, Stack size 16 bytes, main.o(.text.HAL_TIM_PeriodElapsedCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = HAL_TIM_PeriodElapsedCallback
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_IncTick
+<BR>[Calls]<UL><LI><a href="#[102]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_IncTick
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[ee]"></a>HAL_TIM_TriggerCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback))
+<P><STRONG><a name="[ee]"></a>HAL_TIM_ReadCapturedValue</STRONG> (Thumb, 86 bytes, Stack size 16 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue))
+<BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = HAL_TIM_ReadCapturedValue
+</UL>
+<BR>[Called By]<UL><LI><a href="#[ed]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_CaptureCallback
+</UL>
+
+<P><STRONG><a name="[fc]"></a>HAL_TIM_TriggerCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_TIM_TriggerCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 
-<P><STRONG><a name="[11b]"></a>HAL_UARTEx_DisableFifoMode</STRONG> (Thumb, 124 bytes, Stack size 12 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode))
+<P><STRONG><a name="[12c]"></a>HAL_UARTEx_DisableFifoMode</STRONG> (Thumb, 124 bytes, Stack size 12 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode))
 <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = HAL_UARTEx_DisableFifoMode
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<BR>[Called By]<UL><LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
 </UL>
 
-<P><STRONG><a name="[f5]"></a>HAL_UARTEx_ReceiveToIdle_DMA</STRONG> (Thumb, 176 bytes, Stack size 32 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA))
+<P><STRONG><a name="[103]"></a>HAL_UARTEx_ReceiveToIdle_DMA</STRONG> (Thumb, 176 bytes, Stack size 32 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA))
 <BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
+<BR>[Calls]<UL><LI><a href="#[104]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
 </UL>
-<BR>[Called By]<UL><LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<BR>[Called By]<UL><LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
 </UL>
 
-<P><STRONG><a name="[f7]"></a>HAL_UARTEx_RxEventCallback</STRONG> (Thumb, 112 bytes, Stack size 24 bytes, gps.o(.text.HAL_UARTEx_RxEventCallback))
+<P><STRONG><a name="[105]"></a>HAL_UARTEx_RxEventCallback</STRONG> (Thumb, 112 bytes, Stack size 24 bytes, gps.o(.text.HAL_UARTEx_RxEventCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 144<LI>Call Chain = HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_ReceiveToIdle_DMA
-<LI><a href="#[f8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memcpy
+<BR>[Calls]<UL><LI><a href="#[103]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_ReceiveToIdle_DMA
+<LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memcpy
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 <LI><a href="#[90]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMARxHalfCplt
 <LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAReceiveCplt
 <LI><a href="#[8e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_8BIT
@@ -1382,135 +1446,139 @@ Global Symbols
 <LI><a href="#[92]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_16BIT_FIFOEN
 </UL>
 
-<P><STRONG><a name="[105]"></a>HAL_UARTEx_RxFifoFullCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback))
+<P><STRONG><a name="[113]"></a>HAL_UARTEx_RxFifoFullCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UARTEx_RxFifoFullCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[f9]"></a>HAL_UARTEx_SetRxFifoThreshold</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold))
+<P><STRONG><a name="[107]"></a>HAL_UARTEx_SetRxFifoThreshold</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold))
 <BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = HAL_UARTEx_SetRxFifoThreshold &rArr; UARTEx_SetNbDataToProcess
 </UL>
-<BR>[Calls]<UL><LI><a href="#[fa]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UARTEx_SetNbDataToProcess
+<BR>[Calls]<UL><LI><a href="#[108]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UARTEx_SetNbDataToProcess
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<BR>[Called By]<UL><LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
 </UL>
 
-<P><STRONG><a name="[fb]"></a>HAL_UARTEx_SetTxFifoThreshold</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold))
+<P><STRONG><a name="[109]"></a>HAL_UARTEx_SetTxFifoThreshold</STRONG> (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold))
 <BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = HAL_UARTEx_SetTxFifoThreshold &rArr; UARTEx_SetNbDataToProcess
 </UL>
-<BR>[Calls]<UL><LI><a href="#[fa]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UARTEx_SetNbDataToProcess
+<BR>[Calls]<UL><LI><a href="#[108]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UARTEx_SetNbDataToProcess
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<BR>[Called By]<UL><LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
 </UL>
 
-<P><STRONG><a name="[104]"></a>HAL_UARTEx_TxFifoEmptyCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback))
+<P><STRONG><a name="[112]"></a>HAL_UARTEx_TxFifoEmptyCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UARTEx_TxFifoEmptyCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[102]"></a>HAL_UARTEx_WakeupCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback))
+<P><STRONG><a name="[110]"></a>HAL_UARTEx_WakeupCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UARTEx_WakeupCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[fc]"></a>HAL_UART_AbortReceive</STRONG> (Thumb, 278 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive))
+<P><STRONG><a name="[10a]"></a>HAL_UART_AbortReceive</STRONG> (Thumb, 278 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive))
 <BR><BR>[Stack]<UL><LI>Max Depth = 56<LI>Call Chain = HAL_UART_AbortReceive &rArr; HAL_DMA_Abort
 </UL>
-<BR>[Calls]<UL><LI><a href="#[fd]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_GetError
+<BR>[Calls]<UL><LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_GetError
 <LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort
 </UL>
 <BR>[Called By]<UL><LI><a href="#[44]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART1_IRQHandler
 </UL>
 
-<P><STRONG><a name="[101]"></a>HAL_UART_ErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback))
+<P><STRONG><a name="[10f]"></a>HAL_UART_ErrorCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UART_ErrorCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 <LI><a href="#[8c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAAbortOnError
 <LI><a href="#[91]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAError
 <LI><a href="#[93]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_8BIT_FIFOEN
 <LI><a href="#[92]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_16BIT_FIFOEN
 </UL>
 
-<P><STRONG><a name="[fe]"></a>HAL_UART_IRQHandler</STRONG> (Thumb, 1346 bytes, Stack size 64 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler))
+<P><STRONG><a name="[10c]"></a>HAL_UART_IRQHandler</STRONG> (Thumb, 1346 bytes, Stack size 64 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler))
 <BR><BR>[Stack]<UL><LI>Max Depth = 208<LI>Call Chain = HAL_UART_IRQHandler &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort
-<LI><a href="#[100]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort_IT
-<LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxFifoFullCallback
-<LI><a href="#[104]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_TxFifoEmptyCallback
-<LI><a href="#[102]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_WakeupCallback
-<LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
-<LI><a href="#[103]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTransmit_IT
-<LI><a href="#[ff]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
-<LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<BR>[Calls]<UL><LI><a href="#[10e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort_IT
+<LI><a href="#[113]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxFifoFullCallback
+<LI><a href="#[112]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_TxFifoEmptyCallback
+<LI><a href="#[110]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_WakeupCallback
+<LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
+<LI><a href="#[111]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTransmit_IT
+<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
+<LI><a href="#[c3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Abort
+<LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[45]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART2_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[48]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART5_IRQHandler
+<LI><a href="#[45]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART2_IRQHandler
 <LI><a href="#[44]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART1_IRQHandler
 </UL>
 
-<P><STRONG><a name="[106]"></a>HAL_UART_Init</STRONG> (Thumb, 170 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 672 + Unknown Stack Size
+<P><STRONG><a name="[114]"></a>HAL_UART_Init</STRONG> (Thumb, 170 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 688 + Unknown Stack Size
 <LI>Call Chain = HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
-<BR>[Calls]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
-<LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
-<LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
-<LI><a href="#[108]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_AdvFeatureConfig
+<BR>[Calls]<UL><LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_MspInit
+<LI><a href="#[118]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
+<LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_SetConfig
+<LI><a href="#[116]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_AdvFeatureConfig
 </UL>
-<BR>[Called By]<UL><LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<BR>[Called By]<UL><LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
 </UL>
 
-<P><STRONG><a name="[107]"></a>HAL_UART_MspInit</STRONG> (Thumb, 968 bytes, Stack size 448 bytes, usart.o(.text.HAL_UART_MspInit))
-<BR><BR>[Stack]<UL><LI>Max Depth = 656 + Unknown Stack Size
+<P><STRONG><a name="[115]"></a>HAL_UART_MspInit</STRONG> (Thumb, 1130 bytes, Stack size 464 bytes, usart.o(.text.HAL_UART_MspInit))
+<BR><BR>[Stack]<UL><LI>Max Depth = 672 + Unknown Stack Size
 <LI>Call Chain = HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
 <BR>[Calls]<UL><LI><a href="#[c4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Init
-<LI><a href="#[110]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_ConfigChannelAttributes
-<LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_LinkQ
+<LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_ConfigChannelAttributes
+<LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_LinkQ
 <LI><a href="#[b9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_Init
 <LI><a href="#[c1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_SetCircularMode
 <LI><a href="#[bc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_InsertNode
 <LI><a href="#[b7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_BuildNode
-<LI><a href="#[10e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
 <LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
 <LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_EnableIRQ
 <LI><a href="#[d2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_SetPriority
-<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
-<LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr8
-<LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
+<LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr8
+<LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
-<BR>[Called By]<UL><LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
 </UL>
 
-<P><STRONG><a name="[111]"></a>HAL_UART_Receive_DMA</STRONG> (Thumb, 178 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA))
+<P><STRONG><a name="[11e]"></a>HAL_UART_Receive_DMA</STRONG> (Thumb, 178 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA))
 <BR><BR>[Stack]<UL><LI>Max Depth = 120<LI>Call Chain = HAL_UART_Receive_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
+<BR>[Calls]<UL><LI><a href="#[104]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_DMA
 </UL>
-<BR>[Called By]<UL><LI><a href="#[116]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HCBle_InitDMAReception
+<BR>[Called By]<UL><LI><a href="#[123]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HCBle_InitDMAReception
 </UL>
 
-<P><STRONG><a name="[112]"></a>HAL_UART_Receive_IT</STRONG> (Thumb, 206 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT))
+<P><STRONG><a name="[11f]"></a>HAL_UART_Receive_IT</STRONG> (Thumb, 206 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT))
 <BR><BR>[Stack]<UL><LI>Max Depth = 64<LI>Call Chain = HAL_UART_Receive_IT &rArr; UART_Start_Receive_IT
 </UL>
-<BR>[Calls]<UL><LI><a href="#[113]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_IT
+<BR>[Calls]<UL><LI><a href="#[120]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_Start_Receive_IT
 </UL>
-<BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Called By]<UL><LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 
-<P><STRONG><a name="[114]"></a>HAL_UART_RxCpltCallback</STRONG> (Thumb, 166 bytes, Stack size 16 bytes, hcble.o(.text.HAL_UART_RxCpltCallback))
+<P><STRONG><a name="[121]"></a>HAL_UART_RxCpltCallback</STRONG> (Thumb, 166 bytes, Stack size 16 bytes, hcble.o(.text.HAL_UART_RxCpltCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 80 + Unknown Stack Size
 <LI>Call Chain = HAL_UART_RxCpltCallback &rArr; HAL_UART_Receive_IT &rArr; UART_Start_Receive_IT
 </UL>
-<BR>[Calls]<UL><LI><a href="#[112]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_IT
-<LI><a href="#[115]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr
+<BR>[Calls]<UL><LI><a href="#[11f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_IT
+<LI><a href="#[122]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr
 </UL>
 <BR>[Called By]<UL><LI><a href="#[8f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAReceiveCplt
 <LI><a href="#[8e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_8BIT
@@ -1519,22 +1587,22 @@ Global Symbols
 <LI><a href="#[92]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_RxISR_16BIT_FIFOEN
 </UL>
 
-<P><STRONG><a name="[120]"></a>HAL_UART_RxHalfCpltCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback))
+<P><STRONG><a name="[132]"></a>HAL_UART_RxHalfCpltCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UART_RxHalfCpltCallback
 </UL>
 <BR>[Called By]<UL><LI><a href="#[90]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMARxHalfCplt
 </UL>
 
-<P><STRONG><a name="[121]"></a>HAL_UART_TxCpltCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback))
+<P><STRONG><a name="[133]"></a>HAL_UART_TxCpltCallback</STRONG> (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = HAL_UART_TxCpltCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[103]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTransmit_IT
+<BR>[Called By]<UL><LI><a href="#[111]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTransmit_IT
 </UL>
 
-<P><STRONG><a name="[116]"></a>HCBle_InitDMAReception</STRONG> (Thumb, 44 bytes, Stack size 16 bytes, hcble.o(.text.HCBle_InitDMAReception))
+<P><STRONG><a name="[123]"></a>HCBle_InitDMAReception</STRONG> (Thumb, 44 bytes, Stack size 16 bytes, hcble.o(.text.HCBle_InitDMAReception))
 <BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = HCBle_InitDMAReception &rArr; HAL_UART_Receive_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[111]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_DMA
+<BR>[Calls]<UL><LI><a href="#[11e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_DMA
 </UL>
 <BR>[Called By]<UL><LI><a href="#[44]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;USART1_IRQHandler
 </UL>
@@ -1542,7 +1610,7 @@ Global Symbols
 <P><STRONG><a name="[2]"></a>HardFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.HardFault_Handler))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[117]"></a>MX_GPDMA1_Init</STRONG> (Thumb, 94 bytes, Stack size 32 bytes, gpdma.o(.text.MX_GPDMA1_Init))
+<P><STRONG><a name="[124]"></a>MX_GPDMA1_Init</STRONG> (Thumb, 94 bytes, Stack size 32 bytes, gpdma.o(.text.MX_GPDMA1_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 96<LI>Call Chain = MX_GPDMA1_Init &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_EnableIRQ
@@ -1551,43 +1619,72 @@ Global Symbols
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
 
-<P><STRONG><a name="[132]"></a>MX_GPIO_Init</STRONG> (Thumb, 96 bytes, Stack size 12 bytes, gpio.o(.text.MX_GPIO_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = MX_GPIO_Init
+<P><STRONG><a name="[125]"></a>MX_GPIO_Init</STRONG> (Thumb, 230 bytes, Stack size 72 bytes, gpio.o(.text.MX_GPIO_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 92<LI>Call Chain = MX_GPIO_Init &rArr; HAL_GPIO_Init
+</UL>
+<BR>[Calls]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_Init
+<LI><a href="#[126]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GPIO_WritePin
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
 
-<P><STRONG><a name="[118]"></a>MX_ThreadX_Init</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, app_threadx.o(.text.MX_ThreadX_Init))
+<P><STRONG><a name="[127]"></a>MX_TIM2_Init</STRONG> (Thumb, 198 bytes, Stack size 56 bytes, tim.o(.text.MX_TIM2_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 184<LI>Call Chain = MX_TIM2_Init &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+</UL>
+<BR>[Calls]<UL><LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_ConfigChannel
+<LI><a href="#[128]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIMEx_MasterConfigSynchronization
+<LI><a href="#[f4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_Init
+<LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ConfigClockSource
+<LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+</UL>
+<BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
+</UL>
+
+<P><STRONG><a name="[129]"></a>MX_ThreadX_Init</STRONG> (Thumb, 8 bytes, Stack size 8 bytes, app_threadx.o(.text.MX_ThreadX_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 272 + Unknown Stack Size
 <LI>Call Chain = MX_ThreadX_Init &rArr; _tx_initialize_kernel_enter &rArr; _tx_initialize_high_level &rArr; _tx_timer_initialize &rArr; _tx_thread_create &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
+<BR>[Calls]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
 
-<P><STRONG><a name="[11a]"></a>MX_USART1_UART_Init</STRONG> (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_USART1_UART_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 688 + Unknown Stack Size
+<P><STRONG><a name="[12b]"></a>MX_UART5_Init</STRONG> (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_UART5_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 704 + Unknown Stack Size
+<LI>Call Chain = MX_UART5_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
+</UL>
+<BR>[Calls]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_DisableFifoMode
+<LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
+<LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
+<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+</UL>
+<BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
+</UL>
+
+<P><STRONG><a name="[12d]"></a>MX_USART1_UART_Init</STRONG> (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_USART1_UART_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 704 + Unknown Stack Size
 <LI>Call Chain = MX_USART1_UART_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
-<BR>[Calls]<UL><LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_DisableFifoMode
-<LI><a href="#[f9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
-<LI><a href="#[fb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
-<LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
-<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+<BR>[Calls]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_DisableFifoMode
+<LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
+<LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
+<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
 
-<P><STRONG><a name="[11c]"></a>MX_USART2_UART_Init</STRONG> (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_USART2_UART_Init))
-<BR><BR>[Stack]<UL><LI>Max Depth = 688 + Unknown Stack Size
+<P><STRONG><a name="[12e]"></a>MX_USART2_UART_Init</STRONG> (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_USART2_UART_Init))
+<BR><BR>[Stack]<UL><LI>Max Depth = 704 + Unknown Stack Size
 <LI>Call Chain = MX_USART2_UART_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
-<BR>[Calls]<UL><LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_DisableFifoMode
-<LI><a href="#[f9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
-<LI><a href="#[fb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
-<LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
-<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+<BR>[Calls]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_DisableFifoMode
+<LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
+<LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
+<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
@@ -1598,14 +1695,14 @@ Global Symbols
 <P><STRONG><a name="[1]"></a>NMI_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.NMI_Handler))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[11d]"></a>SystemClock_Config</STRONG> (Thumb, 198 bytes, Stack size 120 bytes, main.o(.text.SystemClock_Config))
-<BR><BR>[Stack]<UL><LI>Max Depth = 280 + Unknown Stack Size
-<LI>Call Chain = SystemClock_Config &rArr; HAL_RCC_OscConfig &rArr; HAL_InitTick &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
+<P><STRONG><a name="[12f]"></a>SystemClock_Config</STRONG> (Thumb, 198 bytes, Stack size 120 bytes, main.o(.text.SystemClock_Config))
+<BR><BR>[Stack]<UL><LI>Max Depth = 344 + Unknown Stack Size
+<LI>Call Chain = SystemClock_Config &rArr; HAL_RCC_OscConfig &rArr; HAL_InitTick &rArr; HAL_TIM_Base_Init &rArr; HAL_TIM_Base_MspInit &rArr; HAL_NVIC_SetPriority &rArr; NVIC_EncodePriority
 </UL>
 <BR>[Calls]<UL><LI><a href="#[e3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_ClockConfig
-<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
+<LI><a href="#[11b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;Error_Handler
 <LI><a href="#[e4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCC_OscConfig
-<LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
+<LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;main
 </UL>
@@ -1616,167 +1713,194 @@ Global Symbols
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(.text)
 </UL>
 <P><STRONG><a name="[34]"></a>TIM1_UP_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.TIM1_UP_IRQHandler))
-<BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = TIM1_UP_IRQHandler &rArr; HAL_TIM_IRQHandler &rArr; HAL_TIM_PeriodElapsedCallback
+<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = TIM1_UP_IRQHandler &rArr; HAL_TIM_IRQHandler &rArr; HAL_TIM_IC_CaptureCallback &rArr; HAL_TIM_ReadCapturedValue
 </UL>
-<BR>[Calls]<UL><LI><a href="#[e7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+<BR>[Calls]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
+</UL>
+<BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
+</UL>
+<P><STRONG><a name="[37]"></a>TIM2_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.TIM2_IRQHandler))
+<BR><BR>[Stack]<UL><LI>Max Depth = 72<LI>Call Chain = TIM2_IRQHandler &rArr; HAL_TIM_IRQHandler &rArr; HAL_TIM_IC_CaptureCallback &rArr; HAL_TIM_ReadCapturedValue
+</UL>
+<BR>[Calls]<UL><LI><a href="#[f6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IRQHandler
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
 <P><STRONG><a name="[e6]"></a>TIM_Base_SetConfig</STRONG> (Thumb, 858 bytes, Stack size 12 bytes, stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig))
 <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = TIM_Base_SetConfig
 </UL>
-<BR>[Called By]<UL><LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
+<BR>[Called By]<UL><LI><a href="#[f4]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_Init
+<LI><a href="#[d0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_Base_Init
 </UL>
 
-<P><STRONG><a name="[108]"></a>UART_AdvFeatureConfig</STRONG> (Thumb, 328 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig))
+<P><STRONG><a name="[e9]"></a>TIM_ETR_SetConfig</STRONG> (Thumb, 52 bytes, Stack size 20 bytes, stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = TIM_ETR_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ConfigClockSource
+</UL>
+
+<P><STRONG><a name="[f0]"></a>TIM_TI1_SetConfig</STRONG> (Thumb, 440 bytes, Stack size 28 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = TIM_TI1_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_ConfigChannel
+</UL>
+
+<P><STRONG><a name="[48]"></a>UART5_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.UART5_IRQHandler))
+<BR><BR>[Stack]<UL><LI>Max Depth = 216<LI>Call Chain = UART5_IRQHandler &rArr; HAL_UART_IRQHandler &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
+</UL>
+<BR>[Calls]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+</UL>
+<BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
+</UL>
+<P><STRONG><a name="[116]"></a>UART_AdvFeatureConfig</STRONG> (Thumb, 328 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig))
 <BR><BR>[Stack]<UL><LI>Max Depth = 4<LI>Call Chain = UART_AdvFeatureConfig
 </UL>
-<BR>[Called By]<UL><LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
 </UL>
 
-<P><STRONG><a name="[10a]"></a>UART_CheckIdleState</STRONG> (Thumb, 326 bytes, Stack size 40 bytes, stm32h5xx_hal_uart.o(.text.UART_CheckIdleState))
+<P><STRONG><a name="[118]"></a>UART_CheckIdleState</STRONG> (Thumb, 326 bytes, Stack size 40 bytes, stm32h5xx_hal_uart.o(.text.UART_CheckIdleState))
 <BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = UART_CheckIdleState &rArr; UART_WaitOnFlagUntilTimeout &rArr; UART_EndRxTransfer
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
-<LI><a href="#[11e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
+<LI><a href="#[130]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
 </UL>
-<BR>[Called By]<UL><LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
 </UL>
 
-<P><STRONG><a name="[109]"></a>UART_SetConfig</STRONG> (Thumb, 1048 bytes, Stack size 48 bytes, stm32h5xx_hal_uart.o(.text.UART_SetConfig))
+<P><STRONG><a name="[117]"></a>UART_SetConfig</STRONG> (Thumb, 1048 bytes, Stack size 48 bytes, stm32h5xx_hal_uart.o(.text.UART_SetConfig))
 <BR><BR>[Stack]<UL><LI>Max Depth = 220<LI>Call Chain = UART_SetConfig &rArr; HAL_RCCEx_GetPeriphCLKFreq &rArr; HAL_RCC_GetPCLK3Freq &rArr; HAL_RCC_GetHCLKFreq &rArr; HAL_RCC_GetSysClockFreq
 </UL>
 <BR>[Calls]<UL><LI><a href="#[d9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_GetPeriphCLKFreq
-<LI><a href="#[122]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
+<LI><a href="#[134]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_uldivmod
 </UL>
-<BR>[Called By]<UL><LI><a href="#[106]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
+<BR>[Called By]<UL><LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Init
 </UL>
 
-<P><STRONG><a name="[f6]"></a>UART_Start_Receive_DMA</STRONG> (Thumb, 472 bytes, Stack size 40 bytes, stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA))
+<P><STRONG><a name="[104]"></a>UART_Start_Receive_DMA</STRONG> (Thumb, 472 bytes, Stack size 40 bytes, stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA))
 <BR><BR>[Stack]<UL><LI>Max Depth = 88<LI>Call Chain = UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
 <BR>[Calls]<UL><LI><a href="#[c6]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMA_Start_IT
 <LI><a href="#[c2]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_Start_IT
 </UL>
-<BR>[Called By]<UL><LI><a href="#[f5]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_ReceiveToIdle_DMA
-<LI><a href="#[111]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_DMA
+<BR>[Called By]<UL><LI><a href="#[103]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_ReceiveToIdle_DMA
+<LI><a href="#[11e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_DMA
 </UL>
 
-<P><STRONG><a name="[113]"></a>UART_Start_Receive_IT</STRONG> (Thumb, 546 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT))
+<P><STRONG><a name="[120]"></a>UART_Start_Receive_IT</STRONG> (Thumb, 546 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT))
 <BR><BR>[Stack]<UL><LI>Max Depth = 32<LI>Call Chain = UART_Start_Receive_IT
 </UL>
-<BR>[Called By]<UL><LI><a href="#[112]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_IT
+<BR>[Called By]<UL><LI><a href="#[11f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_Receive_IT
 </UL>
 
-<P><STRONG><a name="[11e]"></a>UART_WaitOnFlagUntilTimeout</STRONG> (Thumb, 268 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout))
+<P><STRONG><a name="[130]"></a>UART_WaitOnFlagUntilTimeout</STRONG> (Thumb, 268 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout))
 <BR><BR>[Stack]<UL><LI>Max Depth = 48<LI>Call Chain = UART_WaitOnFlagUntilTimeout &rArr; UART_EndRxTransfer
 </UL>
 <BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
-<LI><a href="#[ff]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
+<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
 </UL>
-<BR>[Called By]<UL><LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
+<BR>[Called By]<UL><LI><a href="#[118]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_CheckIdleState
 </UL>
 
 <P><STRONG><a name="[44]"></a>USART1_IRQHandler</STRONG> (Thumb, 160 bytes, Stack size 16 bytes, stm32h5xx_it.o(.text.USART1_IRQHandler))
 <BR><BR>[Stack]<UL><LI>Max Depth = 224<LI>Call Chain = USART1_IRQHandler &rArr; HAL_UART_IRQHandler &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[116]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HCBle_InitDMAReception
-<LI><a href="#[fc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
-<LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Calls]<UL><LI><a href="#[123]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HCBle_InitDMAReception
+<LI><a href="#[10a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_AbortReceive
+<LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
 <P><STRONG><a name="[45]"></a>USART2_IRQHandler</STRONG> (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.USART2_IRQHandler))
 <BR><BR>[Stack]<UL><LI>Max Depth = 216<LI>Call Chain = USART2_IRQHandler &rArr; HAL_UART_IRQHandler &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Calls]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
 <P><STRONG><a name="[5]"></a>UsageFault_Handler</STRONG> (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.UsageFault_Handler))
 <BR>[Address Reference Count : 1]<UL><LI> startup_stm32h563xx.o(RESET)
 </UL>
-<P><STRONG><a name="[123]"></a>_tx_byte_pool_create</STRONG> (Thumb, 304 bytes, Stack size 64 bytes, tx_byte_pool_create.o(.text._tx_byte_pool_create))
+<P><STRONG><a name="[135]"></a>_tx_byte_pool_create</STRONG> (Thumb, 304 bytes, Stack size 64 bytes, tx_byte_pool_create.o(.text._tx_byte_pool_create))
 <BR><BR>[Stack]<UL><LI>Max Depth = 64 + Unknown Stack Size
 <LI>Call Chain = _tx_byte_pool_create
 </UL>
-<BR>[Calls]<UL><LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
+<BR>[Calls]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
-<BR>[Called By]<UL><LI><a href="#[131]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
+<BR>[Called By]<UL><LI><a href="#[143]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
 </UL>
 
-<P><STRONG><a name="[124]"></a>_tx_initialize_high_level</STRONG> (Thumb, 134 bytes, Stack size 8 bytes, tx_initialize_high_level.o(.text._tx_initialize_high_level))
+<P><STRONG><a name="[136]"></a>_tx_initialize_high_level</STRONG> (Thumb, 134 bytes, Stack size 8 bytes, tx_initialize_high_level.o(.text._tx_initialize_high_level))
 <BR><BR>[Stack]<UL><LI>Max Depth = 248 + Unknown Stack Size
 <LI>Call Chain = _tx_initialize_high_level &rArr; _tx_timer_initialize &rArr; _tx_thread_create &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[126]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
-<LI><a href="#[125]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_initialize
+<BR>[Calls]<UL><LI><a href="#[138]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
+<LI><a href="#[137]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_initialize
 </UL>
-<BR>[Called By]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
+<BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
 </UL>
 
-<P><STRONG><a name="[119]"></a>_tx_initialize_kernel_enter</STRONG> (Thumb, 104 bytes, Stack size 16 bytes, tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter))
+<P><STRONG><a name="[12a]"></a>_tx_initialize_kernel_enter</STRONG> (Thumb, 104 bytes, Stack size 16 bytes, tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter))
 <BR><BR>[Stack]<UL><LI>Max Depth = 264 + Unknown Stack Size
 <LI>Call Chain = _tx_initialize_kernel_enter &rArr; _tx_initialize_high_level &rArr; _tx_timer_initialize &rArr; _tx_thread_create &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[128]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
-<LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_low_level
-<LI><a href="#[129]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_schedule
-<LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
+<BR>[Calls]<UL><LI><a href="#[13a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
+<LI><a href="#[139]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_low_level
+<LI><a href="#[13b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_schedule
+<LI><a href="#[136]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
 </UL>
-<BR>[Called By]<UL><LI><a href="#[118]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_ThreadX_Init
+<BR>[Called By]<UL><LI><a href="#[129]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_ThreadX_Init
 </UL>
 
-<P><STRONG><a name="[12a]"></a>_tx_thread_create</STRONG> (Thumb, 538 bytes, Stack size 80 bytes, tx_thread_create.o(.text._tx_thread_create))
+<P><STRONG><a name="[13c]"></a>_tx_thread_create</STRONG> (Thumb, 538 bytes, Stack size 80 bytes, tx_thread_create.o(.text._tx_thread_create))
 <BR><BR>[Stack]<UL><LI>Max Depth = 192 + Unknown Stack Size
 <LI>Call Chain = _tx_thread_create &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_preempt_check
-<LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
-<LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_stack_build
+<BR>[Calls]<UL><LI><a href="#[13f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_preempt_check
+<LI><a href="#[13e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
+<LI><a href="#[13d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_stack_build
+<LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 <LI><a href="#[b0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memset
-<LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
-<BR>[Called By]<UL><LI><a href="#[126]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
+<BR>[Called By]<UL><LI><a href="#[138]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_initialize
 </UL>
 
-<P><STRONG><a name="[125]"></a>_tx_thread_initialize</STRONG> (Thumb, 126 bytes, Stack size 16 bytes, tx_thread_initialize.o(.text._tx_thread_initialize))
+<P><STRONG><a name="[137]"></a>_tx_thread_initialize</STRONG> (Thumb, 126 bytes, Stack size 16 bytes, tx_thread_initialize.o(.text._tx_thread_initialize))
 <BR><BR>[Stack]<UL><LI>Max Depth = 16 + Unknown Stack Size
 <LI>Call Chain = _tx_thread_initialize
 </UL>
-<BR>[Calls]<UL><LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
+<BR>[Calls]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
-<BR>[Called By]<UL><LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
+<BR>[Called By]<UL><LI><a href="#[136]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
 </UL>
 
 <P><STRONG><a name="[95]"></a>_tx_thread_shell_entry</STRONG> (Thumb, 148 bytes, Stack size 40 bytes, tx_thread_shell_entry.o(.text._tx_thread_shell_entry))
 <BR><BR>[Stack]<UL><LI>Max Depth = 188<LI>Call Chain = _tx_thread_shell_entry &rArr; _tx_thread_system_suspend &rArr; _tx_timer_system_activate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
+<BR>[Calls]<UL><LI><a href="#[140]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> tx_thread_create.o(.text._tx_thread_create)
 </UL>
-<P><STRONG><a name="[12d]"></a>_tx_thread_system_preempt_check</STRONG> (Thumb, 112 bytes, Stack size 28 bytes, tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check))
+<P><STRONG><a name="[13f]"></a>_tx_thread_system_preempt_check</STRONG> (Thumb, 112 bytes, Stack size 28 bytes, tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check))
 <BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = _tx_thread_system_preempt_check
 </UL>
-<BR>[Called By]<UL><LI><a href="#[131]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
-<LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<BR>[Called By]<UL><LI><a href="#[143]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
+<LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
 </UL>
 
-<P><STRONG><a name="[12c]"></a>_tx_thread_system_resume</STRONG> (Thumb, 584 bytes, Stack size 96 bytes, tx_thread_system_resume.o(.text._tx_thread_system_resume))
+<P><STRONG><a name="[13e]"></a>_tx_thread_system_resume</STRONG> (Thumb, 584 bytes, Stack size 96 bytes, tx_thread_system_resume.o(.text._tx_thread_system_resume))
 <BR><BR>[Stack]<UL><LI>Max Depth = 112<LI>Call Chain = _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_deactivate
+<BR>[Calls]<UL><LI><a href="#[141]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_deactivate
 </UL>
 <BR>[Called By]<UL><LI><a href="#[ac]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_expiration_process
 <LI><a href="#[94]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_timeout
-<LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
 </UL>
 
-<P><STRONG><a name="[12e]"></a>_tx_thread_system_suspend</STRONG> (Thumb, 640 bytes, Stack size 120 bytes, tx_thread_system_suspend.o(.text._tx_thread_system_suspend))
+<P><STRONG><a name="[140]"></a>_tx_thread_system_suspend</STRONG> (Thumb, 640 bytes, Stack size 120 bytes, tx_thread_system_suspend.o(.text._tx_thread_system_suspend))
 <BR><BR>[Stack]<UL><LI>Max Depth = 148<LI>Call Chain = _tx_thread_system_suspend &rArr; _tx_timer_system_activate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[130]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_activate
+<BR>[Calls]<UL><LI><a href="#[142]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_activate
 </UL>
 <BR>[Called By]<UL><LI><a href="#[96]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_thread_entry
 <LI><a href="#[95]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_shell_entry
@@ -1791,95 +1915,133 @@ Global Symbols
 <P><STRONG><a name="[94]"></a>_tx_thread_timeout</STRONG> (Thumb, 114 bytes, Stack size 48 bytes, tx_thread_timeout.o(.text._tx_thread_timeout))
 <BR><BR>[Stack]<UL><LI>Max Depth = 160<LI>Call Chain = _tx_thread_timeout &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
+<BR>[Calls]<UL><LI><a href="#[13e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> tx_thread_create.o(.text._tx_thread_create)
 </UL>
 <P><STRONG><a name="[ac]"></a>_tx_timer_expiration_process</STRONG> (Thumb, 60 bytes, Stack size 24 bytes, tx_timer_expiration_process.o(.text._tx_timer_expiration_process))
 <BR><BR>[Stack]<UL><LI>Max Depth = 136<LI>Call Chain = _tx_timer_expiration_process &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
+<BR>[Calls]<UL><LI><a href="#[13e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_interrupt
 </UL>
 
-<P><STRONG><a name="[126]"></a>_tx_timer_initialize</STRONG> (Thumb, 286 bytes, Stack size 48 bytes, tx_timer_initialize.o(.text._tx_timer_initialize))
+<P><STRONG><a name="[138]"></a>_tx_timer_initialize</STRONG> (Thumb, 286 bytes, Stack size 48 bytes, tx_timer_initialize.o(.text._tx_timer_initialize))
 <BR><BR>[Stack]<UL><LI>Max Depth = 240 + Unknown Stack Size
 <LI>Call Chain = _tx_timer_initialize &rArr; _tx_thread_create &rArr; _tx_thread_system_resume &rArr; _tx_timer_system_deactivate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
-<LI><a href="#[10b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
+<BR>[Calls]<UL><LI><a href="#[13c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_create
+<LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__aeabi_memclr4
 </UL>
-<BR>[Called By]<UL><LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
+<BR>[Called By]<UL><LI><a href="#[136]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_high_level
 </UL>
 
-<P><STRONG><a name="[130]"></a>_tx_timer_system_activate</STRONG> (Thumb, 212 bytes, Stack size 28 bytes, tx_timer_system_activate.o(.text._tx_timer_system_activate))
+<P><STRONG><a name="[142]"></a>_tx_timer_system_activate</STRONG> (Thumb, 212 bytes, Stack size 28 bytes, tx_timer_system_activate.o(.text._tx_timer_system_activate))
 <BR><BR>[Stack]<UL><LI>Max Depth = 28<LI>Call Chain = _tx_timer_system_activate
 </UL>
-<BR>[Called By]<UL><LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
+<BR>[Called By]<UL><LI><a href="#[140]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
 <LI><a href="#[96]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_thread_entry
 </UL>
 
-<P><STRONG><a name="[12f]"></a>_tx_timer_system_deactivate</STRONG> (Thumb, 112 bytes, Stack size 16 bytes, tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate))
+<P><STRONG><a name="[141]"></a>_tx_timer_system_deactivate</STRONG> (Thumb, 112 bytes, Stack size 16 bytes, tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate))
 <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = _tx_timer_system_deactivate
 </UL>
-<BR>[Called By]<UL><LI><a href="#[12c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
+<BR>[Called By]<UL><LI><a href="#[13e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_resume
 </UL>
 
 <P><STRONG><a name="[96]"></a>_tx_timer_thread_entry</STRONG> (Thumb, 536 bytes, Stack size 104 bytes, tx_timer_thread_entry.o(.text._tx_timer_thread_entry))
 <BR><BR>[Stack]<UL><LI>Max Depth = 252<LI>Call Chain = _tx_timer_thread_entry &rArr; _tx_thread_system_suspend &rArr; _tx_timer_system_activate
 </UL>
-<BR>[Calls]<UL><LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
-<LI><a href="#[130]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_activate
+<BR>[Calls]<UL><LI><a href="#[140]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_suspend
+<LI><a href="#[142]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_timer_system_activate
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> tx_timer_initialize.o(.text._tx_timer_initialize)
 </UL>
-<P><STRONG><a name="[131]"></a>_txe_byte_pool_create</STRONG> (Thumb, 372 bytes, Stack size 80 bytes, txe_byte_pool_create.o(.text._txe_byte_pool_create))
+<P><STRONG><a name="[143]"></a>_txe_byte_pool_create</STRONG> (Thumb, 372 bytes, Stack size 80 bytes, txe_byte_pool_create.o(.text._txe_byte_pool_create))
 <BR><BR>[Stack]<UL><LI>Max Depth = 144 + Unknown Stack Size
 <LI>Call Chain = _txe_byte_pool_create &rArr; _tx_byte_pool_create
 </UL>
-<BR>[Calls]<UL><LI><a href="#[123]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_byte_pool_create
-<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_preempt_check
+<BR>[Calls]<UL><LI><a href="#[135]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_byte_pool_create
+<LI><a href="#[13f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_thread_system_preempt_check
 </UL>
-<BR>[Called By]<UL><LI><a href="#[128]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
+<BR>[Called By]<UL><LI><a href="#[13a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;tx_application_define
 </UL>
 
-<P><STRONG><a name="[a2]"></a>main</STRONG> (Thumb, 40 bytes, Stack size 16 bytes, main.o(.text.main))
-<BR><BR>[Stack]<UL><LI>Max Depth = 704 + Unknown Stack Size
-<LI>Call Chain = main &rArr; MX_USART2_UART_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
+<P><STRONG><a name="[a2]"></a>main</STRONG> (Thumb, 48 bytes, Stack size 16 bytes, main.o(.text.main))
+<BR><BR>[Stack]<UL><LI>Max Depth = 720 + Unknown Stack Size
+<LI>Call Chain = main &rArr; MX_UART5_Init &rArr; HAL_UART_Init &rArr; HAL_UART_MspInit &rArr; HAL_RCCEx_PeriphCLKConfig &rArr; RCCEx_PLL3_Config
 </UL>
-<BR>[Calls]<UL><LI><a href="#[118]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_ThreadX_Init
-<LI><a href="#[11c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
-<LI><a href="#[11a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
-<LI><a href="#[117]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
-<LI><a href="#[132]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
-<LI><a href="#[11d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
+<BR>[Calls]<UL><LI><a href="#[129]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_ThreadX_Init
+<LI><a href="#[12b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_UART5_Init
+<LI><a href="#[127]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_TIM2_Init
+<LI><a href="#[12e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART2_UART_Init
+<LI><a href="#[12d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_USART1_UART_Init
+<LI><a href="#[124]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPDMA1_Init
+<LI><a href="#[125]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;MX_GPIO_Init
+<LI><a href="#[12f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;SystemClock_Config
 <LI><a href="#[c8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_Init
 </UL>
 <BR>[Called By]<UL><LI><a href="#[a1]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_entry_main
 </UL>
 
-<P><STRONG><a name="[128]"></a>tx_application_define</STRONG> (Thumb, 88 bytes, Stack size 24 bytes, app_azure_rtos.o(.text.tx_application_define))
+<P><STRONG><a name="[13a]"></a>tx_application_define</STRONG> (Thumb, 88 bytes, Stack size 24 bytes, app_azure_rtos.o(.text.tx_application_define))
 <BR><BR>[Stack]<UL><LI>Max Depth = 168 + Unknown Stack Size
 <LI>Call Chain = tx_application_define &rArr; _txe_byte_pool_create &rArr; _tx_byte_pool_create
 </UL>
-<BR>[Calls]<UL><LI><a href="#[131]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
-<LI><a href="#[133]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;App_ThreadX_Init
+<BR>[Calls]<UL><LI><a href="#[143]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_txe_byte_pool_create
+<LI><a href="#[144]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;App_ThreadX_Init
 </UL>
-<BR>[Called By]<UL><LI><a href="#[119]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
+<BR>[Called By]<UL><LI><a href="#[12a]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;_tx_initialize_kernel_enter
 </UL>
 
 <P><STRONG><a name="[9c]"></a>_fp_init</STRONG> (Thumb, 26 bytes, Stack size 0 bytes, fpinit.o(x$fpl$fpinit))
 <BR><BR>[Called By]<UL><LI><a href="#[9b]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;__rt_lib_init_fp_1
 </UL>
 
-<P><STRONG><a name="[169]"></a>__fplib_config_fpu_vfp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
+<P><STRONG><a name="[17a]"></a>__fplib_config_fpu_vfp</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
 
-<P><STRONG><a name="[16a]"></a>__fplib_config_pureend_doubles</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
+<P><STRONG><a name="[17b]"></a>__fplib_config_pureend_doubles</STRONG> (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED)
 <P>
 <H3>
 Local Symbols
 </H3>
+<P><STRONG><a name="[f1]"></a>TIM_TI2_SetConfig</STRONG> (Thumb, 108 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = TIM_TI2_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_ConfigChannel
+</UL>
+
+<P><STRONG><a name="[f2]"></a>TIM_TI3_SetConfig</STRONG> (Thumb, 106 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = TIM_TI3_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_ConfigChannel
+</UL>
+
+<P><STRONG><a name="[f3]"></a>TIM_TI4_SetConfig</STRONG> (Thumb, 108 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = TIM_TI4_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[ef]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_IC_ConfigChannel
+</UL>
+
+<P><STRONG><a name="[ea]"></a>TIM_TI1_ConfigInputStage</STRONG> (Thumb, 80 bytes, Stack size 20 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage))
+<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = TIM_TI1_ConfigInputStage
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ConfigClockSource
+</UL>
+
+<P><STRONG><a name="[eb]"></a>TIM_ITRx_SetConfig</STRONG> (Thumb, 48 bytes, Stack size 12 bytes, stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig))
+<BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = TIM_ITRx_SetConfig
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ConfigClockSource
+</UL>
+
+<P><STRONG><a name="[ec]"></a>TIM_TI2_ConfigInputStage</STRONG> (Thumb, 82 bytes, Stack size 20 bytes, stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage))
+<BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = TIM_TI2_ConfigInputStage
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e8]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_TIM_ConfigClockSource
+</UL>
+
 <P><STRONG><a name="[d8]"></a>__NVIC_SetPriorityGrouping</STRONG> (Thumb, 60 bytes, Stack size 12 bytes, stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping))
 <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = __NVIC_SetPriorityGrouping
 </UL>
@@ -1908,6 +2070,22 @@ Local Symbols
 <BR>[Called By]<UL><LI><a href="#[d3]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_NVIC_EnableIRQ
 </UL>
 
+<P><STRONG><a name="[e1]"></a>RCCEx_PLL2_Config</STRONG> (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config))
+<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = RCCEx_PLL2_Config
+</UL>
+<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
+</UL>
+
+<P><STRONG><a name="[e2]"></a>RCCEx_PLL3_Config</STRONG> (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config))
+<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = RCCEx_PLL3_Config
+</UL>
+<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
+</UL>
+<BR>[Called By]<UL><LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
+</UL>
+
 <P><STRONG><a name="[c5]"></a>DMA_Init</STRONG> (Thumb, 1930 bytes, Stack size 20 bytes, stm32h5xx_hal_dma.o(.text.DMA_Init))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = DMA_Init
 </UL>
@@ -1959,27 +2137,11 @@ Local Symbols
 <LI><a href="#[bc]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_DMAEx_List_InsertNode
 </UL>
 
-<P><STRONG><a name="[e1]"></a>RCCEx_PLL2_Config</STRONG> (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config))
-<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = RCCEx_PLL2_Config
-</UL>
-<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
-</UL>
-<BR>[Called By]<UL><LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
-</UL>
-
-<P><STRONG><a name="[e2]"></a>RCCEx_PLL3_Config</STRONG> (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config))
-<BR><BR>[Stack]<UL><LI>Max Depth = 24<LI>Call Chain = RCCEx_PLL3_Config
-</UL>
-<BR>[Calls]<UL><LI><a href="#[ba]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_GetTick
-</UL>
-<BR>[Called By]<UL><LI><a href="#[e0]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_RCCEx_PeriphCLKConfig
-</UL>
-
-<P><STRONG><a name="[ff]"></a>UART_EndRxTransfer</STRONG> (Thumb, 158 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer))
+<P><STRONG><a name="[10d]"></a>UART_EndRxTransfer</STRONG> (Thumb, 158 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer))
 <BR><BR>[Stack]<UL><LI>Max Depth = 16<LI>Call Chain = UART_EndRxTransfer
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
-<LI><a href="#[11e]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<LI><a href="#[130]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_WaitOnFlagUntilTimeout
 <LI><a href="#[91]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAError
 </UL>
 
@@ -1987,9 +2149,9 @@ Local Symbols
 <BR><BR>[Stack]<UL><LI>Max Depth = 208 + Unknown Stack Size
 <LI>Call Chain = UART_RxISR_16BIT_FIFOEN &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
-<LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
-<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
+<LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
 </UL>
@@ -1997,9 +2159,9 @@ Local Symbols
 <BR><BR>[Stack]<UL><LI>Max Depth = 208 + Unknown Stack Size
 <LI>Call Chain = UART_RxISR_8BIT_FIFOEN &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
-<LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
-<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
+<LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
 </UL>
@@ -2007,8 +2169,8 @@ Local Symbols
 <BR><BR>[Stack]<UL><LI>Max Depth = 184 + Unknown Stack Size
 <LI>Call Chain = UART_RxISR_16BIT &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
-<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 <BR>[Address Reference Count : 2]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
 <LI> stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN)
@@ -2017,8 +2179,8 @@ Local Symbols
 <BR><BR>[Stack]<UL><LI>Max Depth = 176 + Unknown Stack Size
 <LI>Call Chain = UART_RxISR_8BIT &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
-<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 <BR>[Address Reference Count : 2]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
 <LI> stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN)
@@ -2026,13 +2188,13 @@ Local Symbols
 <P><STRONG><a name="[91]"></a>UART_DMAError</STRONG> (Thumb, 128 bytes, Stack size 24 bytes, stm32h5xx_hal_uart.o(.text.UART_DMAError))
 <BR><BR>[Stack]<UL><LI>Max Depth = 40<LI>Call Chain = UART_DMAError &rArr; UART_EndRxTransfer
 </UL>
-<BR>[Calls]<UL><LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
-<LI><a href="#[11f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTxTransfer
-<LI><a href="#[ff]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
+<BR>[Calls]<UL><LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
+<LI><a href="#[131]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndTxTransfer
+<LI><a href="#[10d]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_EndRxTransfer
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
 </UL>
-<P><STRONG><a name="[11f]"></a>UART_EndTxTransfer</STRONG> (Thumb, 92 bytes, Stack size 12 bytes, stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer))
+<P><STRONG><a name="[131]"></a>UART_EndTxTransfer</STRONG> (Thumb, 92 bytes, Stack size 12 bytes, stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer))
 <BR><BR>[Stack]<UL><LI>Max Depth = 12<LI>Call Chain = UART_EndTxTransfer
 </UL>
 <BR>[Called By]<UL><LI><a href="#[91]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;UART_DMAError
@@ -2042,39 +2204,39 @@ Local Symbols
 <BR><BR>[Stack]<UL><LI>Max Depth = 176 + Unknown Stack Size
 <LI>Call Chain = UART_DMAReceiveCplt &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
-<LI><a href="#[114]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxCpltCallback
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
 </UL>
 <P><STRONG><a name="[90]"></a>UART_DMARxHalfCplt</STRONG> (Thumb, 110 bytes, Stack size 24 bytes, stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt))
 <BR><BR>[Stack]<UL><LI>Max Depth = 168<LI>Call Chain = UART_DMARxHalfCplt &rArr; HAL_UARTEx_RxEventCallback &rArr; HAL_UARTEx_ReceiveToIdle_DMA &rArr; UART_Start_Receive_DMA &rArr; HAL_DMA_Start_IT &rArr; DMA_SetConfig
 </UL>
-<BR>[Calls]<UL><LI><a href="#[120]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxHalfCpltCallback
-<LI><a href="#[f7]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
+<BR>[Calls]<UL><LI><a href="#[132]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_RxHalfCpltCallback
+<LI><a href="#[105]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_RxEventCallback
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
 </UL>
 <P><STRONG><a name="[8c]"></a>UART_DMAAbortOnError</STRONG> (Thumb, 30 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = UART_DMAAbortOnError &rArr; HAL_UART_ErrorCallback
 </UL>
-<BR>[Calls]<UL><LI><a href="#[101]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
+<BR>[Calls]<UL><LI><a href="#[10f]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_ErrorCallback
 </UL>
 <BR>[Address Reference Count : 1]<UL><LI> stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler)
 </UL>
-<P><STRONG><a name="[103]"></a>UART_EndTransmit_IT</STRONG> (Thumb, 68 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT))
+<P><STRONG><a name="[111]"></a>UART_EndTransmit_IT</STRONG> (Thumb, 68 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT))
 <BR><BR>[Stack]<UL><LI>Max Depth = 20<LI>Call Chain = UART_EndTransmit_IT &rArr; HAL_UART_TxCpltCallback
 </UL>
-<BR>[Calls]<UL><LI><a href="#[121]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_TxCpltCallback
+<BR>[Calls]<UL><LI><a href="#[133]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_TxCpltCallback
 </UL>
-<BR>[Called By]<UL><LI><a href="#[fe]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
+<BR>[Called By]<UL><LI><a href="#[10c]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UART_IRQHandler
 </UL>
 
-<P><STRONG><a name="[fa]"></a>UARTEx_SetNbDataToProcess</STRONG> (Thumb, 138 bytes, Stack size 8 bytes, stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess))
+<P><STRONG><a name="[108]"></a>UARTEx_SetNbDataToProcess</STRONG> (Thumb, 138 bytes, Stack size 8 bytes, stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess))
 <BR><BR>[Stack]<UL><LI>Max Depth = 8<LI>Call Chain = UARTEx_SetNbDataToProcess
 </UL>
-<BR>[Called By]<UL><LI><a href="#[f9]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
-<LI><a href="#[fb]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
+<BR>[Called By]<UL><LI><a href="#[107]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetRxFifoThreshold
+<LI><a href="#[109]">&gt;&gt;</a>&nbsp;&nbsp;&nbsp;HAL_UARTEx_SetTxFifoThreshold
 </UL>
 <P>
 <H3>
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp b/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp
index a412840..494cc35 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp
@@ -6,6 +6,7 @@
 "autoguidestick\gpdma.o"
 "autoguidestick\memorymap.o"
 "autoguidestick\app_threadx.o"
+"autoguidestick\tim.o"
 "autoguidestick\usart.o"
 "autoguidestick\stm32h5xx_it.o"
 "autoguidestick\stm32h5xx_hal_msp.o"
@@ -14,13 +15,13 @@
 "autoguidestick\stm32h5xx_hal_tim.o"
 "autoguidestick\stm32h5xx_hal_tim_ex.o"
 "autoguidestick\stm32h5xx_hal_cortex.o"
-"autoguidestick\stm32h5xx_hal_dma.o"
-"autoguidestick\stm32h5xx_hal_dma_ex.o"
 "autoguidestick\stm32h5xx_hal_rcc.o"
 "autoguidestick\stm32h5xx_hal_rcc_ex.o"
 "autoguidestick\stm32h5xx_hal_flash.o"
 "autoguidestick\stm32h5xx_hal_flash_ex.o"
 "autoguidestick\stm32h5xx_hal_gpio.o"
+"autoguidestick\stm32h5xx_hal_dma.o"
+"autoguidestick\stm32h5xx_hal_dma_ex.o"
 "autoguidestick\stm32h5xx_hal_pwr.o"
 "autoguidestick\stm32h5xx_hal_pwr_ex.o"
 "autoguidestick\stm32h5xx_hal.o"
@@ -195,6 +196,9 @@
 "autoguidestick\txe_timer_info_get.o"
 "autoguidestick\hcble.o"
 "autoguidestick\gps.o"
+"autoguidestick\buzzer.o"
+"autoguidestick\shake_motor.o"
+"autoguidestick\ultrasound.o"
 --strict --scatter "AutoGuideStick\AutoGuideStick.sct"
 --summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols
 --info sizes --info totals --info unused --info veneers
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.map b/MDK-ARM/AutoGuideStick/AutoGuideStick.map
index a34672f..5b0cd07 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick.map
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.map
@@ -21,8 +21,10 @@ Section Cross References
     startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.GPDMA1_Channel4_IRQHandler) for GPDMA1_Channel4_IRQHandler
     startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.GPDMA1_Channel5_IRQHandler) for GPDMA1_Channel5_IRQHandler
     startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler
+    startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.TIM2_IRQHandler) for TIM2_IRQHandler
     startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.USART1_IRQHandler) for USART1_IRQHandler
     startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.USART2_IRQHandler) for USART2_IRQHandler
+    startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.UART5_IRQHandler) for UART5_IRQHandler
     startup_stm32h563xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory
     startup_stm32h563xx.o(.text) refers to system_stm32h5xx.o(.text.SystemInit) for SystemInit
     startup_stm32h563xx.o(.text) refers to __main.o(!!!main) for __main
@@ -34,6 +36,8 @@ Section Cross References
     main.o(.text.main) refers to gpdma.o(.text.MX_GPDMA1_Init) for MX_GPDMA1_Init
     main.o(.text.main) refers to usart.o(.text.MX_USART1_UART_Init) for MX_USART1_UART_Init
     main.o(.text.main) refers to usart.o(.text.MX_USART2_UART_Init) for MX_USART2_UART_Init
+    main.o(.text.main) refers to tim.o(.text.MX_TIM2_Init) for MX_TIM2_Init
+    main.o(.text.main) refers to usart.o(.text.MX_UART5_Init) for MX_UART5_Init
     main.o(.text.main) refers to app_threadx.o(.text.MX_ThreadX_Init) for MX_ThreadX_Init
     main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol]
     main.o(.text.SystemClock_Config) refers to rt_memclr_w.o(.text) for __aeabi_memclr4
@@ -47,6 +51,8 @@ Section Cross References
     tx_initialize_low_level.o(.text) refers to tx_timer_interrupt.o(.text) for _tx_timer_interrupt
     tx_initialize_low_level.o(.text) refers to startup_stm32h563xx.o(RESET) for __Vectors
     tx_initialize_low_level.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_system_stack_ptr) for _tx_thread_system_stack_ptr
+    gpio.o(.text.MX_GPIO_Init) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    gpio.o(.text.MX_GPIO_Init) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init
     gpio.o(.ARM.exidx.text.MX_GPIO_Init) refers to gpio.o(.text.MX_GPIO_Init) for [Anonymous Symbol]
     gpdma.o(.text.MX_GPDMA1_Init) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority
     gpdma.o(.text.MX_GPDMA1_Init) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ
@@ -54,6 +60,28 @@ Section Cross References
     app_threadx.o(.ARM.exidx.text.App_ThreadX_Init) refers to app_threadx.o(.text.App_ThreadX_Init) for [Anonymous Symbol]
     app_threadx.o(.text.MX_ThreadX_Init) refers to tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) for _tx_initialize_kernel_enter
     app_threadx.o(.ARM.exidx.text.MX_ThreadX_Init) refers to app_threadx.o(.text.MX_ThreadX_Init) for [Anonymous Symbol]
+    tim.o(.text.MX_TIM2_Init) refers to tim.o(.bss.htim2) for htim2
+    tim.o(.text.MX_TIM2_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) for HAL_TIM_Base_Init
+    tim.o(.text.MX_TIM2_Init) refers to main.o(.text.Error_Handler) for Error_Handler
+    tim.o(.text.MX_TIM2_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) for HAL_TIM_ConfigClockSource
+    tim.o(.text.MX_TIM2_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init) for HAL_TIM_IC_Init
+    tim.o(.text.MX_TIM2_Init) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization) for HAL_TIMEx_MasterConfigSynchronization
+    tim.o(.text.MX_TIM2_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) for HAL_TIM_IC_ConfigChannel
+    tim.o(.ARM.exidx.text.MX_TIM2_Init) refers to tim.o(.text.MX_TIM2_Init) for [Anonymous Symbol]
+    tim.o(.text.HAL_TIM_Base_MspInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init
+    tim.o(.text.HAL_TIM_Base_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority
+    tim.o(.text.HAL_TIM_Base_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ
+    tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol]
+    tim.o(.text.HAL_TIM_Base_MspDeInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit
+    tim.o(.text.HAL_TIM_Base_MspDeInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ
+    tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol]
+    usart.o(.text.MX_UART5_Init) refers to usart.o(.bss.huart5) for huart5
+    usart.o(.text.MX_UART5_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init
+    usart.o(.text.MX_UART5_Init) refers to main.o(.text.Error_Handler) for Error_Handler
+    usart.o(.text.MX_UART5_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold) for HAL_UARTEx_SetTxFifoThreshold
+    usart.o(.text.MX_UART5_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold) for HAL_UARTEx_SetRxFifoThreshold
+    usart.o(.text.MX_UART5_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode) for HAL_UARTEx_DisableFifoMode
+    usart.o(.ARM.exidx.text.MX_UART5_Init) refers to usart.o(.text.MX_UART5_Init) for [Anonymous Symbol]
     usart.o(.text.MX_USART1_UART_Init) refers to usart.o(.bss.huart1) for huart1
     usart.o(.text.MX_USART1_UART_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init
     usart.o(.text.MX_USART1_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler
@@ -72,6 +100,8 @@ Section Cross References
     usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for HAL_RCCEx_PeriphCLKConfig
     usart.o(.text.HAL_UART_MspInit) refers to main.o(.text.Error_Handler) for Error_Handler
     usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init
+    usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority
+    usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.Node_GPDMA1_Channel5) for Node_GPDMA1_Channel5
     usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) for HAL_DMAEx_List_BuildNode
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.List_GPDMA1_Channel5) for List_GPDMA1_Channel5
@@ -83,15 +113,13 @@ Section Cross References
     usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes) for HAL_DMA_ConfigChannelAttributes
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.handle_GPDMA1_Channel4) for handle_GPDMA1_Channel4
     usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) for HAL_DMA_Init
-    usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority
-    usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.Node_GPDMA1_Channel3) for Node_GPDMA1_Channel3
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.List_GPDMA1_Channel3) for List_GPDMA1_Channel3
     usart.o(.text.HAL_UART_MspInit) refers to usart.o(.bss.handle_GPDMA1_Channel3) for handle_GPDMA1_Channel3
     usart.o(.ARM.exidx.text.HAL_UART_MspInit) refers to usart.o(.text.HAL_UART_MspInit) for [Anonymous Symbol]
     usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit
-    usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) for HAL_DMA_DeInit
     usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ
+    usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) for HAL_DMA_DeInit
     usart.o(.ARM.exidx.text.HAL_UART_MspDeInit) refers to usart.o(.text.HAL_UART_MspDeInit) for [Anonymous Symbol]
     stm32h5xx_it.o(.ARM.exidx.text.NMI_Handler) refers to stm32h5xx_it.o(.text.NMI_Handler) for [Anonymous Symbol]
     stm32h5xx_it.o(.ARM.exidx.text.HardFault_Handler) refers to stm32h5xx_it.o(.text.HardFault_Handler) for [Anonymous Symbol]
@@ -111,6 +139,9 @@ Section Cross References
     stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) refers to stm32h5xx_hal_timebase_tim.o(.bss.htim1) for htim1
     stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for HAL_TIM_IRQHandler
     stm32h5xx_it.o(.ARM.exidx.text.TIM1_UP_IRQHandler) refers to stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) for [Anonymous Symbol]
+    stm32h5xx_it.o(.text.TIM2_IRQHandler) refers to tim.o(.bss.htim2) for htim2
+    stm32h5xx_it.o(.text.TIM2_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for HAL_TIM_IRQHandler
+    stm32h5xx_it.o(.ARM.exidx.text.TIM2_IRQHandler) refers to stm32h5xx_it.o(.text.TIM2_IRQHandler) for [Anonymous Symbol]
     stm32h5xx_it.o(.text.USART1_IRQHandler) refers to usart.o(.bss.huart1) for huart1
     stm32h5xx_it.o(.text.USART1_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler
     stm32h5xx_it.o(.text.USART1_IRQHandler) refers to hcble.o(.bss.uart_dma_rx_buf) for uart_dma_rx_buf
@@ -121,6 +152,9 @@ Section Cross References
     stm32h5xx_it.o(.text.USART2_IRQHandler) refers to usart.o(.bss.huart2) for huart2
     stm32h5xx_it.o(.text.USART2_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler
     stm32h5xx_it.o(.ARM.exidx.text.USART2_IRQHandler) refers to stm32h5xx_it.o(.text.USART2_IRQHandler) for [Anonymous Symbol]
+    stm32h5xx_it.o(.text.UART5_IRQHandler) refers to usart.o(.bss.huart5) for huart5
+    stm32h5xx_it.o(.text.UART5_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler
+    stm32h5xx_it.o(.ARM.exidx.text.UART5_IRQHandler) refers to stm32h5xx_it.o(.text.UART5_IRQHandler) for [Anonymous Symbol]
     stm32h5xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit) refers to stm32h5xx_hal_msp.o(.text.HAL_MspInit) for [Anonymous Symbol]
     stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for HAL_RCC_GetClockConfig
     stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for HAL_RCC_GetPCLK2Freq
@@ -141,12 +175,12 @@ Section Cross References
     app_azure_rtos.o(.text.tx_application_define) refers to txe_byte_pool_create.o(.text._txe_byte_pool_create) for _txe_byte_pool_create
     app_azure_rtos.o(.text.tx_application_define) refers to app_threadx.o(.text.App_ThreadX_Init) for App_ThreadX_Init
     app_azure_rtos.o(.ARM.exidx.text.tx_application_define) refers to app_azure_rtos.o(.text.tx_application_define) for [Anonymous Symbol]
-    stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for HAL_TIM_Base_MspInit
+    stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to tim.o(.text.HAL_TIM_Base_MspInit) for HAL_TIM_Base_MspInit
     stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) for [Anonymous Symbol]
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol]
     stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for [Anonymous Symbol]
-    stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for HAL_TIM_Base_MspDeInit
+    stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) refers to tim.o(.text.HAL_TIM_Base_MspDeInit) for HAL_TIM_Base_MspDeInit
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) for [Anonymous Symbol]
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol]
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start) for [Anonymous Symbol]
@@ -243,7 +277,7 @@ Section Cross References
     stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError
     stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) for [Anonymous Symbol]
-    stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback
+    stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) refers to ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback
     stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for [Anonymous Symbol]
     stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for HAL_TIM_IC_CaptureHalfCpltCallback
     stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for [Anonymous Symbol]
@@ -289,7 +323,7 @@ Section Cross References
     stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd
     stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT
     stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) for [Anonymous Symbol]
-    stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback
+    stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback
     stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for HAL_TIM_OC_DelayElapsedCallback
     stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback
     stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback
@@ -589,157 +623,6 @@ Section Cross References
     stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes) for MPU_ConfigMemoryAttributes
     stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigMemoryAttributes) for [Anonymous Symbol]
     stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for DMA_Init
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for DMA_List_Init
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for DMA_List_BuildNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for DMA_List_GetNodeConfig
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for DMA_List_ResetQueueNodes
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for DMA_List_ConvertNodeToDynamic
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for DMA_List_UpdateDynamicQueueNodesCLLR
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToDynamic.update_link
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for DMA_List_ClearUnusedFields
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for DMA_List_UpdateStaticQueueNodesCLLR
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for DMA_List_ConvertNodeToStatic
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToStatic.update_link
-    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for [Anonymous Symbol]
-    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for [Anonymous Symbol]
     stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
     stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio
     stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick
@@ -966,6 +849,157 @@ Section Cross References
     stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for [Anonymous Symbol]
     stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Rising_Callback) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Rising_Callback) for [Anonymous Symbol]
     stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Falling_Callback) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Falling_Callback) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for DMA_Init
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes) for [Anonymous Symbol]
+    stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for DMA_List_Init
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for DMA_List_BuildNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for DMA_List_GetNodeConfig
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for DMA_List_ResetQueueNodes
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for DMA_List_ConvertNodeToDynamic
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for DMA_List_UpdateDynamicQueueNodesCLLR
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToDynamic.update_link
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for DMA_List_ClearUnusedFields
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for DMA_List_UpdateStaticQueueNodesCLLR
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for DMA_List_ConvertNodeToStatic
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToStatic.update_link
+    stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for [Anonymous Symbol]
+    stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for [Anonymous Symbol]
     stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DeInit) for [Anonymous Symbol]
     stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for [Anonymous Symbol]
     stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for [Anonymous Symbol]
@@ -2058,6 +2092,34 @@ Section Cross References
     gps.o(.text.Convert_to_degrees) refers to daddsub_clz.o(x$fpl$dsub) for __aeabi_dsub
     gps.o(.text.Convert_to_degrees) refers to daddsub_clz.o(x$fpl$dadd) for __aeabi_dadd
     gps.o(.ARM.exidx.text.Convert_to_degrees) refers to gps.o(.text.Convert_to_degrees) for [Anonymous Symbol]
+    buzzer.o(.text.Buzzer_Open) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    buzzer.o(.ARM.exidx.text.Buzzer_Open) refers to buzzer.o(.text.Buzzer_Open) for [Anonymous Symbol]
+    buzzer.o(.text.Buzzer_Close) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    buzzer.o(.ARM.exidx.text.Buzzer_Close) refers to buzzer.o(.text.Buzzer_Close) for [Anonymous Symbol]
+    shake_motor.o(.text.Shake_Motor_Open) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    shake_motor.o(.ARM.exidx.text.Shake_Motor_Open) refers to shake_motor.o(.text.Shake_Motor_Open) for [Anonymous Symbol]
+    shake_motor.o(.text.Shake_Motor_Close) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    shake_motor.o(.ARM.exidx.text.Shake_Motor_Close) refers to shake_motor.o(.text.Shake_Motor_Close) for [Anonymous Symbol]
+    ultrasound.o(.ARM.exidx.text.DWT_Init) refers to ultrasound.o(.text.DWT_Init) for [Anonymous Symbol]
+    ultrasound.o(.text.delay_us) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock
+    ultrasound.o(.ARM.exidx.text.delay_us) refers to ultrasound.o(.text.delay_us) for [Anonymous Symbol]
+    ultrasound.o(.text.HCSR04_Trigger) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for HAL_GPIO_WritePin
+    ultrasound.o(.text.HCSR04_Trigger) refers to ultrasound.o(.text.delay_us) for delay_us
+    ultrasound.o(.ARM.exidx.text.HCSR04_Trigger) refers to ultrasound.o(.text.HCSR04_Trigger) for [Anonymous Symbol]
+    ultrasound.o(.text.ultrasonic_task_entry) refers to tim.o(.bss.htim2) for htim2
+    ultrasound.o(.text.ultrasonic_task_entry) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) for HAL_TIM_IC_Start_IT
+    ultrasound.o(.text.ultrasonic_task_entry) refers to ultrasound.o(.text.HCSR04_Trigger) for HCSR04_Trigger
+    ultrasound.o(.text.ultrasonic_task_entry) refers to ultrasound.o(.bss.ultrasonic_event) for ultrasonic_event
+    ultrasound.o(.text.ultrasonic_task_entry) refers to txe_event_flags_get.o(.text._txe_event_flags_get) for _txe_event_flags_get
+    ultrasound.o(.text.ultrasonic_task_entry) refers to ultrasound.o(.bss.distance_cm) for distance_cm
+    ultrasound.o(.text.ultrasonic_task_entry) refers to tx_thread_sleep.o(.text._tx_thread_sleep) for _tx_thread_sleep
+    ultrasound.o(.ARM.exidx.text.ultrasonic_task_entry) refers to ultrasound.o(.text.ultrasonic_task_entry) for [Anonymous Symbol]
+    ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) refers to ultrasound.o(.bss.is_first_capture) for is_first_capture
+    ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue) for HAL_TIM_ReadCapturedValue
+    ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) refers to ultrasound.o(.bss.ic_val1) for ic_val1
+    ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) refers to ultrasound.o(.bss.ic_val2) for ic_val2
+    ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) refers to ultrasound.o(.bss.distance_cm) for distance_cm
+    ultrasound.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback) refers to ultrasound.o(.text.HAL_TIM_IC_CaptureCallback) for [Anonymous Symbol]
     vsprintf.o(.text) refers (Special) to _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) for _printf_a
     vsprintf.o(.text) refers (Special) to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c
     vsprintf.o(.text) refers (Special) to _printf_charcount.o(.text) for _printf_charcount
@@ -2563,11 +2625,17 @@ Removing Unused input sections from the image.
     Removing app_threadx.o(.text), (0 bytes).
     Removing app_threadx.o(.ARM.exidx.text.App_ThreadX_Init), (8 bytes).
     Removing app_threadx.o(.ARM.exidx.text.MX_ThreadX_Init), (8 bytes).
+    Removing tim.o(.text), (0 bytes).
+    Removing tim.o(.ARM.exidx.text.MX_TIM2_Init), (8 bytes).
+    Removing tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes).
+    Removing tim.o(.text.HAL_TIM_Base_MspDeInit), (58 bytes).
+    Removing tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit), (8 bytes).
     Removing usart.o(.text), (0 bytes).
+    Removing usart.o(.ARM.exidx.text.MX_UART5_Init), (8 bytes).
     Removing usart.o(.ARM.exidx.text.MX_USART1_UART_Init), (8 bytes).
     Removing usart.o(.ARM.exidx.text.MX_USART2_UART_Init), (8 bytes).
     Removing usart.o(.ARM.exidx.text.HAL_UART_MspInit), (8 bytes).
-    Removing usart.o(.text.HAL_UART_MspDeInit), (152 bytes).
+    Removing usart.o(.text.HAL_UART_MspDeInit), (212 bytes).
     Removing usart.o(.ARM.exidx.text.HAL_UART_MspDeInit), (8 bytes).
     Removing stm32h5xx_it.o(.text), (0 bytes).
     Removing stm32h5xx_it.o(.ARM.exidx.text.NMI_Handler), (8 bytes).
@@ -2580,8 +2648,10 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_it.o(.ARM.exidx.text.GPDMA1_Channel4_IRQHandler), (8 bytes).
     Removing stm32h5xx_it.o(.ARM.exidx.text.GPDMA1_Channel5_IRQHandler), (8 bytes).
     Removing stm32h5xx_it.o(.ARM.exidx.text.TIM1_UP_IRQHandler), (8 bytes).
+    Removing stm32h5xx_it.o(.ARM.exidx.text.TIM2_IRQHandler), (8 bytes).
     Removing stm32h5xx_it.o(.ARM.exidx.text.USART1_IRQHandler), (8 bytes).
     Removing stm32h5xx_it.o(.ARM.exidx.text.USART2_IRQHandler), (8 bytes).
+    Removing stm32h5xx_it.o(.ARM.exidx.text.UART5_IRQHandler), (8 bytes).
     Removing stm32h5xx_hal_msp.o(.text), (0 bytes).
     Removing stm32h5xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit), (8 bytes).
     Removing stm32h5xx_hal_timebase_tim.o(.text), (0 bytes).
@@ -2594,6 +2664,7 @@ Removing Unused input sections from the image.
     Removing app_azure_rtos.o(.ARM.exidx.text.tx_application_define), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text), (0 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init), (8 bytes).
+    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit), (178 bytes).
@@ -2665,9 +2736,7 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA), (638 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init), (168 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_DeInit), (178 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit), (8 bytes).
@@ -2726,6 +2795,7 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA), (470 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler), (8 bytes).
+    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback), (8 bytes).
@@ -2746,15 +2816,10 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC5_SetConfig), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.TIM_OC6_SetConfig), (292 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC6_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel), (304 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig), (440 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig), (108 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig), (106 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig), (108 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel), (432 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel), (8 bytes).
@@ -2780,15 +2845,10 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear), (500 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig), (52 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource), (520 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage), (80 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig), (48 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage), (82 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input), (44 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input), (8 bytes).
@@ -2798,7 +2858,6 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT), (150 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT), (8 bytes).
-    Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue), (86 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes).
     Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes).
@@ -2897,7 +2956,6 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt), (8 bytes).
     Removing stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt), (30 bytes).
     Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt), (8 bytes).
-    Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization), (530 bytes).
     Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization), (8 bytes).
     Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime), (340 bytes).
     Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime), (8 bytes).
@@ -3026,120 +3084,6 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigMemoryAttributes), (8 bytes).
     Removing stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes), (94 bytes).
     Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigMemoryAttributes), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text), (0 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit), (476 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_Start), (170 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer), (526 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback), (142 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback), (164 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState), (14 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes), (156 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes), (8 bytes).
-    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes), (88 bytes).
-    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text), (0 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit), (502 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start), (268 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig), (52 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig), (532 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head), (214 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail), (240 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode), (368 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue), (34 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head), (262 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail), (214 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode), (534 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head), (268 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail), (260 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ), (148 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes), (126 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ), (618 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head), (376 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail), (364 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig), (234 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode), (158 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic), (296 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode), (56 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic), (282 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR), (222 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic), (202 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR), (174 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic), (196 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ), (112 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling), (130 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger), (136 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock), (322 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend), (172 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT), (88 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume), (106 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel), (18 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode), (112 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields), (44 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields), (8 bytes).
-    Removing stm32h5xx_hal_dma_ex.o(.rodata.cst32), (64 bytes).
     Removing stm32h5xx_hal_rcc.o(.text), (0 bytes).
     Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit), (754 bytes).
     Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit), (8 bytes).
@@ -3340,7 +3284,6 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit), (8 bytes).
     Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_ReadPin), (46 bytes).
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin), (8 bytes).
-    Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin), (44 bytes).
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin), (8 bytes).
     Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WriteMultipleStatePin), (36 bytes).
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WriteMultipleStatePin), (8 bytes).
@@ -3358,6 +3301,120 @@ Removing Unused input sections from the image.
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Rising_Callback), (8 bytes).
     Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Falling_Callback), (10 bytes).
     Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Falling_Callback), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text), (0 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit), (476 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_Start), (170 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer), (526 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback), (142 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback), (164 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState), (14 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes), (156 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes), (8 bytes).
+    Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes), (88 bytes).
+    Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text), (0 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit), (502 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start), (268 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig), (52 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig), (532 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head), (214 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail), (240 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode), (368 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue), (34 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head), (262 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail), (214 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode), (534 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head), (268 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail), (260 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ), (148 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes), (126 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ), (618 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head), (376 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail), (364 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig), (234 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode), (158 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic), (296 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode), (56 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic), (282 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR), (222 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic), (202 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR), (174 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic), (196 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ), (112 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling), (130 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger), (136 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock), (322 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend), (172 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT), (88 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume), (106 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel), (18 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode), (112 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields), (44 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields), (8 bytes).
+    Removing stm32h5xx_hal_dma_ex.o(.rodata.cst32), (64 bytes).
     Removing stm32h5xx_hal_pwr.o(.text), (0 bytes).
     Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DeInit), (2 bytes).
     Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit), (8 bytes).
@@ -4240,8 +4297,30 @@ Removing Unused input sections from the image.
     Removing gps.o(.text.Convert_to_degrees), (176 bytes).
     Removing gps.o(.ARM.exidx.text.Convert_to_degrees), (8 bytes).
     Removing gps.o(.rodata.str1.1), (2 bytes).
+    Removing buzzer.o(.text), (0 bytes).
+    Removing buzzer.o(.text.Buzzer_Open), (20 bytes).
+    Removing buzzer.o(.ARM.exidx.text.Buzzer_Open), (8 bytes).
+    Removing buzzer.o(.text.Buzzer_Close), (20 bytes).
+    Removing buzzer.o(.ARM.exidx.text.Buzzer_Close), (8 bytes).
+    Removing shake_motor.o(.text), (0 bytes).
+    Removing shake_motor.o(.text.Shake_Motor_Open), (20 bytes).
+    Removing shake_motor.o(.ARM.exidx.text.Shake_Motor_Open), (8 bytes).
+    Removing shake_motor.o(.text.Shake_Motor_Close), (20 bytes).
+    Removing shake_motor.o(.ARM.exidx.text.Shake_Motor_Close), (8 bytes).
+    Removing ultrasound.o(.text), (0 bytes).
+    Removing ultrasound.o(.text.DWT_Init), (46 bytes).
+    Removing ultrasound.o(.ARM.exidx.text.DWT_Init), (8 bytes).
+    Removing ultrasound.o(.text.delay_us), (78 bytes).
+    Removing ultrasound.o(.ARM.exidx.text.delay_us), (8 bytes).
+    Removing ultrasound.o(.text.HCSR04_Trigger), (60 bytes).
+    Removing ultrasound.o(.ARM.exidx.text.HCSR04_Trigger), (8 bytes).
+    Removing ultrasound.o(.text.ultrasonic_task_entry), (84 bytes).
+    Removing ultrasound.o(.ARM.exidx.text.ultrasonic_task_entry), (8 bytes).
+    Removing ultrasound.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback), (8 bytes).
+    Removing ultrasound.o(.bss.ultrasonic_event), (36 bytes).
+    Removing ultrasound.o(.bss.ultrasonic_task_handle), (176 bytes).
 
-1691 unused section(s) (total 123383 bytes) removed from the image.
+1708 unused section(s) (total 121513 bytes) removed from the image.
 
 ==============================================================================
 
@@ -4447,7 +4526,10 @@ Image Symbol Table
     ../mathlib/frexp.c                       0x00000000   Number         0  frexp.o ABSOLUTE
     ../mathlib/ldexp.c                       0x00000000   Number         0  ldexp.o ABSOLUTE
     ../mathlib/narrow.c                      0x00000000   Number         0  narrow.o ABSOLUTE
+    Buzzer.c                                 0x00000000   Number         0  buzzer.o ABSOLUTE
     HCBle.c                                  0x00000000   Number         0  hcble.o ABSOLUTE
+    Shake_Motor.c                            0x00000000   Number         0  shake_motor.o ABSOLUTE
+    Ultrasound.c                             0x00000000   Number         0  ultrasound.o ABSOLUTE
     app_azure_rtos.c                         0x00000000   Number         0  app_azure_rtos.o ABSOLUTE
     app_threadx.c                            0x00000000   Number         0  app_threadx.o ABSOLUTE
     dc.s                                     0x00000000   Number         0  dc.o ABSOLUTE
@@ -4477,6 +4559,7 @@ Image Symbol Table
     stm32h5xx_hal_uart_ex.c                  0x00000000   Number         0  stm32h5xx_hal_uart_ex.o ABSOLUTE
     stm32h5xx_it.c                           0x00000000   Number         0  stm32h5xx_it.o ABSOLUTE
     system_stm32h5xx.c                       0x00000000   Number         0  system_stm32h5xx.o ABSOLUTE
+    tim.c                                    0x00000000   Number         0  tim.o ABSOLUTE
     tx_block_allocate.c                      0x00000000   Number         0  tx_block_allocate.o ABSOLUTE
     tx_block_pool_cleanup.c                  0x00000000   Number         0  tx_block_pool_cleanup.o ABSOLUTE
     tx_block_pool_create.c                   0x00000000   Number         0  tx_block_pool_create.o ABSOLUTE
@@ -4756,162 +4839,187 @@ Image Symbol Table
     [Anonymous Symbol]                       0x08002828   Section        0  stm32h5xx_hal_dma.o(.text.HAL_DMA_Init)
     [Anonymous Symbol]                       0x08002be8   Section        0  stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT)
     [Anonymous Symbol]                       0x08002ccc   Section        0  stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init)
-    [Anonymous Symbol]                       0x08002fb8   Section        0  stm32h5xx_hal.o(.text.HAL_GetTick)
-    [Anonymous Symbol]                       0x08002fc4   Section        0  stm32h5xx_hal.o(.text.HAL_IncTick)
-    [Anonymous Symbol]                       0x08002fe0   Section        0  stm32h5xx_hal.o(.text.HAL_Init)
-    [Anonymous Symbol]                       0x08003040   Section        0  stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick)
-    [Anonymous Symbol]                       0x08003110   Section        0  stm32h5xx_hal_msp.o(.text.HAL_MspInit)
-    [Anonymous Symbol]                       0x08003114   Section        0  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)
-    [Anonymous Symbol]                       0x08003128   Section        0  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)
-    [Anonymous Symbol]                       0x08003158   Section        0  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)
-    [Anonymous Symbol]                       0x08003168   Section        0  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq)
-    [Anonymous Symbol]                       0x08003460   Section        0  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq)
-    [Anonymous Symbol]                       0x08003758   Section        0  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq)
-    [Anonymous Symbol]                       0x08003a50   Section        0  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq)
-    [Anonymous Symbol]                       0x08006348   Section        0  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig)
-    [Anonymous Symbol]                       0x08007c38   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)
-    [Anonymous Symbol]                       0x080080cc   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig)
-    [Anonymous Symbol]                       0x08008138   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)
-    [Anonymous Symbol]                       0x0800816c   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)
-    [Anonymous Symbol]                       0x08008194   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq)
-    [Anonymous Symbol]                       0x080081bc   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq)
-    [Anonymous Symbol]                       0x080081e4   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)
-    [Anonymous Symbol]                       0x080084b0   Section        0  stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig)
-    [Anonymous Symbol]                       0x08008eac   Section        0  stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig)
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-    [Anonymous Symbol]                       0x08008f58   Section        0  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback)
-    [Anonymous Symbol]                       0x08008f60   Section        0  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback)
-    [Anonymous Symbol]                       0x08008f68   Section        0  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback)
-    [Anonymous Symbol]                       0x08008f70   Section        0  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback)
-    [Anonymous Symbol]                       0x08008f78   Section        0  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback)
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-    [Anonymous Symbol]                       0x08009028   Section        0  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit)
-    [Anonymous Symbol]                       0x08009030   Section        0  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT)
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-    [Anonymous Symbol]                       0x080094d4   Section        0  stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback)
-    [Anonymous Symbol]                       0x080094dc   Section        0  main.o(.text.HAL_TIM_PeriodElapsedCallback)
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-    [Anonymous Symbol]                       0x08009634   Section        0  gps.o(.text.HAL_UARTEx_RxEventCallback)
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+    [Anonymous Symbol]                       0x08009fe0   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive)
+    [Anonymous Symbol]                       0x0800a0f8   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback)
+    [Anonymous Symbol]                       0x0800a100   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler)
+    [Anonymous Symbol]                       0x0800a644   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_Init)
+    [Anonymous Symbol]                       0x0800a6f0   Section        0  usart.o(.text.HAL_UART_MspInit)
+    [Anonymous Symbol]                       0x0800ab5c   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA)
+    [Anonymous Symbol]                       0x0800ac10   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT)
+    [Anonymous Symbol]                       0x0800ace0   Section        0  hcble.o(.text.HAL_UART_RxCpltCallback)
+    [Anonymous Symbol]                       0x0800ad88   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback)
+    [Anonymous Symbol]                       0x0800ad90   Section        0  stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback)
+    [Anonymous Symbol]                       0x0800ad98   Section        0  hcble.o(.text.HCBle_InitDMAReception)
+    [Anonymous Symbol]                       0x0800adc4   Section        0  stm32h5xx_it.o(.text.HardFault_Handler)
+    [Anonymous Symbol]                       0x0800adc8   Section        0  gpdma.o(.text.MX_GPDMA1_Init)
+    [Anonymous Symbol]                       0x0800ae28   Section        0  gpio.o(.text.MX_GPIO_Init)
+    [Anonymous Symbol]                       0x0800af10   Section        0  tim.o(.text.MX_TIM2_Init)
+    [Anonymous Symbol]                       0x0800afd8   Section        0  app_threadx.o(.text.MX_ThreadX_Init)
+    [Anonymous Symbol]                       0x0800afe0   Section        0  usart.o(.text.MX_UART5_Init)
+    [Anonymous Symbol]                       0x0800b070   Section        0  usart.o(.text.MX_USART1_UART_Init)
+    [Anonymous Symbol]                       0x0800b100   Section        0  usart.o(.text.MX_USART2_UART_Init)
+    [Anonymous Symbol]                       0x0800b190   Section        0  stm32h5xx_it.o(.text.MemManage_Handler)
+    [Anonymous Symbol]                       0x0800b194   Section        0  stm32h5xx_it.o(.text.NMI_Handler)
+    NVIC_EncodePriority                      0x0800b199   Thumb Code   108  stm32h5xx_hal_cortex.o(.text.NVIC_EncodePriority)
+    [Anonymous Symbol]                       0x0800b198   Section        0  stm32h5xx_hal_cortex.o(.text.NVIC_EncodePriority)
+    RCCEx_PLL2_Config                        0x0800b205   Thumb Code   364  stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config)
+    [Anonymous Symbol]                       0x0800b204   Section        0  stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config)
+    RCCEx_PLL3_Config                        0x0800b371   Thumb Code   364  stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config)
+    [Anonymous Symbol]                       0x0800b370   Section        0  stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config)
+    [Anonymous Symbol]                       0x0800b4dc   Section        0  main.o(.text.SystemClock_Config)
+    [Anonymous Symbol]                       0x0800b5a4   Section        0  system_stm32h5xx.o(.text.SystemInit)
+    [Anonymous Symbol]                       0x0800b6dc   Section        0  stm32h5xx_it.o(.text.TIM1_UP_IRQHandler)
+    [Anonymous Symbol]                       0x0800b6ec   Section        0  stm32h5xx_it.o(.text.TIM2_IRQHandler)
+    [Anonymous Symbol]                       0x0800b6fc   Section        0  stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig)
+    [Anonymous Symbol]                       0x0800ba58   Section        0  stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig)
+    TIM_ITRx_SetConfig                       0x0800ba8d   Thumb Code    48  stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig)
+    [Anonymous Symbol]                       0x0800ba8c   Section        0  stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig)
+    TIM_TI1_ConfigInputStage                 0x0800babd   Thumb Code    80  stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage)
+    [Anonymous Symbol]                       0x0800babc   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage)
+    [Anonymous Symbol]                       0x0800bb0c   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig)
+    TIM_TI2_ConfigInputStage                 0x0800bcc5   Thumb Code    82  stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage)
+    [Anonymous Symbol]                       0x0800bcc4   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage)
+    TIM_TI2_SetConfig                        0x0800bd19   Thumb Code   108  stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig)
+    [Anonymous Symbol]                       0x0800bd18   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig)
+    TIM_TI3_SetConfig                        0x0800bd85   Thumb Code   106  stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig)
+    [Anonymous Symbol]                       0x0800bd84   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig)
+    TIM_TI4_SetConfig                        0x0800bdf1   Thumb Code   108  stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig)
+    [Anonymous Symbol]                       0x0800bdf0   Section        0  stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig)
+    [Anonymous Symbol]                       0x0800be5c   Section        0  stm32h5xx_it.o(.text.UART5_IRQHandler)
+    UARTEx_SetNbDataToProcess                0x0800be6d   Thumb Code   138  stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess)
+    [Anonymous Symbol]                       0x0800be6c   Section        0  stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess)
+    [Anonymous Symbol]                       0x0800bef8   Section        0  stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig)
+    [Anonymous Symbol]                       0x0800c040   Section        0  stm32h5xx_hal_uart.o(.text.UART_CheckIdleState)
+    UART_DMAAbortOnError                     0x0800c189   Thumb Code    30  stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError)
+    [Anonymous Symbol]                       0x0800c188   Section        0  stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError)
+    UART_DMAError                            0x0800c1a9   Thumb Code   128  stm32h5xx_hal_uart.o(.text.UART_DMAError)
+    [Anonymous Symbol]                       0x0800c1a8   Section        0  stm32h5xx_hal_uart.o(.text.UART_DMAError)
+    UART_DMAReceiveCplt                      0x0800c229   Thumb Code   260  stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt)
+    [Anonymous Symbol]                       0x0800c228   Section        0  stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt)
+    UART_DMARxHalfCplt                       0x0800c32d   Thumb Code   110  stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt)
+    [Anonymous Symbol]                       0x0800c32c   Section        0  stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt)
+    UART_EndRxTransfer                       0x0800c39d   Thumb Code   158  stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer)
+    [Anonymous Symbol]                       0x0800c39c   Section        0  stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer)
+    UART_EndTransmit_IT                      0x0800c43d   Thumb Code    68  stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT)
+    [Anonymous Symbol]                       0x0800c43c   Section        0  stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT)
+    UART_EndTxTransfer                       0x0800c481   Thumb Code    92  stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer)
+    [Anonymous Symbol]                       0x0800c480   Section        0  stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer)
+    UART_RxISR_16BIT                         0x0800c4dd   Thumb Code   406  stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT)
+    [Anonymous Symbol]                       0x0800c4dc   Section        0  stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT)
+    UART_RxISR_16BIT_FIFOEN                  0x0800c675   Thumb Code   794  stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN)
+    [Anonymous Symbol]                       0x0800c674   Section        0  stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN)
+    UART_RxISR_8BIT                          0x0800c991   Thumb Code   402  stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT)
+    [Anonymous Symbol]                       0x0800c990   Section        0  stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT)
+    UART_RxISR_8BIT_FIFOEN                   0x0800cb25   Thumb Code   790  stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN)
+    [Anonymous Symbol]                       0x0800cb24   Section        0  stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN)
+    [Anonymous Symbol]                       0x0800ce3c   Section        0  stm32h5xx_hal_uart.o(.text.UART_SetConfig)
+    [Anonymous Symbol]                       0x0800d254   Section        0  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
+    [Anonymous Symbol]                       0x0800d42c   Section        0  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
+    [Anonymous Symbol]                       0x0800d650   Section        0  stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout)
+    [Anonymous Symbol]                       0x0800d75c   Section        0  stm32h5xx_it.o(.text.USART1_IRQHandler)
+    [Anonymous Symbol]                       0x0800d7fc   Section        0  stm32h5xx_it.o(.text.USART2_IRQHandler)
+    [Anonymous Symbol]                       0x0800d80c   Section        0  stm32h5xx_it.o(.text.UsageFault_Handler)
+    __NVIC_EnableIRQ                         0x0800d811   Thumb Code    48  stm32h5xx_hal_cortex.o(.text.__NVIC_EnableIRQ)
+    [Anonymous Symbol]                       0x0800d810   Section        0  stm32h5xx_hal_cortex.o(.text.__NVIC_EnableIRQ)
+    __NVIC_GetPriorityGrouping               0x0800d841   Thumb Code    16  stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping)
+    [Anonymous Symbol]                       0x0800d840   Section        0  stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping)
+    __NVIC_SetPriority                       0x0800d851   Thumb Code    66  stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriority)
+    [Anonymous Symbol]                       0x0800d850   Section        0  stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriority)
+    __NVIC_SetPriorityGrouping               0x0800d895   Thumb Code    60  stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping)
+    [Anonymous Symbol]                       0x0800d894   Section        0  stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping)
+    [Anonymous Symbol]                       0x0800d8d0   Section        0  tx_byte_pool_create.o(.text._tx_byte_pool_create)
+    [Anonymous Symbol]                       0x0800da00   Section        0  tx_initialize_high_level.o(.text._tx_initialize_high_level)
+    [Anonymous Symbol]                       0x0800da88   Section        0  tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter)
+    [Anonymous Symbol]                       0x0800daf0   Section        0  tx_thread_create.o(.text._tx_thread_create)
+    [Anonymous Symbol]                       0x0800dd0c   Section        0  tx_thread_initialize.o(.text._tx_thread_initialize)
+    [Anonymous Symbol]                       0x0800dd8c   Section        0  tx_thread_shell_entry.o(.text._tx_thread_shell_entry)
+    [Anonymous Symbol]                       0x0800de20   Section        0  tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check)
+    [Anonymous Symbol]                       0x0800de90   Section        0  tx_thread_system_resume.o(.text._tx_thread_system_resume)
+    [Anonymous Symbol]                       0x0800e0d8   Section        0  tx_thread_system_suspend.o(.text._tx_thread_system_suspend)
+    [Anonymous Symbol]                       0x0800e358   Section        0  tx_thread_time_slice.o(.text._tx_thread_time_slice)
+    [Anonymous Symbol]                       0x0800e3fc   Section        0  tx_thread_timeout.o(.text._tx_thread_timeout)
+    [Anonymous Symbol]                       0x0800e470   Section        0  tx_timer_expiration_process.o(.text._tx_timer_expiration_process)
+    [Anonymous Symbol]                       0x0800e4ac   Section        0  tx_timer_initialize.o(.text._tx_timer_initialize)
+    [Anonymous Symbol]                       0x0800e5cc   Section        0  tx_timer_system_activate.o(.text._tx_timer_system_activate)
+    [Anonymous Symbol]                       0x0800e6a0   Section        0  tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate)
+    [Anonymous Symbol]                       0x0800e710   Section        0  tx_timer_thread_entry.o(.text._tx_timer_thread_entry)
+    [Anonymous Symbol]                       0x0800e928   Section        0  txe_byte_pool_create.o(.text._txe_byte_pool_create)
+    [Anonymous Symbol]                       0x0800ea9c   Section        0  main.o(.text.main)
+    [Anonymous Symbol]                       0x0800eacc   Section        0  app_azure_rtos.o(.text.tx_application_define)
+    $v0                                      0x0800eb24   Number         0  fpinit.o(x$fpl$fpinit)
+    x$fpl$fpinit                             0x0800eb24   Section       26  fpinit.o(x$fpl$fpinit)
+    UARTEx_SetNbDataToProcess.denominator    0x0800eb56   Data           8  stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.denominator)
+    [Anonymous Symbol]                       0x0800eb56   Section        0  stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.denominator)
+    UARTEx_SetNbDataToProcess.numerator      0x0800eb5e   Data           8  stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.numerator)
+    [Anonymous Symbol]                       0x0800eb5e   Section        0  stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.numerator)
+    .L.str                                   0x0800eb7e   Data          19  app_azure_rtos.o(.rodata.str1.1)
+    [Anonymous Symbol]                       0x0800eb7e   Section        0  app_azure_rtos.o(.rodata.str1.1)
+    .L.str                                   0x0800eb91   Data          20  tx_timer_initialize.o(.rodata.str1.1)
+    [Anonymous Symbol]                       0x0800eb91   Section        0  tx_timer_initialize.o(.rodata.str1.1)
     SYSTEM_CLOCK                             0x0ee6b280   Number         0  tx_initialize_low_level.o ABSOLUTE
     .bss                                     0x20000010   Section       96  libspace.o(.bss)
-    tx_app_byte_pool                         0x20000cd4   Data          52  app_azure_rtos.o(.bss.tx_app_byte_pool)
-    [Anonymous Symbol]                       0x20000cd4   Section        0  app_azure_rtos.o(.bss.tx_app_byte_pool)
-    tx_byte_pool_buffer                      0x20000d08   Data        1024  app_azure_rtos.o(.bss.tx_byte_pool_buffer)
-    [Anonymous Symbol]                       0x20000d08   Section        0  app_azure_rtos.o(.bss.tx_byte_pool_buffer)
-    Heap_Mem                                 0x20001150   Data         512  startup_stm32h563xx.o(HEAP)
-    HEAP                                     0x20001150   Section      512  startup_stm32h563xx.o(HEAP)
-    Stack_Mem                                0x20001350   Data        1024  startup_stm32h563xx.o(STACK)
-    STACK                                    0x20001350   Section     1024  startup_stm32h563xx.o(STACK)
-    __initial_sp                             0x20001750   Data           0  startup_stm32h563xx.o(STACK)
+    tx_app_byte_pool                         0x20000dc0   Data          52  app_azure_rtos.o(.bss.tx_app_byte_pool)
+    [Anonymous Symbol]                       0x20000dc0   Section        0  app_azure_rtos.o(.bss.tx_app_byte_pool)
+    tx_byte_pool_buffer                      0x20000df4   Data        1024  app_azure_rtos.o(.bss.tx_byte_pool_buffer)
+    [Anonymous Symbol]                       0x20000df4   Section        0  app_azure_rtos.o(.bss.tx_byte_pool_buffer)
+    Heap_Mem                                 0x20001238   Data         512  startup_stm32h563xx.o(HEAP)
+    HEAP                                     0x20001238   Section      512  startup_stm32h563xx.o(HEAP)
+    Stack_Mem                                0x20001438   Data        1024  startup_stm32h563xx.o(STACK)
+    STACK                                    0x20001438   Section     1024  startup_stm32h563xx.o(STACK)
+    __initial_sp                             0x20001838   Data           0  startup_stm32h563xx.o(STACK)
 
     Global Symbols
 
@@ -5104,7 +5212,6 @@ Image Symbol Table
     TIM1_BRK_IRQHandler                      0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     TIM1_CC_IRQHandler                       0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     TIM1_TRG_COM_IRQHandler                  0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
-    TIM2_IRQHandler                          0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     TIM3_IRQHandler                          0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     TIM4_IRQHandler                          0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     TIM5_IRQHandler                          0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
@@ -5116,7 +5223,6 @@ Image Symbol Table
     TIM8_UP_IRQHandler                       0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     UART12_IRQHandler                        0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     UART4_IRQHandler                         0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
-    UART5_IRQHandler                         0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     UART7_IRQHandler                         0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     UART8_IRQHandler                         0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
     UART9_IRQHandler                         0x08000335   Thumb Code     0  startup_stm32h563xx.o(.text)
@@ -5189,111 +5295,124 @@ Image Symbol Table
     HAL_DMA_Init                             0x08002829   Thumb Code   960  stm32h5xx_hal_dma.o(.text.HAL_DMA_Init)
     HAL_DMA_Start_IT                         0x08002be9   Thumb Code   226  stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT)
     HAL_GPIO_Init                            0x08002ccd   Thumb Code   746  stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init)
-    HAL_GetTick                              0x08002fb9   Thumb Code    12  stm32h5xx_hal.o(.text.HAL_GetTick)
-    HAL_IncTick                              0x08002fc5   Thumb Code    26  stm32h5xx_hal.o(.text.HAL_IncTick)
-    HAL_Init                                 0x08002fe1   Thumb Code    94  stm32h5xx_hal.o(.text.HAL_Init)
-    HAL_InitTick                             0x08003041   Thumb Code   206  stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick)
-    HAL_MspInit                              0x08003111   Thumb Code     2  stm32h5xx_hal_msp.o(.text.HAL_MspInit)
-    HAL_NVIC_EnableIRQ                       0x08003115   Thumb Code    20  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)
-    HAL_NVIC_SetPriority                     0x08003129   Thumb Code    46  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)
-    HAL_NVIC_SetPriorityGrouping             0x08003159   Thumb Code    16  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)
-    HAL_RCCEx_GetPLL1ClockFreq               0x08003169   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq)
-    HAL_RCCEx_GetPLL2ClockFreq               0x08003461   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq)
-    HAL_RCCEx_GetPLL3ClockFreq               0x08003759   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq)
-    HAL_RCCEx_GetPeriphCLKFreq               0x08003a51   Thumb Code 10488  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq)
-    HAL_RCCEx_PeriphCLKConfig                0x08006349   Thumb Code  6382  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig)
-    HAL_RCC_ClockConfig                      0x08007c39   Thumb Code  1172  stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)
-    HAL_RCC_GetClockConfig                   0x080080cd   Thumb Code   108  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig)
-    HAL_RCC_GetHCLKFreq                      0x08008139   Thumb Code    52  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)
-    HAL_RCC_GetPCLK1Freq                     0x0800816d   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)
-    HAL_RCC_GetPCLK2Freq                     0x08008195   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq)
-    HAL_RCC_GetPCLK3Freq                     0x080081bd   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq)
-    HAL_RCC_GetSysClockFreq                  0x080081e5   Thumb Code   700  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)
-    HAL_RCC_OscConfig                        0x080084b1   Thumb Code  2556  stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig)
-    HAL_SYSTICK_CLKSourceConfig              0x08008ead   Thumb Code   154  stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig)
-    HAL_TIMEx_Break2Callback                 0x08008f49   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback)
-    HAL_TIMEx_BreakCallback                  0x08008f51   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback)
-    HAL_TIMEx_CommutCallback                 0x08008f59   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback)
-    HAL_TIMEx_DirectionChangeCallback        0x08008f61   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback)
-    HAL_TIMEx_EncoderIndexCallback           0x08008f69   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback)
-    HAL_TIMEx_IndexErrorCallback             0x08008f71   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback)
-    HAL_TIMEx_TransitionErrorCallback        0x08008f79   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback)
-    HAL_TIM_Base_Init                        0x08008f81   Thumb Code   168  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init)
-    HAL_TIM_Base_MspInit                     0x08009029   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit)
-    HAL_TIM_Base_Start_IT                    0x08009031   Thumb Code   402  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT)
-    HAL_TIM_IC_CaptureCallback               0x080091c5   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback)
-    HAL_TIM_IRQHandler                       0x080091cd   Thumb Code   768  stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler)
-    HAL_TIM_OC_DelayElapsedCallback          0x080094cd   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback)
-    HAL_TIM_PWM_PulseFinishedCallback        0x080094d5   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback)
-    HAL_TIM_PeriodElapsedCallback            0x080094dd   Thumb Code    34  main.o(.text.HAL_TIM_PeriodElapsedCallback)
-    HAL_TIM_TriggerCallback                  0x08009501   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback)
-    HAL_UARTEx_DisableFifoMode               0x08009509   Thumb Code   124  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode)
-    HAL_UARTEx_ReceiveToIdle_DMA             0x08009585   Thumb Code   176  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA)
-    HAL_UARTEx_RxEventCallback               0x08009635   Thumb Code   112  gps.o(.text.HAL_UARTEx_RxEventCallback)
-    HAL_UARTEx_RxFifoFullCallback            0x080096a5   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback)
-    HAL_UARTEx_SetRxFifoThreshold            0x080096ad   Thumb Code   140  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold)
-    HAL_UARTEx_SetTxFifoThreshold            0x08009739   Thumb Code   140  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold)
-    HAL_UARTEx_TxFifoEmptyCallback           0x080097c5   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback)
-    HAL_UARTEx_WakeupCallback                0x080097cd   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback)
-    HAL_UART_AbortReceive                    0x080097d5   Thumb Code   278  stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive)
-    HAL_UART_ErrorCallback                   0x080098ed   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback)
-    HAL_UART_IRQHandler                      0x080098f5   Thumb Code  1346  stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler)
-    HAL_UART_Init                            0x08009e39   Thumb Code   170  stm32h5xx_hal_uart.o(.text.HAL_UART_Init)
-    HAL_UART_MspInit                         0x08009ee5   Thumb Code   968  usart.o(.text.HAL_UART_MspInit)
-    HAL_UART_Receive_DMA                     0x0800a2ad   Thumb Code   178  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA)
-    HAL_UART_Receive_IT                      0x0800a361   Thumb Code   206  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT)
-    HAL_UART_RxCpltCallback                  0x0800a431   Thumb Code   166  hcble.o(.text.HAL_UART_RxCpltCallback)
-    HAL_UART_RxHalfCpltCallback              0x0800a4d9   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback)
-    HAL_UART_TxCpltCallback                  0x0800a4e1   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback)
-    HCBle_InitDMAReception                   0x0800a4e9   Thumb Code    44  hcble.o(.text.HCBle_InitDMAReception)
-    HardFault_Handler                        0x0800a515   Thumb Code     4  stm32h5xx_it.o(.text.HardFault_Handler)
-    MX_GPDMA1_Init                           0x0800a519   Thumb Code    94  gpdma.o(.text.MX_GPDMA1_Init)
-    MX_GPIO_Init                             0x0800a579   Thumb Code    96  gpio.o(.text.MX_GPIO_Init)
-    MX_ThreadX_Init                          0x0800a5d9   Thumb Code     8  app_threadx.o(.text.MX_ThreadX_Init)
-    MX_USART1_UART_Init                      0x0800a5e1   Thumb Code   142  usart.o(.text.MX_USART1_UART_Init)
-    MX_USART2_UART_Init                      0x0800a671   Thumb Code   142  usart.o(.text.MX_USART2_UART_Init)
-    MemManage_Handler                        0x0800a701   Thumb Code     4  stm32h5xx_it.o(.text.MemManage_Handler)
-    NMI_Handler                              0x0800a705   Thumb Code     4  stm32h5xx_it.o(.text.NMI_Handler)
-    SystemClock_Config                       0x0800aa4d   Thumb Code   198  main.o(.text.SystemClock_Config)
-    SystemInit                               0x0800ab15   Thumb Code   310  system_stm32h5xx.o(.text.SystemInit)
-    TIM1_UP_IRQHandler                       0x0800ac4d   Thumb Code    16  stm32h5xx_it.o(.text.TIM1_UP_IRQHandler)
-    TIM_Base_SetConfig                       0x0800ac5d   Thumb Code   858  stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig)
-    UART_AdvFeatureConfig                    0x0800b045   Thumb Code   328  stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig)
-    UART_CheckIdleState                      0x0800b18d   Thumb Code   326  stm32h5xx_hal_uart.o(.text.UART_CheckIdleState)
-    UART_SetConfig                           0x0800bf89   Thumb Code  1048  stm32h5xx_hal_uart.o(.text.UART_SetConfig)
-    UART_Start_Receive_DMA                   0x0800c3a1   Thumb Code   472  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
-    UART_Start_Receive_IT                    0x0800c579   Thumb Code   546  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
-    UART_WaitOnFlagUntilTimeout              0x0800c79d   Thumb Code   268  stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout)
-    USART1_IRQHandler                        0x0800c8a9   Thumb Code   160  stm32h5xx_it.o(.text.USART1_IRQHandler)
-    USART2_IRQHandler                        0x0800c949   Thumb Code    16  stm32h5xx_it.o(.text.USART2_IRQHandler)
-    UsageFault_Handler                       0x0800c959   Thumb Code     4  stm32h5xx_it.o(.text.UsageFault_Handler)
-    _tx_byte_pool_create                     0x0800ca1d   Thumb Code   304  tx_byte_pool_create.o(.text._tx_byte_pool_create)
-    _tx_initialize_high_level                0x0800cb4d   Thumb Code   134  tx_initialize_high_level.o(.text._tx_initialize_high_level)
-    _tx_initialize_kernel_enter              0x0800cbd5   Thumb Code   104  tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter)
-    _tx_thread_create                        0x0800cc3d   Thumb Code   538  tx_thread_create.o(.text._tx_thread_create)
-    _tx_thread_initialize                    0x0800ce59   Thumb Code   126  tx_thread_initialize.o(.text._tx_thread_initialize)
-    _tx_thread_shell_entry                   0x0800ced9   Thumb Code   148  tx_thread_shell_entry.o(.text._tx_thread_shell_entry)
-    _tx_thread_system_preempt_check          0x0800cf6d   Thumb Code   112  tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check)
-    _tx_thread_system_resume                 0x0800cfdd   Thumb Code   584  tx_thread_system_resume.o(.text._tx_thread_system_resume)
-    _tx_thread_system_suspend                0x0800d225   Thumb Code   640  tx_thread_system_suspend.o(.text._tx_thread_system_suspend)
-    _tx_thread_time_slice                    0x0800d4a5   Thumb Code   162  tx_thread_time_slice.o(.text._tx_thread_time_slice)
-    _tx_thread_timeout                       0x0800d549   Thumb Code   114  tx_thread_timeout.o(.text._tx_thread_timeout)
-    _tx_timer_expiration_process             0x0800d5bd   Thumb Code    60  tx_timer_expiration_process.o(.text._tx_timer_expiration_process)
-    _tx_timer_initialize                     0x0800d5f9   Thumb Code   286  tx_timer_initialize.o(.text._tx_timer_initialize)
-    _tx_timer_system_activate                0x0800d719   Thumb Code   212  tx_timer_system_activate.o(.text._tx_timer_system_activate)
-    _tx_timer_system_deactivate              0x0800d7ed   Thumb Code   112  tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate)
-    _tx_timer_thread_entry                   0x0800d85d   Thumb Code   536  tx_timer_thread_entry.o(.text._tx_timer_thread_entry)
-    _txe_byte_pool_create                    0x0800da75   Thumb Code   372  txe_byte_pool_create.o(.text._txe_byte_pool_create)
-    main                                     0x0800dbe9   Thumb Code    40  main.o(.text.main)
-    tx_application_define                    0x0800dc11   Thumb Code    88  app_azure_rtos.o(.text.tx_application_define)
-    _fp_init                                 0x0800dc69   Thumb Code    26  fpinit.o(x$fpl$fpinit)
-    __fplib_config_fpu_vfp                   0x0800dc81   Thumb Code     0  fpinit.o(x$fpl$fpinit)
-    __fplib_config_pureend_doubles           0x0800dc81   Thumb Code     0  fpinit.o(x$fpl$fpinit)
-    AHBPrescTable                            0x0800dc82   Data          16  system_stm32h5xx.o(.rodata.AHBPrescTable)
-    APBPrescTable                            0x0800dc92   Data           8  system_stm32h5xx.o(.rodata.APBPrescTable)
-    UARTPrescTable                           0x0800dcaa   Data          24  stm32h5xx_hal_uart.o(.rodata.UARTPrescTable)
-    Region$$Table$$Base                      0x0800dcec   Number         0  anon$$obj.o(Region$$Table)
-    Region$$Table$$Limit                     0x0800dd0c   Number         0  anon$$obj.o(Region$$Table)
+    HAL_GPIO_WritePin                        0x08002fb9   Thumb Code    44  stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin)
+    HAL_GetTick                              0x08002fe5   Thumb Code    12  stm32h5xx_hal.o(.text.HAL_GetTick)
+    HAL_IncTick                              0x08002ff1   Thumb Code    26  stm32h5xx_hal.o(.text.HAL_IncTick)
+    HAL_Init                                 0x0800300d   Thumb Code    94  stm32h5xx_hal.o(.text.HAL_Init)
+    HAL_InitTick                             0x0800306d   Thumb Code   206  stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick)
+    HAL_MspInit                              0x0800313d   Thumb Code     2  stm32h5xx_hal_msp.o(.text.HAL_MspInit)
+    HAL_NVIC_EnableIRQ                       0x08003141   Thumb Code    20  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)
+    HAL_NVIC_SetPriority                     0x08003155   Thumb Code    46  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)
+    HAL_NVIC_SetPriorityGrouping             0x08003185   Thumb Code    16  stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)
+    HAL_RCCEx_GetPLL1ClockFreq               0x08003195   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq)
+    HAL_RCCEx_GetPLL2ClockFreq               0x0800348d   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq)
+    HAL_RCCEx_GetPLL3ClockFreq               0x08003785   Thumb Code   748  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq)
+    HAL_RCCEx_GetPeriphCLKFreq               0x08003a7d   Thumb Code 10488  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq)
+    HAL_RCCEx_PeriphCLKConfig                0x08006375   Thumb Code  6382  stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig)
+    HAL_RCC_ClockConfig                      0x08007c65   Thumb Code  1172  stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)
+    HAL_RCC_GetClockConfig                   0x080080f9   Thumb Code   108  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig)
+    HAL_RCC_GetHCLKFreq                      0x08008165   Thumb Code    52  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)
+    HAL_RCC_GetPCLK1Freq                     0x08008199   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)
+    HAL_RCC_GetPCLK2Freq                     0x080081c1   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq)
+    HAL_RCC_GetPCLK3Freq                     0x080081e9   Thumb Code    38  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq)
+    HAL_RCC_GetSysClockFreq                  0x08008211   Thumb Code   700  stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)
+    HAL_RCC_OscConfig                        0x080084dd   Thumb Code  2556  stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig)
+    HAL_SYSTICK_CLKSourceConfig              0x08008ed9   Thumb Code   154  stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig)
+    HAL_TIMEx_Break2Callback                 0x08008f75   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback)
+    HAL_TIMEx_BreakCallback                  0x08008f7d   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback)
+    HAL_TIMEx_CommutCallback                 0x08008f85   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback)
+    HAL_TIMEx_DirectionChangeCallback        0x08008f8d   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback)
+    HAL_TIMEx_EncoderIndexCallback           0x08008f95   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback)
+    HAL_TIMEx_IndexErrorCallback             0x08008f9d   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback)
+    HAL_TIMEx_MasterConfigSynchronization    0x08008fa5   Thumb Code   530  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization)
+    HAL_TIMEx_TransitionErrorCallback        0x080091b9   Thumb Code     8  stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback)
+    HAL_TIM_Base_Init                        0x080091c1   Thumb Code   168  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init)
+    HAL_TIM_Base_MspInit                     0x08009269   Thumb Code   144  tim.o(.text.HAL_TIM_Base_MspInit)
+    HAL_TIM_Base_Start_IT                    0x080092f9   Thumb Code   402  stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT)
+    HAL_TIM_ConfigClockSource                0x0800948d   Thumb Code   520  stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource)
+    HAL_TIM_IC_CaptureCallback               0x08009695   Thumb Code   266  ultrasound.o(.text.HAL_TIM_IC_CaptureCallback)
+    HAL_TIM_IC_ConfigChannel                 0x080097a1   Thumb Code   304  stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel)
+    HAL_TIM_IC_Init                          0x080098d1   Thumb Code   168  stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init)
+    HAL_TIM_IC_MspInit                       0x08009979   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit)
+    HAL_TIM_IRQHandler                       0x08009981   Thumb Code   768  stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler)
+    HAL_TIM_OC_DelayElapsedCallback          0x08009c81   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback)
+    HAL_TIM_PWM_PulseFinishedCallback        0x08009c89   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback)
+    HAL_TIM_PeriodElapsedCallback            0x08009c91   Thumb Code    34  main.o(.text.HAL_TIM_PeriodElapsedCallback)
+    HAL_TIM_ReadCapturedValue                0x08009cb5   Thumb Code    86  stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue)
+    HAL_TIM_TriggerCallback                  0x08009d0d   Thumb Code     8  stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback)
+    HAL_UARTEx_DisableFifoMode               0x08009d15   Thumb Code   124  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode)
+    HAL_UARTEx_ReceiveToIdle_DMA             0x08009d91   Thumb Code   176  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA)
+    HAL_UARTEx_RxEventCallback               0x08009e41   Thumb Code   112  gps.o(.text.HAL_UARTEx_RxEventCallback)
+    HAL_UARTEx_RxFifoFullCallback            0x08009eb1   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback)
+    HAL_UARTEx_SetRxFifoThreshold            0x08009eb9   Thumb Code   140  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold)
+    HAL_UARTEx_SetTxFifoThreshold            0x08009f45   Thumb Code   140  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold)
+    HAL_UARTEx_TxFifoEmptyCallback           0x08009fd1   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback)
+    HAL_UARTEx_WakeupCallback                0x08009fd9   Thumb Code     8  stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback)
+    HAL_UART_AbortReceive                    0x08009fe1   Thumb Code   278  stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive)
+    HAL_UART_ErrorCallback                   0x0800a0f9   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback)
+    HAL_UART_IRQHandler                      0x0800a101   Thumb Code  1346  stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler)
+    HAL_UART_Init                            0x0800a645   Thumb Code   170  stm32h5xx_hal_uart.o(.text.HAL_UART_Init)
+    HAL_UART_MspInit                         0x0800a6f1   Thumb Code  1130  usart.o(.text.HAL_UART_MspInit)
+    HAL_UART_Receive_DMA                     0x0800ab5d   Thumb Code   178  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA)
+    HAL_UART_Receive_IT                      0x0800ac11   Thumb Code   206  stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT)
+    HAL_UART_RxCpltCallback                  0x0800ace1   Thumb Code   166  hcble.o(.text.HAL_UART_RxCpltCallback)
+    HAL_UART_RxHalfCpltCallback              0x0800ad89   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback)
+    HAL_UART_TxCpltCallback                  0x0800ad91   Thumb Code     8  stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback)
+    HCBle_InitDMAReception                   0x0800ad99   Thumb Code    44  hcble.o(.text.HCBle_InitDMAReception)
+    HardFault_Handler                        0x0800adc5   Thumb Code     4  stm32h5xx_it.o(.text.HardFault_Handler)
+    MX_GPDMA1_Init                           0x0800adc9   Thumb Code    94  gpdma.o(.text.MX_GPDMA1_Init)
+    MX_GPIO_Init                             0x0800ae29   Thumb Code   230  gpio.o(.text.MX_GPIO_Init)
+    MX_TIM2_Init                             0x0800af11   Thumb Code   198  tim.o(.text.MX_TIM2_Init)
+    MX_ThreadX_Init                          0x0800afd9   Thumb Code     8  app_threadx.o(.text.MX_ThreadX_Init)
+    MX_UART5_Init                            0x0800afe1   Thumb Code   142  usart.o(.text.MX_UART5_Init)
+    MX_USART1_UART_Init                      0x0800b071   Thumb Code   142  usart.o(.text.MX_USART1_UART_Init)
+    MX_USART2_UART_Init                      0x0800b101   Thumb Code   142  usart.o(.text.MX_USART2_UART_Init)
+    MemManage_Handler                        0x0800b191   Thumb Code     4  stm32h5xx_it.o(.text.MemManage_Handler)
+    NMI_Handler                              0x0800b195   Thumb Code     4  stm32h5xx_it.o(.text.NMI_Handler)
+    SystemClock_Config                       0x0800b4dd   Thumb Code   198  main.o(.text.SystemClock_Config)
+    SystemInit                               0x0800b5a5   Thumb Code   310  system_stm32h5xx.o(.text.SystemInit)
+    TIM1_UP_IRQHandler                       0x0800b6dd   Thumb Code    16  stm32h5xx_it.o(.text.TIM1_UP_IRQHandler)
+    TIM2_IRQHandler                          0x0800b6ed   Thumb Code    16  stm32h5xx_it.o(.text.TIM2_IRQHandler)
+    TIM_Base_SetConfig                       0x0800b6fd   Thumb Code   858  stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig)
+    TIM_ETR_SetConfig                        0x0800ba59   Thumb Code    52  stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig)
+    TIM_TI1_SetConfig                        0x0800bb0d   Thumb Code   440  stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig)
+    UART5_IRQHandler                         0x0800be5d   Thumb Code    16  stm32h5xx_it.o(.text.UART5_IRQHandler)
+    UART_AdvFeatureConfig                    0x0800bef9   Thumb Code   328  stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig)
+    UART_CheckIdleState                      0x0800c041   Thumb Code   326  stm32h5xx_hal_uart.o(.text.UART_CheckIdleState)
+    UART_SetConfig                           0x0800ce3d   Thumb Code  1048  stm32h5xx_hal_uart.o(.text.UART_SetConfig)
+    UART_Start_Receive_DMA                   0x0800d255   Thumb Code   472  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA)
+    UART_Start_Receive_IT                    0x0800d42d   Thumb Code   546  stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT)
+    UART_WaitOnFlagUntilTimeout              0x0800d651   Thumb Code   268  stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout)
+    USART1_IRQHandler                        0x0800d75d   Thumb Code   160  stm32h5xx_it.o(.text.USART1_IRQHandler)
+    USART2_IRQHandler                        0x0800d7fd   Thumb Code    16  stm32h5xx_it.o(.text.USART2_IRQHandler)
+    UsageFault_Handler                       0x0800d80d   Thumb Code     4  stm32h5xx_it.o(.text.UsageFault_Handler)
+    _tx_byte_pool_create                     0x0800d8d1   Thumb Code   304  tx_byte_pool_create.o(.text._tx_byte_pool_create)
+    _tx_initialize_high_level                0x0800da01   Thumb Code   134  tx_initialize_high_level.o(.text._tx_initialize_high_level)
+    _tx_initialize_kernel_enter              0x0800da89   Thumb Code   104  tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter)
+    _tx_thread_create                        0x0800daf1   Thumb Code   538  tx_thread_create.o(.text._tx_thread_create)
+    _tx_thread_initialize                    0x0800dd0d   Thumb Code   126  tx_thread_initialize.o(.text._tx_thread_initialize)
+    _tx_thread_shell_entry                   0x0800dd8d   Thumb Code   148  tx_thread_shell_entry.o(.text._tx_thread_shell_entry)
+    _tx_thread_system_preempt_check          0x0800de21   Thumb Code   112  tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check)
+    _tx_thread_system_resume                 0x0800de91   Thumb Code   584  tx_thread_system_resume.o(.text._tx_thread_system_resume)
+    _tx_thread_system_suspend                0x0800e0d9   Thumb Code   640  tx_thread_system_suspend.o(.text._tx_thread_system_suspend)
+    _tx_thread_time_slice                    0x0800e359   Thumb Code   162  tx_thread_time_slice.o(.text._tx_thread_time_slice)
+    _tx_thread_timeout                       0x0800e3fd   Thumb Code   114  tx_thread_timeout.o(.text._tx_thread_timeout)
+    _tx_timer_expiration_process             0x0800e471   Thumb Code    60  tx_timer_expiration_process.o(.text._tx_timer_expiration_process)
+    _tx_timer_initialize                     0x0800e4ad   Thumb Code   286  tx_timer_initialize.o(.text._tx_timer_initialize)
+    _tx_timer_system_activate                0x0800e5cd   Thumb Code   212  tx_timer_system_activate.o(.text._tx_timer_system_activate)
+    _tx_timer_system_deactivate              0x0800e6a1   Thumb Code   112  tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate)
+    _tx_timer_thread_entry                   0x0800e711   Thumb Code   536  tx_timer_thread_entry.o(.text._tx_timer_thread_entry)
+    _txe_byte_pool_create                    0x0800e929   Thumb Code   372  txe_byte_pool_create.o(.text._txe_byte_pool_create)
+    main                                     0x0800ea9d   Thumb Code    48  main.o(.text.main)
+    tx_application_define                    0x0800eacd   Thumb Code    88  app_azure_rtos.o(.text.tx_application_define)
+    _fp_init                                 0x0800eb25   Thumb Code    26  fpinit.o(x$fpl$fpinit)
+    __fplib_config_fpu_vfp                   0x0800eb3d   Thumb Code     0  fpinit.o(x$fpl$fpinit)
+    __fplib_config_pureend_doubles           0x0800eb3d   Thumb Code     0  fpinit.o(x$fpl$fpinit)
+    AHBPrescTable                            0x0800eb3e   Data          16  system_stm32h5xx.o(.rodata.AHBPrescTable)
+    APBPrescTable                            0x0800eb4e   Data           8  system_stm32h5xx.o(.rodata.APBPrescTable)
+    UARTPrescTable                           0x0800eb66   Data          24  stm32h5xx_hal_uart.o(.rodata.UARTPrescTable)
+    Region$$Table$$Base                      0x0800eba8   Number         0  anon$$obj.o(Region$$Table)
+    Region$$Table$$Limit                     0x0800ebc8   Number         0  anon$$obj.o(Region$$Table)
     SystemCoreClock                          0x20000000   Data           4  system_stm32h5xx.o(.data.SystemCoreClock)
     _tx_thread_system_state                  0x20000004   Data           4  tx_thread_initialize.o(.data._tx_thread_system_state)
     uwTickFreq                               0x20000008   Data           1  stm32h5xx_hal.o(.data.uwTickFreq)
@@ -5349,16 +5468,22 @@ Image Symbol Table
     _tx_timer_time_slice                     0x200008e8   Data           4  tx_timer_initialize.o(.bss._tx_timer_time_slice)
     ble_rx_ring                              0x200008ec   Data         260  hcble.o(.bss.ble_rx_ring)
     data_received                            0x200009f0   Data           1  hcble.o(.bss.data_received)
-    handle_GPDMA1_Channel3                   0x200009f4   Data         120  usart.o(.bss.handle_GPDMA1_Channel3)
-    handle_GPDMA1_Channel4                   0x20000a6c   Data         120  usart.o(.bss.handle_GPDMA1_Channel4)
-    handle_GPDMA1_Channel5                   0x20000ae4   Data         120  usart.o(.bss.handle_GPDMA1_Channel5)
-    htim1                                    0x20000b5c   Data          76  stm32h5xx_hal_timebase_tim.o(.bss.htim1)
-    huart1                                   0x20000ba8   Data         148  usart.o(.bss.huart1)
-    huart2                                   0x20000c3c   Data         148  usart.o(.bss.huart2)
-    rx_data                                  0x20000cd0   Data           1  hcble.o(.bss.rx_data)
-    rx_index                                 0x20000cd2   Data           2  hcble.o(.bss.rx_index)
-    uart_dma_rx_buf                          0x20001108   Data          64  hcble.o(.bss.uart_dma_rx_buf)
-    uwTick                                   0x20001148   Data           4  stm32h5xx_hal.o(.bss.uwTick)
+    distance_cm                              0x200009f4   Data           4  ultrasound.o(.bss.distance_cm)
+    handle_GPDMA1_Channel3                   0x200009f8   Data         120  usart.o(.bss.handle_GPDMA1_Channel3)
+    handle_GPDMA1_Channel4                   0x20000a70   Data         120  usart.o(.bss.handle_GPDMA1_Channel4)
+    handle_GPDMA1_Channel5                   0x20000ae8   Data         120  usart.o(.bss.handle_GPDMA1_Channel5)
+    htim1                                    0x20000b60   Data          76  stm32h5xx_hal_timebase_tim.o(.bss.htim1)
+    htim2                                    0x20000bac   Data          76  tim.o(.bss.htim2)
+    huart1                                   0x20000bf8   Data         148  usart.o(.bss.huart1)
+    huart2                                   0x20000c8c   Data         148  usart.o(.bss.huart2)
+    huart5                                   0x20000d20   Data         148  usart.o(.bss.huart5)
+    ic_val1                                  0x20000db4   Data           4  ultrasound.o(.bss.ic_val1)
+    ic_val2                                  0x20000db8   Data           4  ultrasound.o(.bss.ic_val2)
+    is_first_capture                         0x20000dbc   Data           1  ultrasound.o(.bss.is_first_capture)
+    rx_data                                  0x20000dbd   Data           1  hcble.o(.bss.rx_data)
+    rx_index                                 0x20000dbe   Data           2  hcble.o(.bss.rx_index)
+    uart_dma_rx_buf                          0x200011f4   Data          64  hcble.o(.bss.uart_dma_rx_buf)
+    uwTick                                   0x20001234   Data           4  stm32h5xx_hal.o(.bss.uwTick)
 
 
 
@@ -5368,375 +5493,407 @@ Memory Map of the image
 
   Image Entry point : 0x0800024d
 
-  Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000dd20, Max: 0x00200000, ABSOLUTE)
+  Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000ebd8, Max: 0x00200000, ABSOLUTE)
 
-    Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000dd0c, Max: 0x00200000, ABSOLUTE)
+    Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000ebc8, Max: 0x00200000, ABSOLUTE)
 
     Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
 
     0x08000000   0x08000000   0x0000024c   Data   RO            3    RESET               startup_stm32h563xx.o
-    0x0800024c   0x0800024c   0x00000008   Code   RO         2899  * !!!main             c_w.l(__main.o)
-    0x08000254   0x08000254   0x0000005c   Code   RO         3396    !!!scatter          c_w.l(__scatter.o)
-    0x080002b0   0x080002b0   0x0000001a   Code   RO         3400    !!handler_copy      c_w.l(__scatter_copy.o)
+    0x0800024c   0x0800024c   0x00000008   Code   RO         2965  * !!!main             c_w.l(__main.o)
+    0x08000254   0x08000254   0x0000005c   Code   RO         3462    !!!scatter          c_w.l(__scatter.o)
+    0x080002b0   0x080002b0   0x0000001a   Code   RO         3466    !!handler_copy      c_w.l(__scatter_copy.o)
     0x080002ca   0x080002ca   0x00000002   PAD
-    0x080002cc   0x080002cc   0x00000002   Code   RO         3397    !!handler_null      c_w.l(__scatter.o)
+    0x080002cc   0x080002cc   0x00000002   Code   RO         3463    !!handler_null      c_w.l(__scatter.o)
     0x080002ce   0x080002ce   0x00000002   PAD
-    0x080002d0   0x080002d0   0x0000001c   Code   RO         3402    !!handler_zi        c_w.l(__scatter_zi.o)
-    0x080002ec   0x080002ec   0x00000002   Code   RO         3178    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
-    0x080002ee   0x080002ee   0x00000004   Code   RO         3179    .ARM.Collect$$libinit$$00000001  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3182    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3184    .ARM.Collect$$libinit$$00000006  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3187    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3189    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3191    .ARM.Collect$$libinit$$00000010  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3194    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3196    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3198    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3200    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3202    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3204    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3206    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3208    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3210    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3212    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3214    .ARM.Collect$$libinit$$00000027  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3218    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3220    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3222    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000000   Code   RO         3224    .ARM.Collect$$libinit$$00000034  c_w.l(libinit2.o)
-    0x080002f2   0x080002f2   0x00000002   Code   RO         3225    .ARM.Collect$$libinit$$00000035  c_w.l(libinit2.o)
-    0x080002f4   0x080002f4   0x00000002   Code   RO         3339    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3373    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3375    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3378    .ARM.Collect$$libshutdown$$00000007  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3381    .ARM.Collect$$libshutdown$$0000000A  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3383    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000000   Code   RO         3386    .ARM.Collect$$libshutdown$$0000000F  c_w.l(libshutdown2.o)
-    0x080002f6   0x080002f6   0x00000002   Code   RO         3387    .ARM.Collect$$libshutdown$$00000010  c_w.l(libshutdown2.o)
-    0x080002f8   0x080002f8   0x00000000   Code   RO         2927    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
-    0x080002f8   0x080002f8   0x00000000   Code   RO         3061    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
-    0x080002f8   0x080002f8   0x00000006   Code   RO         3073    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
-    0x080002fe   0x080002fe   0x00000000   Code   RO         3063    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
-    0x080002fe   0x080002fe   0x00000004   Code   RO         3064    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
-    0x08000302   0x08000302   0x00000000   Code   RO         3066    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
-    0x08000302   0x08000302   0x00000008   Code   RO         3067    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
-    0x0800030a   0x0800030a   0x00000002   Code   RO         3248    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
-    0x0800030c   0x0800030c   0x00000000   Code   RO         3286    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
-    0x0800030c   0x0800030c   0x00000004   Code   RO         3287    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
-    0x08000310   0x08000310   0x00000006   Code   RO         3288    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
+    0x080002d0   0x080002d0   0x0000001c   Code   RO         3468    !!handler_zi        c_w.l(__scatter_zi.o)
+    0x080002ec   0x080002ec   0x00000002   Code   RO         3244    .ARM.Collect$$libinit$$00000000  c_w.l(libinit.o)
+    0x080002ee   0x080002ee   0x00000004   Code   RO         3245    .ARM.Collect$$libinit$$00000001  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3248    .ARM.Collect$$libinit$$00000004  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3250    .ARM.Collect$$libinit$$00000006  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3253    .ARM.Collect$$libinit$$0000000C  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3255    .ARM.Collect$$libinit$$0000000E  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3257    .ARM.Collect$$libinit$$00000010  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3260    .ARM.Collect$$libinit$$00000013  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3262    .ARM.Collect$$libinit$$00000015  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3264    .ARM.Collect$$libinit$$00000017  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3266    .ARM.Collect$$libinit$$00000019  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3268    .ARM.Collect$$libinit$$0000001B  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3270    .ARM.Collect$$libinit$$0000001D  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3272    .ARM.Collect$$libinit$$0000001F  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3274    .ARM.Collect$$libinit$$00000021  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3276    .ARM.Collect$$libinit$$00000023  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3278    .ARM.Collect$$libinit$$00000025  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3280    .ARM.Collect$$libinit$$00000027  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3284    .ARM.Collect$$libinit$$0000002E  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3286    .ARM.Collect$$libinit$$00000030  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3288    .ARM.Collect$$libinit$$00000032  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000000   Code   RO         3290    .ARM.Collect$$libinit$$00000034  c_w.l(libinit2.o)
+    0x080002f2   0x080002f2   0x00000002   Code   RO         3291    .ARM.Collect$$libinit$$00000035  c_w.l(libinit2.o)
+    0x080002f4   0x080002f4   0x00000002   Code   RO         3405    .ARM.Collect$$libshutdown$$00000000  c_w.l(libshutdown.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3439    .ARM.Collect$$libshutdown$$00000002  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3441    .ARM.Collect$$libshutdown$$00000004  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3444    .ARM.Collect$$libshutdown$$00000007  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3447    .ARM.Collect$$libshutdown$$0000000A  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3449    .ARM.Collect$$libshutdown$$0000000C  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000000   Code   RO         3452    .ARM.Collect$$libshutdown$$0000000F  c_w.l(libshutdown2.o)
+    0x080002f6   0x080002f6   0x00000002   Code   RO         3453    .ARM.Collect$$libshutdown$$00000010  c_w.l(libshutdown2.o)
+    0x080002f8   0x080002f8   0x00000000   Code   RO         2993    .ARM.Collect$$rtentry$$00000000  c_w.l(__rtentry.o)
+    0x080002f8   0x080002f8   0x00000000   Code   RO         3127    .ARM.Collect$$rtentry$$00000002  c_w.l(__rtentry2.o)
+    0x080002f8   0x080002f8   0x00000006   Code   RO         3139    .ARM.Collect$$rtentry$$00000004  c_w.l(__rtentry4.o)
+    0x080002fe   0x080002fe   0x00000000   Code   RO         3129    .ARM.Collect$$rtentry$$00000009  c_w.l(__rtentry2.o)
+    0x080002fe   0x080002fe   0x00000004   Code   RO         3130    .ARM.Collect$$rtentry$$0000000A  c_w.l(__rtentry2.o)
+    0x08000302   0x08000302   0x00000000   Code   RO         3132    .ARM.Collect$$rtentry$$0000000C  c_w.l(__rtentry2.o)
+    0x08000302   0x08000302   0x00000008   Code   RO         3133    .ARM.Collect$$rtentry$$0000000D  c_w.l(__rtentry2.o)
+    0x0800030a   0x0800030a   0x00000002   Code   RO         3314    .ARM.Collect$$rtexit$$00000000  c_w.l(rtexit.o)
+    0x0800030c   0x0800030c   0x00000000   Code   RO         3352    .ARM.Collect$$rtexit$$00000002  c_w.l(rtexit2.o)
+    0x0800030c   0x0800030c   0x00000004   Code   RO         3353    .ARM.Collect$$rtexit$$00000003  c_w.l(rtexit2.o)
+    0x08000310   0x08000310   0x00000006   Code   RO         3354    .ARM.Collect$$rtexit$$00000004  c_w.l(rtexit2.o)
     0x08000316   0x08000316   0x00000002   PAD
     0x08000318   0x08000318   0x00000044   Code   RO            4    .text               startup_stm32h563xx.o
     0x0800035c   0x0800035c   0x00000078   Code   RO           26    .text               tx_initialize_low_level.o
-    0x080003d4   0x080003d4   0x000000d0   Code   RO         1593    .text               tx_thread_schedule.o
-    0x080004a4   0x080004a4   0x00000040   Code   RO         1598    .text               tx_thread_stack_build.o
-    0x080004e4   0x080004e4   0x000000b8   Code   RO         1608    .text               tx_timer_interrupt.o
-    0x0800059c   0x0800059c   0x000000f0   Code   RO         2879    .text               c_w.l(lludivv7m.o)
-    0x0800068c   0x0800068c   0x0000008a   Code   RO         2889    .text               c_w.l(rt_memcpy_v6.o)
-    0x08000716   0x08000716   0x00000010   Code   RO         2891    .text               c_w.l(aeabi_memset.o)
-    0x08000726   0x08000726   0x00000044   Code   RO         2893    .text               c_w.l(rt_memclr.o)
-    0x0800076a   0x0800076a   0x0000004e   Code   RO         2895    .text               c_w.l(rt_memclr_w.o)
-    0x080007b8   0x080007b8   0x00000006   Code   RO         2897    .text               c_w.l(heapauxi.o)
-    0x080007be   0x080007be   0x00000064   Code   RO         3043    .text               c_w.l(rt_memcpy_w.o)
+    0x080003d4   0x080003d4   0x000000d0   Code   RO         1614    .text               tx_thread_schedule.o
+    0x080004a4   0x080004a4   0x00000040   Code   RO         1619    .text               tx_thread_stack_build.o
+    0x080004e4   0x080004e4   0x000000b8   Code   RO         1629    .text               tx_timer_interrupt.o
+    0x0800059c   0x0800059c   0x000000f0   Code   RO         2945    .text               c_w.l(lludivv7m.o)
+    0x0800068c   0x0800068c   0x0000008a   Code   RO         2955    .text               c_w.l(rt_memcpy_v6.o)
+    0x08000716   0x08000716   0x00000010   Code   RO         2957    .text               c_w.l(aeabi_memset.o)
+    0x08000726   0x08000726   0x00000044   Code   RO         2959    .text               c_w.l(rt_memclr.o)
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     0x08001546   0x08001546   0x00000002   PAD
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     0x080015a6   0x080015a6   0x00000002   PAD
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     0x080019fa   0x080019fa   0x00000002   PAD
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     0x08001a8e   0x08001a8e   0x00000002   PAD
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     0x08001fae   0x08001fae   0x00000002   PAD
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     0x08002152   0x08002152   0x00000002   PAD
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     0x0800221e   0x0800221e   0x00000002   PAD
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+    0x0800b0fe   0x0800b0fe   0x00000002   PAD
+    0x0800b100   0x0800b100   0x0000008e   Code   RO           78    .text.MX_USART2_UART_Init  usart.o
+    0x0800b18e   0x0800b18e   0x00000002   PAD
+    0x0800b190   0x0800b190   0x00000004   Code   RO          105    .text.MemManage_Handler  stm32h5xx_it.o
+    0x0800b194   0x0800b194   0x00000004   Code   RO          101    .text.NMI_Handler   stm32h5xx_it.o
+    0x0800b198   0x0800b198   0x0000006c   Code   RO          575    .text.NVIC_EncodePriority  stm32h5xx_hal_cortex.o
+    0x0800b204   0x0800b204   0x0000016c   Code   RO          689    .text.RCCEx_PLL2_Config  stm32h5xx_hal_rcc_ex.o
+    0x0800b370   0x0800b370   0x0000016c   Code   RO          691    .text.RCCEx_PLL3_Config  stm32h5xx_hal_rcc_ex.o
+    0x0800b4dc   0x0800b4dc   0x000000c6   Code   RO           13    .text.SystemClock_Config  main.o
+    0x0800b5a2   0x0800b5a2   0x00000002   PAD
+    0x0800b5a4   0x0800b5a4   0x00000136   Code   RO         1539    .text.SystemInit    system_stm32h5xx.o
+    0x0800b6da   0x0800b6da   0x00000002   PAD
+    0x0800b6dc   0x0800b6dc   0x00000010   Code   RO          119    .text.TIM1_UP_IRQHandler  stm32h5xx_it.o
+    0x0800b6ec   0x0800b6ec   0x00000010   Code   RO          121    .text.TIM2_IRQHandler  stm32h5xx_it.o
+    0x0800b6fc   0x0800b6fc   0x0000035a   Code   RO          173    .text.TIM_Base_SetConfig  stm32h5xx_hal_tim.o
+    0x0800ba56   0x0800ba56   0x00000002   PAD
+    0x0800ba58   0x0800ba58   0x00000034   Code   RO          365    .text.TIM_ETR_SetConfig  stm32h5xx_hal_tim.o
+    0x0800ba8c   0x0800ba8c   0x00000030   Code   RO          371    .text.TIM_ITRx_SetConfig  stm32h5xx_hal_tim.o
+    0x0800babc   0x0800babc   0x00000050   Code   RO          369    .text.TIM_TI1_ConfigInputStage  stm32h5xx_hal_tim.o
+    0x0800bb0c   0x0800bb0c   0x000001b8   Code   RO          333    .text.TIM_TI1_SetConfig  stm32h5xx_hal_tim.o
+    0x0800bcc4   0x0800bcc4   0x00000052   Code   RO          373    .text.TIM_TI2_ConfigInputStage  stm32h5xx_hal_tim.o
+    0x0800bd16   0x0800bd16   0x00000002   PAD
+    0x0800bd18   0x0800bd18   0x0000006c   Code   RO          335    .text.TIM_TI2_SetConfig  stm32h5xx_hal_tim.o
+    0x0800bd84   0x0800bd84   0x0000006a   Code   RO          337    .text.TIM_TI3_SetConfig  stm32h5xx_hal_tim.o
+    0x0800bdee   0x0800bdee   0x00000002   PAD
+    0x0800bdf0   0x0800bdf0   0x0000006c   Code   RO          339    .text.TIM_TI4_SetConfig  stm32h5xx_hal_tim.o
+    0x0800be5c   0x0800be5c   0x00000010   Code   RO          127    .text.UART5_IRQHandler  stm32h5xx_it.o
+    0x0800be6c   0x0800be6c   0x0000008a   Code   RO         1514    .text.UARTEx_SetNbDataToProcess  stm32h5xx_hal_uart_ex.o
+    0x0800bef6   0x0800bef6   0x00000002   PAD
+    0x0800bef8   0x0800bef8   0x00000148   Code   RO         1350    .text.UART_AdvFeatureConfig  stm32h5xx_hal_uart.o
+    0x0800c040   0x0800c040   0x00000146   Code   RO         1354    .text.UART_CheckIdleState  stm32h5xx_hal_uart.o
+    0x0800c186   0x0800c186   0x00000002   PAD
+    0x0800c188   0x0800c188   0x0000001e   Code   RO         1436    .text.UART_DMAAbortOnError  stm32h5xx_hal_uart.o
+    0x0800c1a6   0x0800c1a6   0x00000002   PAD
+    0x0800c1a8   0x0800c1a8   0x00000080   Code   RO         1392    .text.UART_DMAError  stm32h5xx_hal_uart.o
+    0x0800c228   0x0800c228   0x00000104   Code   RO         1482    .text.UART_DMAReceiveCplt  stm32h5xx_hal_uart.o
+    0x0800c32c   0x0800c32c   0x0000006e   Code   RO         1484    .text.UART_DMARxHalfCplt  stm32h5xx_hal_uart.o
+    0x0800c39a   0x0800c39a   0x00000002   PAD
+    0x0800c39c   0x0800c39c   0x0000009e   Code   RO         1406    .text.UART_EndRxTransfer  stm32h5xx_hal_uart.o
+    0x0800c43a   0x0800c43a   0x00000002   PAD
+    0x0800c43c   0x0800c43c   0x00000044   Code   RO         1442    .text.UART_EndTransmit_IT  stm32h5xx_hal_uart.o
+    0x0800c480   0x0800c480   0x0000005c   Code   RO         1404    .text.UART_EndTxTransfer  stm32h5xx_hal_uart.o
+    0x0800c4dc   0x0800c4dc   0x00000196   Code   RO         1478    .text.UART_RxISR_16BIT  stm32h5xx_hal_uart.o
+    0x0800c672   0x0800c672   0x00000002   PAD
+    0x0800c674   0x0800c674   0x0000031a   Code   RO         1474    .text.UART_RxISR_16BIT_FIFOEN  stm32h5xx_hal_uart.o
+    0x0800c98e   0x0800c98e   0x00000002   PAD
+    0x0800c990   0x0800c990   0x00000192   Code   RO         1480    .text.UART_RxISR_8BIT  stm32h5xx_hal_uart.o
+    0x0800cb22   0x0800cb22   0x00000002   PAD
+    0x0800cb24   0x0800cb24   0x00000316   Code   RO         1476    .text.UART_RxISR_8BIT_FIFOEN  stm32h5xx_hal_uart.o
+    0x0800ce3a   0x0800ce3a   0x00000002   PAD
+    0x0800ce3c   0x0800ce3c   0x00000418   Code   RO         1352    .text.UART_SetConfig  stm32h5xx_hal_uart.o
+    0x0800d254   0x0800d254   0x000001d8   Code   RO         1396    .text.UART_Start_Receive_DMA  stm32h5xx_hal_uart.o
+    0x0800d42c   0x0800d42c   0x00000222   Code   RO         1384    .text.UART_Start_Receive_IT  stm32h5xx_hal_uart.o
+    0x0800d64e   0x0800d64e   0x00000002   PAD
+    0x0800d650   0x0800d650   0x0000010c   Code   RO         1368    .text.UART_WaitOnFlagUntilTimeout  stm32h5xx_hal_uart.o
+    0x0800d75c   0x0800d75c   0x000000a0   Code   RO          123    .text.USART1_IRQHandler  stm32h5xx_it.o
+    0x0800d7fc   0x0800d7fc   0x00000010   Code   RO          125    .text.USART2_IRQHandler  stm32h5xx_it.o
+    0x0800d80c   0x0800d80c   0x00000004   Code   RO          109    .text.UsageFault_Handler  stm32h5xx_it.o
+    0x0800d810   0x0800d810   0x00000030   Code   RO          579    .text.__NVIC_EnableIRQ  stm32h5xx_hal_cortex.o
+    0x0800d840   0x0800d840   0x00000010   Code   RO          571    .text.__NVIC_GetPriorityGrouping  stm32h5xx_hal_cortex.o
+    0x0800d850   0x0800d850   0x00000042   Code   RO          573    .text.__NVIC_SetPriority  stm32h5xx_hal_cortex.o
+    0x0800d892   0x0800d892   0x00000002   PAD
+    0x0800d894   0x0800d894   0x0000003c   Code   RO          567    .text.__NVIC_SetPriorityGrouping  stm32h5xx_hal_cortex.o
+    0x0800d8d0   0x0800d8d0   0x00000130   Code   RO         1732    .text._tx_byte_pool_create  tx_byte_pool_create.o
+    0x0800da00   0x0800da00   0x00000086   Code   RO         1553    .text._tx_initialize_high_level  tx_initialize_high_level.o
+    0x0800da86   0x0800da86   0x00000002   PAD
+    0x0800da88   0x0800da88   0x00000068   Code   RO         1574    .text._tx_initialize_kernel_enter  tx_initialize_kernel_enter.o
+    0x0800daf0   0x0800daf0   0x0000021a   Code   RO         2060    .text._tx_thread_create  tx_thread_create.o
+    0x0800dd0a   0x0800dd0a   0x00000002   PAD
+    0x0800dd0c   0x0800dd0c   0x0000007e   Code   RO         2100    .text._tx_thread_initialize  tx_thread_initialize.o
+    0x0800dd8a   0x0800dd8a   0x00000002   PAD
+    0x0800dd8c   0x0800dd8c   0x00000094   Code   RO         2163    .text._tx_thread_shell_entry  tx_thread_shell_entry.o
+    0x0800de20   0x0800de20   0x00000070   Code   RO         2195    .text._tx_thread_system_preempt_check  tx_thread_system_preempt_check.o
+    0x0800de90   0x0800de90   0x00000248   Code   RO         1651    .text._tx_thread_system_resume  tx_thread_system_resume.o
+    0x0800e0d8   0x0800e0d8   0x00000280   Code   RO         2203    .text._tx_thread_system_suspend  tx_thread_system_suspend.o
+    0x0800e358   0x0800e358   0x000000a2   Code   RO         2219    .text._tx_thread_time_slice  tx_thread_time_slice.o
+    0x0800e3fa   0x0800e3fa   0x00000002   PAD
+    0x0800e3fc   0x0800e3fc   0x00000072   Code   RO         2235    .text._tx_thread_timeout  tx_thread_timeout.o
+    0x0800e46e   0x0800e46e   0x00000002   PAD
+    0x0800e470   0x0800e470   0x0000003c   Code   RO         2739    .text._tx_timer_expiration_process  tx_timer_expiration_process.o
+    0x0800e4ac   0x0800e4ac   0x0000011e   Code   RO         2755    .text._tx_timer_initialize  tx_timer_initialize.o
+    0x0800e5ca   0x0800e5ca   0x00000002   PAD
+    0x0800e5cc   0x0800e5cc   0x000000d4   Code   RO         2780    .text._tx_timer_system_activate  tx_timer_system_activate.o
+    0x0800e6a0   0x0800e6a0   0x00000070   Code   RO         2788    .text._tx_timer_system_deactivate  tx_timer_system_deactivate.o
+    0x0800e710   0x0800e710   0x00000218   Code   RO         2796    .text._tx_timer_thread_entry  tx_timer_thread_entry.o
+    0x0800e928   0x0800e928   0x00000174   Code   RO         2323    .text._txe_byte_pool_create  txe_byte_pool_create.o
+    0x0800ea9c   0x0800ea9c   0x00000030   Code   RO           11    .text.main          main.o
+    0x0800eacc   0x0800eacc   0x00000058   Code   RO          158    .text.tx_application_define  app_azure_rtos.o
+    0x0800eb24   0x0800eb24   0x0000001a   Code   RO         3339    x$fpl$fpinit        fz_wm.l(fpinit.o)
+    0x0800eb3e   0x0800eb3e   0x00000010   Data   RO         1544    .rodata.AHBPrescTable  system_stm32h5xx.o
+    0x0800eb4e   0x0800eb4e   0x00000008   Data   RO         1545    .rodata.APBPrescTable  system_stm32h5xx.o
+    0x0800eb56   0x0800eb56   0x00000008   Data   RO         1531    .rodata.UARTEx_SetNbDataToProcess.denominator  stm32h5xx_hal_uart_ex.o
+    0x0800eb5e   0x0800eb5e   0x00000008   Data   RO         1530    .rodata.UARTEx_SetNbDataToProcess.numerator  stm32h5xx_hal_uart_ex.o
+    0x0800eb66   0x0800eb66   0x00000018   Data   RO         1486    .rodata.UARTPrescTable  stm32h5xx_hal_uart.o
+    0x0800eb7e   0x0800eb7e   0x00000013   Data   RO          161    .rodata.str1.1      app_azure_rtos.o
+    0x0800eb91   0x0800eb91   0x00000014   Data   RO         2771    .rodata.str1.1      tx_timer_initialize.o
+    0x0800eba5   0x0800eba5   0x00000003   PAD
+    0x0800eba8   0x0800eba8   0x00000020   Data   RO         3461    Region$$Table       anon$$obj.o
 
 
-    Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x0800dd10, Size: 0x00001750, Max: 0x000a0000, ABSOLUTE)
+    Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x0800ebc8, Size: 0x00001838, Max: 0x000a0000, ABSOLUTE)
 
     Exec Addr    Load Addr    Size         Type   Attr      Idx    E Section Name        Object
 
-    0x20000000   0x0800dd10   0x00000004   Data   RW         1522    .data.SystemCoreClock  system_stm32h5xx.o
-    0x20000004   0x0800dd14   0x00000004   Data   RW         2082    .data._tx_thread_system_state  tx_thread_initialize.o
-    0x20000008   0x0800dd18   0x00000001   Data   RW         1287    .data.uwTickFreq    stm32h5xx_hal.o
-    0x20000009   0x0800dd19   0x00000003   PAD
-    0x2000000c   0x0800dd1c   0x00000004   Data   RW         1286    .data.uwTickPrio    stm32h5xx_hal.o
-    0x20000010        -       0x00000060   Zero   RW         3120    .bss                c_w.l(libspace.o)
-    0x20000070        -       0x00000079   Zero   RW         2869    .bss.GPS            gps.o
-    0x200000e9        -       0x000000c8   Zero   RW         2868    .bss.GPS_DMA_RX_BUF  gps.o
-    0x200001b1        -       0x00000080   Zero   RW         2845    .bss.HC_Recevie     hcble.o
-    0x20000231   0x0800dd20   0x00000003   PAD
-    0x20000234        -       0x00000018   Zero   RW           75    .bss.List_GPDMA1_Channel3  usart.o
-    0x2000024c        -       0x00000018   Zero   RW           71    .bss.List_GPDMA1_Channel5  usart.o
-    0x20000264        -       0x00000024   Zero   RW           74    .bss.Node_GPDMA1_Channel3  usart.o
-    0x20000288        -       0x00000024   Zero   RW           70    .bss.Node_GPDMA1_Channel5  usart.o
-    0x200002ac        -       0x00000004   Zero   RW         1541    .bss._tx_block_pool_created_count  tx_initialize_high_level.o
-    0x200002b0        -       0x00000004   Zero   RW         1540    .bss._tx_block_pool_created_ptr  tx_initialize_high_level.o
-    0x200002b4        -       0x00000004   Zero   RW         2093    .bss._tx_build_options  tx_thread_initialize.o
-    0x200002b8        -       0x00000004   Zero   RW         1543    .bss._tx_byte_pool_created_count  tx_initialize_high_level.o
-    0x200002bc        -       0x00000004   Zero   RW         1542    .bss._tx_byte_pool_created_ptr  tx_initialize_high_level.o
-    0x200002c0        -       0x00000004   Zero   RW         1539    .bss._tx_event_flags_created_count  tx_initialize_high_level.o
-    0x200002c4        -       0x00000004   Zero   RW         1538    .bss._tx_event_flags_created_ptr  tx_initialize_high_level.o
-    0x200002c8        -       0x00000004   Zero   RW         1546    .bss._tx_initialize_unused_memory  tx_initialize_high_level.o
-    0x200002cc        -       0x00000004   Zero   RW         1545    .bss._tx_mutex_created_count  tx_initialize_high_level.o
-    0x200002d0        -       0x00000004   Zero   RW         1544    .bss._tx_mutex_created_ptr  tx_initialize_high_level.o
-    0x200002d4        -       0x00000004   Zero   RW         1537    .bss._tx_queue_created_count  tx_initialize_high_level.o
-    0x200002d8        -       0x00000004   Zero   RW         1536    .bss._tx_queue_created_ptr  tx_initialize_high_level.o
-    0x200002dc        -       0x00000004   Zero   RW         1535    .bss._tx_semaphore_created_count  tx_initialize_high_level.o
-    0x200002e0        -       0x00000004   Zero   RW         1534    .bss._tx_semaphore_created_ptr  tx_initialize_high_level.o
-    0x200002e4        -       0x00000004   Zero   RW         2090    .bss._tx_thread_created_count  tx_thread_initialize.o
-    0x200002e8        -       0x00000004   Zero   RW         2089    .bss._tx_thread_created_ptr  tx_thread_initialize.o
-    0x200002ec        -       0x00000004   Zero   RW         2084    .bss._tx_thread_current_ptr  tx_thread_initialize.o
-    0x200002f0        -       0x00000004   Zero   RW         2085    .bss._tx_thread_execute_ptr  tx_thread_initialize.o
-    0x200002f4        -       0x00000004   Zero   RW         2087    .bss._tx_thread_highest_priority  tx_thread_initialize.o
-    0x200002f8        -       0x00000004   Zero   RW         2092    .bss._tx_thread_mutex_release  tx_thread_initialize.o
-    0x200002fc        -       0x00000004   Zero   RW         2091    .bss._tx_thread_preempt_disable  tx_thread_initialize.o
-    0x20000300        -       0x00000080   Zero   RW         2088    .bss._tx_thread_priority_list  tx_thread_initialize.o
-    0x20000380        -       0x00000004   Zero   RW         2086    .bss._tx_thread_priority_maps  tx_thread_initialize.o
-    0x20000384        -       0x00000004   Zero   RW         2094    .bss._tx_thread_system_stack_ptr  tx_thread_initialize.o
-    0x20000388        -       0x00000004   Zero   RW         2752    .bss._tx_timer_created_count  tx_timer_initialize.o
-    0x2000038c        -       0x00000004   Zero   RW         2751    .bss._tx_timer_created_ptr  tx_timer_initialize.o
-    0x20000390        -       0x00000004   Zero   RW         2743    .bss._tx_timer_current_ptr  tx_timer_initialize.o
-    0x20000394        -       0x00000004   Zero   RW         2739    .bss._tx_timer_expired  tx_timer_initialize.o
-    0x20000398        -       0x00000004   Zero   RW         2738    .bss._tx_timer_expired_time_slice  tx_timer_initialize.o
-    0x2000039c        -       0x00000004   Zero   RW         2740    .bss._tx_timer_expired_timer_ptr  tx_timer_initialize.o
-    0x200003a0        -       0x00000080   Zero   RW         2741    .bss._tx_timer_list  tx_timer_initialize.o
-    0x20000420        -       0x00000004   Zero   RW         2744    .bss._tx_timer_list_end  tx_timer_initialize.o
-    0x20000424        -       0x00000004   Zero   RW         2742    .bss._tx_timer_list_start  tx_timer_initialize.o
-    0x20000428        -       0x00000004   Zero   RW         2748    .bss._tx_timer_priority  tx_timer_initialize.o
-    0x2000042c        -       0x00000004   Zero   RW         2747    .bss._tx_timer_stack_size  tx_timer_initialize.o
-    0x20000430        -       0x00000004   Zero   RW         2746    .bss._tx_timer_stack_start  tx_timer_initialize.o
-    0x20000434        -       0x00000004   Zero   RW         2736    .bss._tx_timer_system_clock  tx_timer_initialize.o
-    0x20000438        -       0x000000b0   Zero   RW         2749    .bss._tx_timer_thread  tx_timer_initialize.o
-    0x200004e8        -       0x00000400   Zero   RW         2745    .bss._tx_timer_thread_stack_area  tx_timer_initialize.o
-    0x200008e8        -       0x00000004   Zero   RW         2737    .bss._tx_timer_time_slice  tx_timer_initialize.o
-    0x200008ec        -       0x00000104   Zero   RW         2841    .bss.ble_rx_ring    hcble.o
-    0x200009f0        -       0x00000001   Zero   RW         2840    .bss.data_received  hcble.o
-    0x200009f1   0x0800dd20   0x00000003   PAD
-    0x200009f4        -       0x00000078   Zero   RW           76    .bss.handle_GPDMA1_Channel3  usart.o
-    0x20000a6c        -       0x00000078   Zero   RW           73    .bss.handle_GPDMA1_Channel4  usart.o
-    0x20000ae4        -       0x00000078   Zero   RW           72    .bss.handle_GPDMA1_Channel5  usart.o
-    0x20000b5c        -       0x0000004c   Zero   RW          129    .bss.htim1          stm32h5xx_hal_timebase_tim.o
-    0x20000ba8        -       0x00000094   Zero   RW           68    .bss.huart1         usart.o
-    0x20000c3c        -       0x00000094   Zero   RW           69    .bss.huart2         usart.o
-    0x20000cd0        -       0x00000001   Zero   RW         2844    .bss.rx_data        hcble.o
-    0x20000cd1   0x0800dd20   0x00000001   PAD
-    0x20000cd2        -       0x00000002   Zero   RW         2839    .bss.rx_index       hcble.o
-    0x20000cd4        -       0x00000034   Zero   RW          139    .bss.tx_app_byte_pool  app_azure_rtos.o
-    0x20000d08        -       0x00000400   Zero   RW          141    .bss.tx_byte_pool_buffer  app_azure_rtos.o
-    0x20001108        -       0x00000040   Zero   RW         2842    .bss.uart_dma_rx_buf  hcble.o
-    0x20001148        -       0x00000004   Zero   RW         1288    .bss.uwTick         stm32h5xx_hal.o
-    0x2000114c   0x0800dd20   0x00000004   PAD
-    0x20001150        -       0x00000200   Zero   RW            2    HEAP                startup_stm32h563xx.o
-    0x20001350        -       0x00000400   Zero   RW            1    STACK               startup_stm32h563xx.o
+    0x20000000   0x0800ebc8   0x00000004   Data   RW         1543    .data.SystemCoreClock  system_stm32h5xx.o
+    0x20000004   0x0800ebcc   0x00000004   Data   RW         2103    .data._tx_thread_system_state  tx_thread_initialize.o
+    0x20000008   0x0800ebd0   0x00000001   Data   RW         1308    .data.uwTickFreq    stm32h5xx_hal.o
+    0x20000009   0x0800ebd1   0x00000003   PAD
+    0x2000000c   0x0800ebd4   0x00000004   Data   RW         1307    .data.uwTickPrio    stm32h5xx_hal.o
+    0x20000010        -       0x00000060   Zero   RW         3186    .bss                c_w.l(libspace.o)
+    0x20000070        -       0x00000079   Zero   RW         2890    .bss.GPS            gps.o
+    0x200000e9        -       0x000000c8   Zero   RW         2889    .bss.GPS_DMA_RX_BUF  gps.o
+    0x200001b1        -       0x00000080   Zero   RW         2866    .bss.HC_Recevie     hcble.o
+    0x20000231   0x0800ebd8   0x00000003   PAD
+    0x20000234        -       0x00000018   Zero   RW           92    .bss.List_GPDMA1_Channel3  usart.o
+    0x2000024c        -       0x00000018   Zero   RW           88    .bss.List_GPDMA1_Channel5  usart.o
+    0x20000264        -       0x00000024   Zero   RW           91    .bss.Node_GPDMA1_Channel3  usart.o
+    0x20000288        -       0x00000024   Zero   RW           87    .bss.Node_GPDMA1_Channel5  usart.o
+    0x200002ac        -       0x00000004   Zero   RW         1562    .bss._tx_block_pool_created_count  tx_initialize_high_level.o
+    0x200002b0        -       0x00000004   Zero   RW         1561    .bss._tx_block_pool_created_ptr  tx_initialize_high_level.o
+    0x200002b4        -       0x00000004   Zero   RW         2114    .bss._tx_build_options  tx_thread_initialize.o
+    0x200002b8        -       0x00000004   Zero   RW         1564    .bss._tx_byte_pool_created_count  tx_initialize_high_level.o
+    0x200002bc        -       0x00000004   Zero   RW         1563    .bss._tx_byte_pool_created_ptr  tx_initialize_high_level.o
+    0x200002c0        -       0x00000004   Zero   RW         1560    .bss._tx_event_flags_created_count  tx_initialize_high_level.o
+    0x200002c4        -       0x00000004   Zero   RW         1559    .bss._tx_event_flags_created_ptr  tx_initialize_high_level.o
+    0x200002c8        -       0x00000004   Zero   RW         1567    .bss._tx_initialize_unused_memory  tx_initialize_high_level.o
+    0x200002cc        -       0x00000004   Zero   RW         1566    .bss._tx_mutex_created_count  tx_initialize_high_level.o
+    0x200002d0        -       0x00000004   Zero   RW         1565    .bss._tx_mutex_created_ptr  tx_initialize_high_level.o
+    0x200002d4        -       0x00000004   Zero   RW         1558    .bss._tx_queue_created_count  tx_initialize_high_level.o
+    0x200002d8        -       0x00000004   Zero   RW         1557    .bss._tx_queue_created_ptr  tx_initialize_high_level.o
+    0x200002dc        -       0x00000004   Zero   RW         1556    .bss._tx_semaphore_created_count  tx_initialize_high_level.o
+    0x200002e0        -       0x00000004   Zero   RW         1555    .bss._tx_semaphore_created_ptr  tx_initialize_high_level.o
+    0x200002e4        -       0x00000004   Zero   RW         2111    .bss._tx_thread_created_count  tx_thread_initialize.o
+    0x200002e8        -       0x00000004   Zero   RW         2110    .bss._tx_thread_created_ptr  tx_thread_initialize.o
+    0x200002ec        -       0x00000004   Zero   RW         2105    .bss._tx_thread_current_ptr  tx_thread_initialize.o
+    0x200002f0        -       0x00000004   Zero   RW         2106    .bss._tx_thread_execute_ptr  tx_thread_initialize.o
+    0x200002f4        -       0x00000004   Zero   RW         2108    .bss._tx_thread_highest_priority  tx_thread_initialize.o
+    0x200002f8        -       0x00000004   Zero   RW         2113    .bss._tx_thread_mutex_release  tx_thread_initialize.o
+    0x200002fc        -       0x00000004   Zero   RW         2112    .bss._tx_thread_preempt_disable  tx_thread_initialize.o
+    0x20000300        -       0x00000080   Zero   RW         2109    .bss._tx_thread_priority_list  tx_thread_initialize.o
+    0x20000380        -       0x00000004   Zero   RW         2107    .bss._tx_thread_priority_maps  tx_thread_initialize.o
+    0x20000384        -       0x00000004   Zero   RW         2115    .bss._tx_thread_system_stack_ptr  tx_thread_initialize.o
+    0x20000388        -       0x00000004   Zero   RW         2773    .bss._tx_timer_created_count  tx_timer_initialize.o
+    0x2000038c        -       0x00000004   Zero   RW         2772    .bss._tx_timer_created_ptr  tx_timer_initialize.o
+    0x20000390        -       0x00000004   Zero   RW         2764    .bss._tx_timer_current_ptr  tx_timer_initialize.o
+    0x20000394        -       0x00000004   Zero   RW         2760    .bss._tx_timer_expired  tx_timer_initialize.o
+    0x20000398        -       0x00000004   Zero   RW         2759    .bss._tx_timer_expired_time_slice  tx_timer_initialize.o
+    0x2000039c        -       0x00000004   Zero   RW         2761    .bss._tx_timer_expired_timer_ptr  tx_timer_initialize.o
+    0x200003a0        -       0x00000080   Zero   RW         2762    .bss._tx_timer_list  tx_timer_initialize.o
+    0x20000420        -       0x00000004   Zero   RW         2765    .bss._tx_timer_list_end  tx_timer_initialize.o
+    0x20000424        -       0x00000004   Zero   RW         2763    .bss._tx_timer_list_start  tx_timer_initialize.o
+    0x20000428        -       0x00000004   Zero   RW         2769    .bss._tx_timer_priority  tx_timer_initialize.o
+    0x2000042c        -       0x00000004   Zero   RW         2768    .bss._tx_timer_stack_size  tx_timer_initialize.o
+    0x20000430        -       0x00000004   Zero   RW         2767    .bss._tx_timer_stack_start  tx_timer_initialize.o
+    0x20000434        -       0x00000004   Zero   RW         2757    .bss._tx_timer_system_clock  tx_timer_initialize.o
+    0x20000438        -       0x000000b0   Zero   RW         2770    .bss._tx_timer_thread  tx_timer_initialize.o
+    0x200004e8        -       0x00000400   Zero   RW         2766    .bss._tx_timer_thread_stack_area  tx_timer_initialize.o
+    0x200008e8        -       0x00000004   Zero   RW         2758    .bss._tx_timer_time_slice  tx_timer_initialize.o
+    0x200008ec        -       0x00000104   Zero   RW         2862    .bss.ble_rx_ring    hcble.o
+    0x200009f0        -       0x00000001   Zero   RW         2861    .bss.data_received  hcble.o
+    0x200009f1   0x0800ebd8   0x00000003   PAD
+    0x200009f4        -       0x00000004   Zero   RW         2934    .bss.distance_cm    ultrasound.o
+    0x200009f8        -       0x00000078   Zero   RW           93    .bss.handle_GPDMA1_Channel3  usart.o
+    0x20000a70        -       0x00000078   Zero   RW           90    .bss.handle_GPDMA1_Channel4  usart.o
+    0x20000ae8        -       0x00000078   Zero   RW           89    .bss.handle_GPDMA1_Channel5  usart.o
+    0x20000b60        -       0x0000004c   Zero   RW          150    .bss.htim1          stm32h5xx_hal_timebase_tim.o
+    0x20000bac        -       0x0000004c   Zero   RW           66    .bss.htim2          tim.o
+    0x20000bf8        -       0x00000094   Zero   RW           85    .bss.huart1         usart.o
+    0x20000c8c        -       0x00000094   Zero   RW           86    .bss.huart2         usart.o
+    0x20000d20        -       0x00000094   Zero   RW           84    .bss.huart5         usart.o
+    0x20000db4        -       0x00000004   Zero   RW         2931    .bss.ic_val1        ultrasound.o
+    0x20000db8        -       0x00000004   Zero   RW         2932    .bss.ic_val2        ultrasound.o
+    0x20000dbc        -       0x00000001   Zero   RW         2933    .bss.is_first_capture  ultrasound.o
+    0x20000dbd        -       0x00000001   Zero   RW         2865    .bss.rx_data        hcble.o
+    0x20000dbe        -       0x00000002   Zero   RW         2860    .bss.rx_index       hcble.o
+    0x20000dc0        -       0x00000034   Zero   RW          160    .bss.tx_app_byte_pool  app_azure_rtos.o
+    0x20000df4        -       0x00000400   Zero   RW          162    .bss.tx_byte_pool_buffer  app_azure_rtos.o
+    0x200011f4        -       0x00000040   Zero   RW         2863    .bss.uart_dma_rx_buf  hcble.o
+    0x20001234        -       0x00000004   Zero   RW         1309    .bss.uwTick         stm32h5xx_hal.o
+    0x20001238        -       0x00000200   Zero   RW            2    HEAP                startup_stm32h563xx.o
+    0x20001438        -       0x00000400   Zero   RW            1    STACK               startup_stm32h563xx.o
 
 
 ==============================================================================
@@ -5749,26 +5906,27 @@ Image component sizes
         88          0         19          0       1076       4013   app_azure_rtos.o
         22          0          0          0          0        714   app_threadx.o
         94          0          0          0          0       4935   gpdma.o
-        96          0          0          0          0       2221   gpio.o
+       230          0          0          0          0       2948   gpio.o
        112          0          0          0        321       5806   gps.o
        210          0          0          0        456       5911   hcble.o
-       278          0          0          0          0       8401   main.o
+       286          0          0          0          0       8403   main.o
         68         28        588          0       1536        944   startup_stm32h563xx.o
        132          0          0          5          4      13991   stm32h5xx_hal.o
        534          6          0          0          0      13387   stm32h5xx_hal_cortex.o
       4392          0          0          0          0       9291   stm32h5xx_hal_dma.o
       4770          0          0          0          0      24570   stm32h5xx_hal_dma_ex.o
-       746          0          0          0          0       5090   stm32h5xx_hal_gpio.o
+       790          0          0          0          0       5090   stm32h5xx_hal_gpio.o
          2          0          0          0          0        369   stm32h5xx_hal_msp.o
       4718         16          0          0          0      13001   stm32h5xx_hal_rcc.o
      19878        178          0          0          0      29257   stm32h5xx_hal_rcc_ex.o
-      2236          0          0          0          0      39348   stm32h5xx_hal_tim.o
-        56          0          0          0          0      21807   stm32h5xx_hal_tim_ex.o
+      4330         14          0          0          0      39348   stm32h5xx_hal_tim.o
+       586          0          0          0          0      21807   stm32h5xx_hal_tim_ex.o
        206          0          0          0         76       9734   stm32h5xx_hal_timebase_tim.o
       8428          0         24          0          0      26676   stm32h5xx_hal_uart.o
        742          0         16          0          0       9343   stm32h5xx_hal_uart_ex.o
-       262          0          0          0          0       1660   stm32h5xx_it.o
+       294          0          0          0          0       1842   stm32h5xx_it.o
        310          0         24          4          0       6001   system_stm32h5xx.o
+       342          0          0          0         76      10429   tim.o
        304          0          0          0          0       4756   tx_byte_pool_create.o
        134          0          0          0         52       6286   tx_initialize_high_level.o
        104          0          0          0          0        655   tx_initialize_kernel_enter.o
@@ -5790,12 +5948,13 @@ Image component sizes
        112          0          0          0          0       1413   tx_timer_system_deactivate.o
        536          0          0          0          0       4737   tx_timer_thread_entry.o
        372          0          0          0          0       4931   txe_byte_pool_create.o
-      1252          0          0          0        776      13609   usart.o
+       266          0          0          0         13      11043   ultrasound.o
+      1556          0          0          0        924      13968   usart.o
 
     ----------------------------------------------------------------------
-     54868        308        726         16       5856     336422   Object Totals
+     58640        322        726         16       6088     359164   Object Totals
          0          0         32          0          0          0   (incl. Generated)
-       116          0          3          3         11          0   (incl. Padding)
+       134          0          3          3          6          0   (incl. Padding)
 
     ----------------------------------------------------------------------
 
@@ -5850,15 +6009,15 @@ Image component sizes
 
       Code (inc. data)   RO Data    RW Data    ZI Data      Debug   
 
-     55862        324        726         16       5952     336406   Grand Totals
-     55862        324        726         16       5952     336406   ELF Image Totals
-     55862        324        726         16          0          0   ROM Totals
+     59634        338        726         16       6184     359108   Grand Totals
+     59634        338        726         16       6184     359108   ELF Image Totals
+     59634        338        726         16          0          0   ROM Totals
 
 ==============================================================================
 
-    Total RO  Size (Code + RO Data)                56588 (  55.26kB)
-    Total RW  Size (RW Data + ZI Data)              5968 (   5.83kB)
-    Total ROM Size (Code + RO Data + RW Data)      56604 (  55.28kB)
+    Total RO  Size (Code + RO Data)                60360 (  58.95kB)
+    Total RW  Size (RW Data + ZI Data)              6200 (   6.05kB)
+    Total ROM Size (Code + RO Data + RW Data)      60376 (  58.96kB)
 
 ==============================================================================
 
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep b/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep
index 9558bc4..2b20629 100644
--- a/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep
+++ b/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep
@@ -1,7 +1,7 @@
 Dependencies for Project 'AutoGuideStick', Target 'AutoGuideStick': (DO NOT MODIFY !)
 CompilerVersion: 6210000::V6.21::ARMCLANG
-F (startup_stm32h563xx.s)(0x6847C26A)(--target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -masm=auto  -Wa,armasm,--diag_suppress=A1950W -c

-gdwarf-4 -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-Wa,armasm,--pd,"__UVISION_VERSION SETA 539" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"STM32H563xx SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"TX_SINGLE_MODE_NON_SECURE SETA 1"

-o autoguidestick/startup_stm32h563xx.o)
-F (../Core/Src/main.c)(0x6847C268)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/main.o -MD)
+F (startup_stm32h563xx.s)(0x685A710C)(--target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -masm=auto  -Wa,armasm,--diag_suppress=A1950W -c

-gdwarf-4 -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-Wa,armasm,--pd,"__UVISION_VERSION SETA 539" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"STM32H563xx SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"TX_SINGLE_MODE_NON_SECURE SETA 1"

-o autoguidestick/startup_stm32h563xx.o)
+F (../Core/Src/main.c)(0x685A5175)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/main.o -MD)
 I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
 I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
 I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
@@ -37,10 +37,10 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
-I (..\Core\Inc\gpdma.hx.\Core\Inc\memorymap.h5.\Core\Inc\usart.h)(0x00000000)
-I (..\Core\Inc\gpio.h)(0x6840230C)
+I (..\Core\Inc\gpdma.hx.\Core\Inc\memorymap.h5.\Core\Inc\tim.h)(0x00000000)
+I (..\Core\Inc\usart.hx.\Core\Inc\gpio.h)(0x00000000)
 F (../Core/Src/tx_initialize_low_level.S)(0x6840230D)(--target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -masm=auto  -Wa,armasm,--diag_suppress=A1950W -c

-gdwarf-4 -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION=539 -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_SINGLE_MODE_NON_SECURE=1

-o autoguidestick/tx_initialize_low_level.o)
-F (../Core/Src/gpio.c)(0x6847C265)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gpio.o -MD)
+F (../Core/Src/gpio.c)(0x685A7107)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gpio.o -MD)
 I (..\Core\Inc\main.ho.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -72,7 +72,7 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
-F (../Core/Src/gpdma.c)(0x6847C266)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gpdma.o -MD)
+F (../Core/Src/gpdma.c)(0x6847DDF6)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gpdma.o -MD)
 I (..\Core\Inc\main.hc.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -143,7 +143,39 @@ I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
 I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
 I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
 I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
-F (../Core/Src/usart.c)(0x6847C267)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/usart.o -MD)
+F (../Core/Src/tim.c)(0x685A5D5A)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/tim.o -MD)
+I (..\Core\Inc\main.h..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+F (../Core/Src/usart.c)(0x685A5174)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/usart.o -MD)
 I (..\Core\Inc\main.hc.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -175,7 +207,7 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
-F (../Core/Src/stm32h5xx_it.c)(0x6847D555)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_it.o -MD)
+F (../Core/Src/stm32h5xx_it.c)(0x685A5174)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_it.o -MD)
 I (..\Core\Inc\main.h5.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -209,10 +241,14 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
 I (..\Core\Inc\stm32h5xx_it.hr.\fun\headfile.hx.\Core\Inc\memorymap.h)(0x00000000)
 I (..\Core\Inc\usart.hx.\Core\Inc\gpio.hf.\Core\Inc\gpdma.h)(0x00000000)
-I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
-I (D:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x6569B012)
-I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\Core\Inc\tim.h..\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
 I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Shake_Motor.hG.\fun\Ultrasound.h..\fun\Buzzer.h)(0x00000000)
 F (../Core/Src/stm32h5xx_hal_msp.c)(0x6840230E)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_msp.o -MD)
 I (..\Core\Inc\main.h5.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
@@ -411,70 +447,6 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
-F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_dma.o -MD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
-I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
-I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
-I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
-I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
-I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
-F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_dma_ex.o -MD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
-I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
-I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
-I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
-I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
-I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
-I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
-I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
-I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
 F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_rcc.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_rcc.o -MD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
@@ -635,6 +607,70 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_dma.o -MD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_dma_ex.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_dma_ex.o -MD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
 F (../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_pwr.c)(0x683FA4DD)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/stm32h5xx_hal_pwr.o -MD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
@@ -1990,7 +2026,7 @@ I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
 I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
 I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
 I (..\Middlewares\ST\threadx\common\inc\tx_timer.h)(0x683FA4DA)
-F (..\fun\HCBle.c)(0x6847D555)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/hcble.o -MD)
+F (..\fun\HCBle.c)(0x6847DDF6)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/hcble.o -MD)
 I (..\Core\Inc\main.hu.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -2023,13 +2059,17 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
 I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000)
-I (..\Core\Inc\gpdma.ha:\keil5\ARM\ARMCLANG\include\stdio.h)(0x00000000)
-I (D:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x6569B012)
-I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\Core\Inc\gpdma.ha.\Core\Inc\tim.hs.\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
 I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Shake_Motor.hG.\fun\Ultrasound.h..\fun\Buzzer.h)(0x00000000)
 F (..\fun\HCBle.h)(0x6846523B)()
-F (..\fun\headfile.h)(0x6847C360)()
-F (..\fun\gps.c)(0x6847D555)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gps.o -MD)
+F (..\fun\headfile.h)(0x685A65D0)()
+F (..\fun\gps.c)(0x6847DDF6)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/gps.o -MD)
 I (..\Core\Inc\main.h\.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000)
 I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
@@ -2062,8 +2102,141 @@ I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
 I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
 I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000)
-I (..\Core\Inc\gpdma.ha:\keil5\ARM\ARMCLANG\include\stdio.h)(0x00000000)
-I (D:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x6569B012)
-I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\Core\Inc\gpdma.ha.\Core\Inc\tim.hs.\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
 I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
-F (..\fun\gps.h)(0x6847D555)()
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Shake_Motor.hG.\fun\Ultrasound.h..\fun\Buzzer.h)(0x00000000)
+F (..\fun\gps.h)(0x6847DDF6)()
+F (..\fun\Buzzer.c)(0x685A56C5)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/buzzer.o -MD)
+I (..\fun\headfile.h\.\Core\Inc\main.h)(0x00000000)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000)
+I (..\Core\Inc\gpdma.ha.\Core\Inc\tim.hs.\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
+I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Shake_Motor.hG.\fun\Ultrasound.h)(0x00000000)
+F (..\fun\Buzzer.h)(0x685A56C3)()
+F (..\fun\Shake_Motor.c)(0x685A592E)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/shake_motor.o -MD)
+I (..\fun\headfile.hr.\Core\Inc\main.h)(0x00000000)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000)
+I (..\Core\Inc\gpdma.ha.\Core\Inc\tim.hs.\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
+I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Ultrasound.hN.\fun\Buzzer.h)(0x00000000)
+F (..\fun\Shake_Motor.h)(0x685A558A)()
+F (..\fun\Ultrasound.c)(0x685A6A92)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c

-fno-rtti -funsigned-char -fshort-enums -fshort-wchar

-gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun

-I./RTE/_AutoGuideStick

-ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include

-ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include

-D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx

-o autoguidestick/ultrasound.o -MD)
+I (..\fun\headfile.h..\Core\Inc\main.h)(0x00000000)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD)
+I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE)
+I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE)
+I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE)
+I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD)
+I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD)
+I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD)
+I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000)
+I (..\Core\Inc\gpdma.ha.\Core\Inc\tim.hs.\Core\Inc\app_threadx.h)(0x00000000)
+I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA)
+I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9)
+I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000)
+I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012)
+I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012)
+I (..\fun\Shake_Motor.hG.\fun\Buzzer.h)(0x00000000)
+F (..\fun\Ultrasound.h)(0x685A6A87)()
diff --git a/MDK-ARM/AutoGuideStick/buzzer.d b/MDK-ARM/AutoGuideStick/buzzer.d
new file mode 100644
index 0000000..0c7d48c
--- /dev/null
+++ b/MDK-ARM/AutoGuideStick/buzzer.d
@@ -0,0 +1,42 @@
+autoguidestick/buzzer.o: ..\fun\Buzzer.c ..\fun\Buzzer.h \
+  ..\fun\headfile.h ..\Core\Inc\main.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \
+  ..\Core\Inc\stm32h5xx_hal_conf.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \
+  D:\keil5\ARM\ARMCLANG\include\math.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \
+  ..\Drivers\CMSIS\Include\core_cm33.h \
+  D:\keil5\ARM\ARMCLANG\include\stdint.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \
+  D:\keil5\ARM\ARMCLANG\include\stddef.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
+  ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \
+  ..\Core\Inc\gpdma.h ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
+  D:\keil5\ARM\ARMCLANG\include\stdio.h \
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\HCBle.h ..\fun\gps.h \
+  ..\fun\Shake_Motor.h ..\fun\Ultrasound.h
diff --git a/MDK-ARM/AutoGuideStick/buzzer.o b/MDK-ARM/AutoGuideStick/buzzer.o
new file mode 100644
index 0000000..3c67da9
Binary files /dev/null and b/MDK-ARM/AutoGuideStick/buzzer.o differ
diff --git a/MDK-ARM/AutoGuideStick/gpio.o b/MDK-ARM/AutoGuideStick/gpio.o
index 5183b55..102f0ba 100644
Binary files a/MDK-ARM/AutoGuideStick/gpio.o and b/MDK-ARM/AutoGuideStick/gpio.o differ
diff --git a/MDK-ARM/AutoGuideStick/gps.d b/MDK-ARM/AutoGuideStick/gps.d
index 5f3c8d6..ab314c8 100644
--- a/MDK-ARM/AutoGuideStick/gps.d
+++ b/MDK-ARM/AutoGuideStick/gps.d
@@ -31,7 +31,11 @@ autoguidestick/gps.o: ..\fun\gps.c ..\fun\gps.h ..\fun\headfile.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
   ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \
-  ..\Core\Inc\gpdma.h D:\keil5\ARM\ARMCLANG\include\stdio.h \
-  D:\keil5\ARM\ARMCLANG\include\stdlib.h \
-  D:\keil5\ARM\ARMCLANG\include\stdarg.h \
-  D:\keil5\ARM\ARMCLANG\include\string.h ..\fun\HCBle.h
+  ..\Core\Inc\gpdma.h ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
+  D:\keil5\ARM\ARMCLANG\include\stdio.h \
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\HCBle.h \
+  ..\fun\Shake_Motor.h ..\fun\Ultrasound.h ..\fun\Buzzer.h
diff --git a/MDK-ARM/AutoGuideStick/gps.o b/MDK-ARM/AutoGuideStick/gps.o
index 1331f12..38dbc2c 100644
Binary files a/MDK-ARM/AutoGuideStick/gps.o and b/MDK-ARM/AutoGuideStick/gps.o differ
diff --git a/MDK-ARM/AutoGuideStick/hcble.d b/MDK-ARM/AutoGuideStick/hcble.d
index 97001fb..18bd04c 100644
--- a/MDK-ARM/AutoGuideStick/hcble.d
+++ b/MDK-ARM/AutoGuideStick/hcble.d
@@ -31,7 +31,11 @@ autoguidestick/hcble.o: ..\fun\HCBle.c ..\fun\HCBle.h ..\fun\headfile.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
   ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \
-  ..\Core\Inc\gpdma.h D:\keil5\ARM\ARMCLANG\include\stdio.h \
-  D:\keil5\ARM\ARMCLANG\include\stdlib.h \
-  D:\keil5\ARM\ARMCLANG\include\stdarg.h \
-  D:\keil5\ARM\ARMCLANG\include\string.h ..\fun\gps.h
+  ..\Core\Inc\gpdma.h ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
+  D:\keil5\ARM\ARMCLANG\include\stdio.h \
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\gps.h \
+  ..\fun\Shake_Motor.h ..\fun\Ultrasound.h ..\fun\Buzzer.h
diff --git a/MDK-ARM/AutoGuideStick/main.d b/MDK-ARM/AutoGuideStick/main.d
index 78f0683..1ae755d 100644
--- a/MDK-ARM/AutoGuideStick/main.d
+++ b/MDK-ARM/AutoGuideStick/main.d
@@ -34,5 +34,5 @@ autoguidestick/main.o: ..\Core\Src\main.c ..\Core\Inc\app_threadx.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
-  ..\Core\Inc\gpdma.h ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h \
-  ..\Core\Inc\gpio.h
+  ..\Core\Inc\gpdma.h ..\Core\Inc\memorymap.h ..\Core\Inc\tim.h \
+  ..\Core\Inc\usart.h ..\Core\Inc\gpio.h
diff --git a/MDK-ARM/AutoGuideStick/main.o b/MDK-ARM/AutoGuideStick/main.o
index fcdee2c..ef0f6a5 100644
Binary files a/MDK-ARM/AutoGuideStick/main.o and b/MDK-ARM/AutoGuideStick/main.o differ
diff --git a/MDK-ARM/AutoGuideStick/shake_motor.d b/MDK-ARM/AutoGuideStick/shake_motor.d
new file mode 100644
index 0000000..921df52
--- /dev/null
+++ b/MDK-ARM/AutoGuideStick/shake_motor.d
@@ -0,0 +1,42 @@
+autoguidestick/shake_motor.o: ..\fun\Shake_Motor.c ..\fun\Shake_Motor.h \
+  ..\fun\headfile.h ..\Core\Inc\main.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \
+  ..\Core\Inc\stm32h5xx_hal_conf.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \
+  D:\keil5\ARM\ARMCLANG\include\math.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \
+  ..\Drivers\CMSIS\Include\core_cm33.h \
+  D:\keil5\ARM\ARMCLANG\include\stdint.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \
+  D:\keil5\ARM\ARMCLANG\include\stddef.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
+  ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \
+  ..\Core\Inc\gpdma.h ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
+  D:\keil5\ARM\ARMCLANG\include\stdio.h \
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\HCBle.h ..\fun\gps.h \
+  ..\fun\Ultrasound.h ..\fun\Buzzer.h
diff --git a/MDK-ARM/AutoGuideStick/shake_motor.o b/MDK-ARM/AutoGuideStick/shake_motor.o
new file mode 100644
index 0000000..5e7dc64
Binary files /dev/null and b/MDK-ARM/AutoGuideStick/shake_motor.o differ
diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_it.d b/MDK-ARM/AutoGuideStick/stm32h5xx_it.d
index 225129e..cbe2ed0 100644
--- a/MDK-ARM/AutoGuideStick/stm32h5xx_it.d
+++ b/MDK-ARM/AutoGuideStick/stm32h5xx_it.d
@@ -32,7 +32,11 @@ autoguidestick/stm32h5xx_it.o: ..\Core\Src\stm32h5xx_it.c \
   ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
   ..\Core\Inc\stm32h5xx_it.h ..\fun\headfile.h ..\Core\Inc\memorymap.h \
   ..\Core\Inc\usart.h ..\Core\Inc\gpio.h ..\Core\Inc\gpdma.h \
+  ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
   D:\keil5\ARM\ARMCLANG\include\stdio.h \
-  D:\keil5\ARM\ARMCLANG\include\stdlib.h \
-  D:\keil5\ARM\ARMCLANG\include\stdarg.h \
-  D:\keil5\ARM\ARMCLANG\include\string.h ..\fun\HCBle.h ..\fun\gps.h
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\HCBle.h ..\fun\gps.h \
+  ..\fun\Shake_Motor.h ..\fun\Ultrasound.h ..\fun\Buzzer.h
diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_it.o b/MDK-ARM/AutoGuideStick/stm32h5xx_it.o
index c7f8aa4..7b93b43 100644
Binary files a/MDK-ARM/AutoGuideStick/stm32h5xx_it.o and b/MDK-ARM/AutoGuideStick/stm32h5xx_it.o differ
diff --git a/MDK-ARM/AutoGuideStick/tim.d b/MDK-ARM/AutoGuideStick/tim.d
new file mode 100644
index 0000000..b638a3f
--- /dev/null
+++ b/MDK-ARM/AutoGuideStick/tim.d
@@ -0,0 +1,32 @@
+autoguidestick/tim.o: ..\Core\Src\tim.c ..\Core\Inc\tim.h \
+  ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \
+  ..\Core\Inc\stm32h5xx_hal_conf.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \
+  D:\keil5\ARM\ARMCLANG\include\math.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \
+  ..\Drivers\CMSIS\Include\core_cm33.h \
+  D:\keil5\ARM\ARMCLANG\include\stdint.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \
+  D:\keil5\ARM\ARMCLANG\include\stddef.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h
diff --git a/MDK-ARM/AutoGuideStick/tim.o b/MDK-ARM/AutoGuideStick/tim.o
new file mode 100644
index 0000000..5a655a7
Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tim.o differ
diff --git a/MDK-ARM/AutoGuideStick/ultrasound.d b/MDK-ARM/AutoGuideStick/ultrasound.d
new file mode 100644
index 0000000..7ceb2b1
--- /dev/null
+++ b/MDK-ARM/AutoGuideStick/ultrasound.d
@@ -0,0 +1,42 @@
+autoguidestick/ultrasound.o: ..\fun\Ultrasound.c ..\fun\Ultrasound.h \
+  ..\fun\headfile.h ..\Core\Inc\main.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \
+  ..\Core\Inc\stm32h5xx_hal_conf.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \
+  D:\keil5\ARM\ARMCLANG\include\math.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \
+  ..\Drivers\CMSIS\Include\core_cm33.h \
+  D:\keil5\ARM\ARMCLANG\include\stdint.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \
+  D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \
+  ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \
+  D:\keil5\ARM\ARMCLANG\include\stddef.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \
+  ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \
+  ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \
+  ..\Core\Inc\gpdma.h ..\Core\Inc\tim.h ..\Core\Inc\app_threadx.h \
+  ..\Middlewares\ST\threadx\common\inc\tx_api.h \
+  ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \
+  ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \
+  D:\keil5\ARM\ARMCLANG\include\string.h \
+  D:\keil5\ARM\ARMCLANG\include\stdio.h \
+  D:\keil5\ARM\ARMCLANG\include\stdarg.h ..\fun\HCBle.h ..\fun\gps.h \
+  ..\fun\Shake_Motor.h ..\fun\Buzzer.h
diff --git a/MDK-ARM/AutoGuideStick/ultrasound.o b/MDK-ARM/AutoGuideStick/ultrasound.o
new file mode 100644
index 0000000..dd5f309
Binary files /dev/null and b/MDK-ARM/AutoGuideStick/ultrasound.o differ
diff --git a/MDK-ARM/AutoGuideStick/usart.o b/MDK-ARM/AutoGuideStick/usart.o
index 733f706..50282ef 100644
Binary files a/MDK-ARM/AutoGuideStick/usart.o and b/MDK-ARM/AutoGuideStick/usart.o differ
diff --git a/fun/Buzzer.c b/fun/Buzzer.c
new file mode 100644
index 0000000..432ac9e
--- /dev/null
+++ b/fun/Buzzer.c
@@ -0,0 +1,11 @@
+#include "Buzzer.h"
+
+void Buzzer_Open(void)
+{
+	HAL_GPIO_WritePin(Buzzer_GPIO_Port,Buzzer_Pin,GPIO_PIN_SET); // 高电平响起
+}
+
+void Buzzer_Close(void)
+{
+	HAL_GPIO_WritePin(Buzzer_GPIO_Port,Buzzer_Pin,GPIO_PIN_RESET); // 低电平关闭
+}
\ No newline at end of file
diff --git a/fun/Buzzer.h b/fun/Buzzer.h
new file mode 100644
index 0000000..d9430f9
--- /dev/null
+++ b/fun/Buzzer.h
@@ -0,0 +1,9 @@
+#ifndef __BUZZER_H__
+#define __BUZZER_H__
+
+#include "headfile.h"
+
+void Buzzer_Open(void);
+void Buzzer_Close(void);
+
+#endif
\ No newline at end of file
diff --git a/fun/HCBle.c b/fun/HCBle.c
index d0ae0e1..b9cd56f 100644
--- a/fun/HCBle.c
+++ b/fun/HCBle.c
@@ -134,6 +134,20 @@ void HCBle_ExtractAndParseFrame(void)
 	}
 }
 
+#ifdef task 
+// BLE接收任务
+void ble_rx_task_entry(ULONG thread_input)
+{
+	HCBle_InitDMAReception();
+	
+	while(1)
+	{
+		// 处理接收到的数据
+		
+	}
+	
+}
+#endif 
 
 
 
diff --git a/fun/HCBle.h b/fun/HCBle.h
index a0c8813..83461e1 100644
--- a/fun/HCBle.h
+++ b/fun/HCBle.h
@@ -7,6 +7,7 @@
 #define RING_BUFFER_SIZE	256	
 #define UART_DMA_RX_BUF_SIZE  64
 
+#define task  1
 // HCBle 相关数据定义
 typedef struct
 {
@@ -34,6 +35,7 @@ typedef struct
 extern uint8_t  rx_data;  
 extern RingBuffer ble_rx_ring; //初始化
 extern uint8_t uart_dma_rx_buf[UART_DMA_RX_BUF_SIZE];
+extern LocationData current_location;
 
 void HCBle_InitDMAReception(void);
 void HCBle_ExtractAndParseFrame(void);
diff --git a/fun/Shake_Motor.c b/fun/Shake_Motor.c
new file mode 100644
index 0000000..50cf4ec
--- /dev/null
+++ b/fun/Shake_Motor.c
@@ -0,0 +1,11 @@
+#include "Shake_Motor.h"
+
+void Shake_Motor_Open(void)
+{
+	HAL_GPIO_WritePin(Shake_Motor_GPIO_Port,Shake_Motor_Pin,GPIO_PIN_SET); // 高电平响起
+}
+
+void Shake_Motor_Close(void)
+{
+	HAL_GPIO_WritePin(Shake_Motor_GPIO_Port,Shake_Motor_Pin,GPIO_PIN_RESET); // 低电平关闭
+}
\ No newline at end of file
diff --git a/fun/Shake_Motor.h b/fun/Shake_Motor.h
new file mode 100644
index 0000000..4b1dfa7
--- /dev/null
+++ b/fun/Shake_Motor.h
@@ -0,0 +1,8 @@
+#ifndef __SHAKE_MOTOR_H
+#define __SHAKE_MOTOR_H	
+
+#include "headfile.h"
+
+
+
+#endif
\ No newline at end of file
diff --git a/fun/Ultrasound.c b/fun/Ultrasound.c
new file mode 100644
index 0000000..a3a4476
--- /dev/null
+++ b/fun/Ultrasound.c
@@ -0,0 +1,111 @@
+#include "Ultrasound.h"
+TX_THREAD ultrasonic_task_handle;
+TX_EVENT_FLAGS_GROUP ultrasonic_event;
+
+
+extern TIM_HandleTypeDef htim2;
+
+volatile uint32_t ic_val1 = 0; // 捕获值1
+volatile uint32_t ic_val2 = 0; // 捕获值2
+volatile uint8_t  is_first_capture = 0; // 是否为第一次捕获
+volatile uint32_t distance_cm = 0;  // 距离按照 cm计算
+
+/*******
+对于 超声波的配置
+Psc: 250 - 1  以达到   1tick = 1us的效果
+*******/
+
+/****
+
+DWT的初始化  待确认
+
+放到main.c中进行初始化
+****/
+void DWT_Init(void)
+{
+	CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+	DWT->CYCCNT = (uint32_t)0u; //新加入的
+	DWT->CTRL |= DWT_CTRL_CYCCNTENA_Msk;
+}
+
+
+
+
+/********
+delay_us() 函数实现 (使用DWT)  待确认
+*********/
+void delay_us(uint32_t us)
+{
+	uint32_t start = DWT->CYCCNT;
+	uint32_t ticks = us * (SystemCoreClock / 1000000U); // us * 64
+	while((DWT->CYCCNT - start) < ticks);
+}
+
+
+
+
+/******
+Trig 触发
+
+ You only need to supply a short 10uS 
+pulse to the trigger input to start the ranging
+
+尤其在周期性测距中，如果前一个测距周期残留了 Trig 为高电平，可能导致错误测距或模块死机。因此加上 HAL_GPIO_WritePin(..., RESET); HAL_Delay(); 是一种保险写法。
+******/
+void HCSR04_Trigger(void)
+{
+	HAL_GPIO_WritePin(HC_Trig_GPIO_Port,HC_Trig_Pin,GPIO_PIN_RESET);
+	delay_us(2);  //拉低2~5us
+	HAL_GPIO_WritePin(HC_Trig_GPIO_Port,HC_Trig_Pin,GPIO_PIN_SET);
+	delay_us(10); // 保持高电平10us 
+	HAL_GPIO_WritePin(HC_Trig_GPIO_Port,HC_Trig_Pin,GPIO_PIN_RESET);
+}
+
+
+#ifdef HCSR_TEST
+void ultrasonic_task_entry(ULONG thread_input) {
+    HAL_TIM_IC_Start_IT(&htim2, TIM_CHANNEL_2);
+
+    while (1) {
+        HCSR04_Trigger();
+
+        ULONG actual_flags;
+        if (tx_event_flags_get(&ultrasonic_event, EVENT_ECHO_DONE, TX_OR_CLEAR,
+                               &actual_flags, TX_WAIT_FOREVER) == TX_SUCCESS) {
+            if (distance_cm < 30) {
+                // 执行避障处理：如振动、停机、语音提示等
+            }
+        }
+
+        tx_thread_sleep(50);  // 每次测距间隔 50 ticks
+    }
+}
+#endif
+
+
+
+
+/*******
+Echo 输入捕获回调函数
+
+******/
+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) {
+    if (htim->Channel == HAL_TIM_ACTIVE_CHANNEL_2) {
+        if (is_first_capture == 0) {
+            ic_val1 = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_2);
+            __HAL_TIM_SET_CAPTUREPOLARITY(htim, TIM_CHANNEL_2, TIM_INPUTCHANNELPOLARITY_FALLING);
+            is_first_capture = 1;
+        } else {
+            ic_val2 = HAL_TIM_ReadCapturedValue(htim, TIM_CHANNEL_2);
+            __HAL_TIM_SET_CAPTUREPOLARITY(htim, TIM_CHANNEL_2, TIM_INPUTCHANNELPOLARITY_RISING);
+            is_first_capture = 0;
+
+            uint32_t delta = (ic_val2 > ic_val1) ? (ic_val2 - ic_val1) : (0xFFFF - ic_val1 + ic_val2);
+            distance_cm = delta / 58;
+
+            // 通知任务
+//            tx_event_flags_set(&ultrasonic_event, EVENT_ECHO_DONE, TX_OR);
+        }
+    }
+}
+
diff --git a/fun/Ultrasound.h b/fun/Ultrasound.h
new file mode 100644
index 0000000..fcee145
--- /dev/null
+++ b/fun/Ultrasound.h
@@ -0,0 +1,25 @@
+#ifndef __ULTRASOUND_H
+#define __ULTRASOUND_H	
+
+#include "headfile.h"
+
+#define HCSR_TEST 1
+#define EVENT_ECHO_DONE		0x01
+
+
+void DWT_Init(void);
+/********
+delay_us() 函数实现 (使用DWT)  待确认
+*********/
+void delay_us(uint32_t us);
+
+/******
+Trig 触发
+
+ You only need to supply a short 10uS 
+pulse to the trigger input to start the ranging
+
+尤其在周期性测距中，如果前一个测距周期残留了 Trig 为高电平，可能导致错误测距或模块死机。因此加上 HAL_GPIO_WritePin(..., RESET); HAL_Delay(); 是一种保险写法。
+******/
+void HCSR04_Trigger(void);
+#endif
\ No newline at end of file
diff --git a/fun/headfile.h b/fun/headfile.h
index cf65a27..494d7db 100644
--- a/fun/headfile.h
+++ b/fun/headfile.h
@@ -6,6 +6,8 @@
 #include "usart.h"
 #include "gpio.h"
 #include "gpdma.h"
+#include "tim.h"
+#include "app_threadx.h"
 
 #include "stdio.h"
 #include "stdlib.h"
@@ -14,5 +16,8 @@
 
 #include "HCBle.h"
 #include "gps.h"
+#include "Shake_Motor.h"
+#include "Ultrasound.h"
+#include "Buzzer.h"
 
 #endif
\ No newline at end of file