diff --git a/.mxproject b/.mxproject index 82e7f1d..468c607 100644 --- a/.mxproject +++ b/.mxproject @@ -1,13 +1,22 @@ +[PreviousLibFiles] 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+HeaderPath=..\Drivers\STM32H5xx_HAL_Driver\Inc;..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy;..\Middlewares\ST\threadx\common\inc;..\Drivers\CMSIS\Device\ST\STM32H5xx\Include;..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc;..\Drivers\CMSIS\Include;..\Core\Inc;..\AZURE_RTOS\App; +CDefines=TX_INCLUDE_USER_DEFINE_FILE;TX_SINGLE_MODE_NON_SECURE:1;USE_HAL_DRIVER;STM32H563xx;USE_HAL_DRIVER;USE_HAL_DRIVER; +ADefines=TX_SINGLE_MODE_NON_SECURE:1; + [PreviousGenFiles] AdvancedFolderStructure=true HeaderFileListSize=10 HeaderFiles#0=..\Core\Inc\gpio.h -HeaderFiles#1=..\Core\Inc\icache.h -HeaderFiles#2=..\Core\Inc\memorymap.h -HeaderFiles#3=..\Core\Inc\app_threadx.h -HeaderFiles#4=..\AZURE_RTOS\App\app_azure_rtos.h -HeaderFiles#5=..\Core\Inc\tx_user.h -HeaderFiles#6=..\AZURE_RTOS\App\app_azure_rtos_config.h +HeaderFiles#1=..\Core\Inc\memorymap.h +HeaderFiles#2=..\Core\Inc\app_threadx.h +HeaderFiles#3=..\AZURE_RTOS\App\app_azure_rtos.h +HeaderFiles#4=..\Core\Inc\tx_user.h +HeaderFiles#5=..\AZURE_RTOS\App\app_azure_rtos_config.h +HeaderFiles#6=..\Core\Inc\usart.h HeaderFiles#7=..\Core\Inc\stm32h5xx_it.h HeaderFiles#8=..\Core\Inc\stm32h5xx_hal_conf.h HeaderFiles#9=..\Core\Inc\main.h @@ -18,10 +27,10 @@ HeaderFiles=; SourceFileListSize=10 SourceFiles#0=..\Core\Src\tx_initialize_low_level.S SourceFiles#1=..\Core\Src\gpio.c -SourceFiles#2=..\Core\Src\icache.c -SourceFiles#3=..\Core\Src\memorymap.c -SourceFiles#4=..\Core\Src\app_threadx.c -SourceFiles#5=..\AZURE_RTOS\App\app_azure_rtos.c +SourceFiles#2=..\Core\Src\memorymap.c +SourceFiles#3=..\Core\Src\app_threadx.c +SourceFiles#4=..\AZURE_RTOS\App\app_azure_rtos.c +SourceFiles#5=..\Core\Src\usart.c SourceFiles#6=..\Core\Src\stm32h5xx_it.c SourceFiles#7=..\Core\Src\stm32h5xx_hal_msp.c SourceFiles#8=..\Core\Src\stm32h5xx_hal_timebase_tim.c @@ -31,12 +40,3 @@ SourcePath#0=..\Core\Src SourcePath#1=..\AZURE_RTOS\App SourceFiles=; -[PreviousLibFiles] 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-HeaderPath=..\Drivers\STM32H5xx_HAL_Driver\Inc;..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy;..\Middlewares\ST\threadx\common\inc;..\Drivers\CMSIS\Device\ST\STM32H5xx\Include;..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc;..\Drivers\CMSIS\Include;..\Core\Inc;..\AZURE_RTOS\App; -CDefines=TX_INCLUDE_USER_DEFINE_FILE;TX_SINGLE_MODE_NON_SECURE:1;USE_HAL_DRIVER;STM32H563xx;USE_HAL_DRIVER;USE_HAL_DRIVER; -ADefines=TX_SINGLE_MODE_NON_SECURE:1; - diff --git a/AutoGuideStick.ioc b/AutoGuideStick.ioc index 334f6bc..fd77254 100644 --- a/AutoGuideStick.ioc +++ b/AutoGuideStick.ioc @@ -1,4 +1,7 @@ #MicroXplorer Configuration settings - do not modify +BOOTPATH.BootPathName=LEGACY +BOOTPATH.IPParameters=BootPathName +BOOTPATH.UserSelectedBootPath=LEGACY CAD.formats= CAD.pinconfig= CAD.provider= @@ -13,35 +16,32 @@ Mcu.ContextProject=TrustZoneDisabled Mcu.Family=STM32H5 Mcu.IP0=BOOTPATH Mcu.IP1=CORTEX_M33_NS -Mcu.IP2=DEBUG -Mcu.IP3=ICACHE -Mcu.IP4=MEMORYMAP -Mcu.IP5=NVIC -Mcu.IP6=PWR -Mcu.IP7=RCC -Mcu.IP8=SYS -Mcu.IP9=THREADX -Mcu.IPNb=10 +Mcu.IP2=MEMORYMAP +Mcu.IP3=NVIC +Mcu.IP4=PWR +Mcu.IP5=RCC +Mcu.IP6=SYS +Mcu.IP7=THREADX +Mcu.IP8=USART1 +Mcu.IPNb=9 Mcu.Name=STM32H563ZITx Mcu.Package=LQFP144 Mcu.Pin0=PH0-OSC_IN(PH0) -Mcu.Pin1=PH1-OSC_OUT(PH1) -Mcu.Pin10=VP_BOOTPATH_VS_BOOTPATH -Mcu.Pin11=VP_MEMORYMAP_VS_MEMORYMAP -Mcu.Pin2=PA13(JTMS/SWDIO) -Mcu.Pin3=PA14(JTCK/SWCLK) -Mcu.Pin4=VP_CORTEX_M33_NS_VS_Hclk -Mcu.Pin5=VP_ICACHE_VS_ICACHE -Mcu.Pin6=VP_PWR_VS_SECSignals -Mcu.Pin7=VP_PWR_VS_LPOM -Mcu.Pin8=VP_SYS_VS_tim1 -Mcu.Pin9=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault -Mcu.PinsNb=12 +Mcu.Pin1=PB14 +Mcu.Pin2=PB15 +Mcu.Pin3=VP_CORTEX_M33_NS_VS_Hclk +Mcu.Pin4=VP_PWR_VS_SECSignals +Mcu.Pin5=VP_PWR_VS_LPOM +Mcu.Pin6=VP_SYS_VS_tim1 +Mcu.Pin7=VP_THREADX_VS_RTOSJjThreadXJjCoreJjDefault +Mcu.Pin8=VP_BOOTPATH_VS_BOOTPATH +Mcu.Pin9=VP_MEMORYMAP_VS_MEMORYMAP +Mcu.PinsNb=10 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32H563ZITx -MxCube.Version=6.14.0 -MxDb.Version=DB.6.0.140 +MxCube.Version=6.14.1 +MxDb.Version=DB.6.0.141 NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false NVIC.ForceEnableDMAVector=true @@ -58,15 +58,14 @@ NVIC.SysTick_IRQn=true\:14\:0\:false\:false\:false\:false\:false\:true\:false NVIC.TIM1_UP_IRQn=true\:15\:0\:false\:false\:true\:false\:false\:true\:true NVIC.TimeBase=TIM1_UP_IRQn NVIC.TimeBaseIP=TIM1 +NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:false\:true\:true\:true NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false -PA13(JTMS/SWDIO).Mode=Serial_Wire -PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO -PA14(JTCK/SWCLK).Mode=Serial_Wire -PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK -PH0-OSC_IN(PH0).Mode=HSE-External-Oscillator +PB14.Mode=Asynchronous +PB14.Signal=USART1_TX +PB15.Mode=Asynchronous +PB15.Signal=USART1_RX +PH0-OSC_IN(PH0).Mode=HSE-External-Clock-Source PH0-OSC_IN(PH0).Signal=RCC_OSC_IN -PH1-OSC_OUT(PH1).Mode=HSE-External-Oscillator -PH1-OSC_OUT(PH1).Signal=RCC_OSC_OUT PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -99,7 +98,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ICACHE_Init-ICACHE-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_USART1_UART_Init-USART1-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true RCC.ADCFreq_Value=250000000 RCC.AHBFreq_Value=250000000 RCC.APB1Freq_Value=250000000 @@ -185,12 +184,13 @@ RCC.VCOInputFreq_Value=4000000 RCC.VCOOutputFreq_Value=500000000 RCC.VCOPLL2OutputFreq_Value=516000000 RCC.VCOPLL3OutputFreq_Value=516000000 +USART1.BaudRate=9600 +USART1.IPParameters=VirtualMode-Asynchronous,BaudRate +USART1.VirtualMode-Asynchronous=VM_ASYNC VP_BOOTPATH_VS_BOOTPATH.Mode=BP_Activate VP_BOOTPATH_VS_BOOTPATH.Signal=BOOTPATH_VS_BOOTPATH VP_CORTEX_M33_NS_VS_Hclk.Mode=Hclk_Mode VP_CORTEX_M33_NS_VS_Hclk.Signal=CORTEX_M33_NS_VS_Hclk -VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache -VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP VP_PWR_VS_LPOM.Mode=PowerOptimisation diff --git a/Core/Inc/stm32h5xx_hal_conf.h b/Core/Inc/stm32h5xx_hal_conf.h index 7bf9e4e..bfcd48e 100644 --- a/Core/Inc/stm32h5xx_hal_conf.h +++ b/Core/Inc/stm32h5xx_hal_conf.h @@ -80,11 +80,11 @@ /*#define HAL_SRAM_MODULE_ENABLED */ #define HAL_TIM_MODULE_ENABLED /*#define HAL_RAMCFG_MODULE_ENABLED */ -/*#define HAL_UART_MODULE_ENABLED */ +#define HAL_UART_MODULE_ENABLED /*#define HAL_USART_MODULE_ENABLED */ /*#define HAL_WWDG_MODULE_ENABLED */ /*#define HAL_PSSI_MODULE_ENABLED */ -#define HAL_ICACHE_MODULE_ENABLED +/*#define HAL_ICACHE_MODULE_ENABLED */ /*#define HAL_PCD_MODULE_ENABLED */ #define HAL_GPIO_MODULE_ENABLED #define HAL_EXTI_MODULE_ENABLED diff --git a/Core/Inc/stm32h5xx_it.h b/Core/Inc/stm32h5xx_it.h index 6d8c5fd..cfaa0a8 100644 --- a/Core/Inc/stm32h5xx_it.h +++ b/Core/Inc/stm32h5xx_it.h @@ -53,6 +53,7 @@ void BusFault_Handler(void); void UsageFault_Handler(void); void DebugMon_Handler(void); void TIM1_UP_IRQHandler(void); +void USART1_IRQHandler(void); /* USER CODE BEGIN EFP */ /* USER CODE END EFP */ diff --git a/Core/Inc/icache.h b/Core/Inc/usart.h similarity index 86% rename from Core/Inc/icache.h rename to Core/Inc/usart.h index e686d12..10c6193 100644 --- a/Core/Inc/icache.h +++ b/Core/Inc/usart.h @@ -1,9 +1,9 @@ /* USER CODE BEGIN Header */ /** ****************************************************************************** - * @file icache.h + * @file usart.h * @brief This file contains all the function prototypes for - * the icache.c file + * the usart.c file ****************************************************************************** * @attention * @@ -18,8 +18,8 @@ */ /* USER CODE END Header */ /* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __ICACHE_H__ -#define __ICACHE_H__ +#ifndef __USART_H__ +#define __USART_H__ #ifdef __cplusplus extern "C" { @@ -32,11 +32,13 @@ extern "C" { /* USER CODE END Includes */ +extern UART_HandleTypeDef huart1; + /* USER CODE BEGIN Private defines */ /* USER CODE END Private defines */ -void MX_ICACHE_Init(void); +void MX_USART1_UART_Init(void); /* USER CODE BEGIN Prototypes */ @@ -46,5 +48,5 @@ void MX_ICACHE_Init(void); } #endif -#endif /* __ICACHE_H__ */ +#endif /* __USART_H__ */ diff --git a/Core/Src/gpio.c b/Core/Src/gpio.c index 60db41d..9dcf175 100644 --- a/Core/Src/gpio.c +++ b/Core/Src/gpio.c @@ -34,16 +34,13 @@ /** Configure pins PH0-OSC_IN(PH0) ------> RCC_OSC_IN - PH1-OSC_OUT(PH1) ------> RCC_OSC_OUT - PA13(JTMS/SWDIO) ------> DEBUG_JTMS-SWDIO - PA14(JTCK/SWCLK) ------> DEBUG_JTCK-SWCLK */ void MX_GPIO_Init(void) { /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); } diff --git a/Core/Src/icache.c b/Core/Src/icache.c deleted file mode 100644 index 63795c3..0000000 --- a/Core/Src/icache.c +++ /dev/null @@ -1,57 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file icache.c - * @brief This file provides code for the configuration - * of the ICACHE instances. - ****************************************************************************** - * @attention - * - * Copyright (c) 2025 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "icache.h" - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* ICACHE init function */ -void MX_ICACHE_Init(void) -{ - - /* USER CODE BEGIN ICACHE_Init 0 */ - - /* USER CODE END ICACHE_Init 0 */ - - /* USER CODE BEGIN ICACHE_Init 1 */ - - /* USER CODE END ICACHE_Init 1 */ - - /** Enable instruction cache in 1-way (direct mapped cache) - */ - if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) - { - Error_Handler(); - } - if (HAL_ICACHE_Enable() != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ICACHE_Init 2 */ - - /* USER CODE END ICACHE_Init 2 */ - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ diff --git a/Core/Src/main.c b/Core/Src/main.c index fe4bae6..055e70f 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -19,8 +19,8 @@ /* Includes ------------------------------------------------------------------*/ #include "app_threadx.h" #include "main.h" -#include "icache.h" #include "memorymap.h" +#include "usart.h" #include "gpio.h" /* Private includes ----------------------------------------------------------*/ @@ -89,7 +89,7 @@ int main(void) /* Initialize all configured peripherals */ MX_GPIO_Init(); - MX_ICACHE_Init(); + MX_USART1_UART_Init(); /* USER CODE BEGIN 2 */ /* USER CODE END 2 */ diff --git a/Core/Src/stm32h5xx_it.c b/Core/Src/stm32h5xx_it.c index dc80d1f..8223192 100644 --- a/Core/Src/stm32h5xx_it.c +++ b/Core/Src/stm32h5xx_it.c @@ -55,6 +55,7 @@ /* USER CODE END 0 */ /* External variables --------------------------------------------------------*/ +extern UART_HandleTypeDef huart1; extern TIM_HandleTypeDef htim1; /* USER CODE BEGIN EV */ @@ -173,6 +174,20 @@ void TIM1_UP_IRQHandler(void) /* USER CODE END TIM1_UP_IRQn 1 */ } +/** + * @brief This function handles USART1 global interrupt. + */ +void USART1_IRQHandler(void) +{ + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Core/Src/usart.c b/Core/Src/usart.c new file mode 100644 index 0000000..9967791 --- /dev/null +++ b/Core/Src/usart.c @@ -0,0 +1,145 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file usart.c + * @brief This file provides code for the configuration + * of the USART instances. + ****************************************************************************** + * @attention + * + * Copyright (c) 2025 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "usart.h" + +/* USER CODE BEGIN 0 */ + +/* USER CODE END 0 */ + +UART_HandleTypeDef huart1; + +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 9600; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + { + Error_Handler(); + } + if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspInit 0 */ + + /* USER CODE END USART1_MspInit 0 */ + + /** Initializes the peripherals clock + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + { + Error_Handler(); + } + + /* USART1 clock enable */ + __HAL_RCC_USART1_CLK_ENABLE(); + + __HAL_RCC_GPIOB_CLK_ENABLE(); + /**USART1 GPIO Configuration + PB14 ------> USART1_TX + PB15 ------> USART1_RX + */ + GPIO_InitStruct.Pin = GPIO_PIN_14|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_NOPULL; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct.Alternate = GPIO_AF4_USART1; + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + /* USART1 interrupt Init */ + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + + if(uartHandle->Instance==USART1) + { + /* USER CODE BEGIN USART1_MspDeInit 0 */ + + /* USER CODE END USART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_USART1_CLK_DISABLE(); + + /**USART1 GPIO Configuration + PB14 ------> USART1_TX + PB15 ------> USART1_RX + */ + HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14|GPIO_PIN_15); + + /* USART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + +/* USER CODE BEGIN 1 */ + +/* USER CODE END 1 */ diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h deleted file mode 100644 index 20de95b..0000000 --- a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h +++ /dev/null @@ -1,300 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_hal_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32H5xx_HAL_ICACHE_H -#define STM32H5xx_HAL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32h5xx_hal_def.h" - -#if defined(ICACHE) -/** @addtogroup STM32H5xx_HAL_Driver - * @{ - */ - -/** @addtogroup ICACHE - * @{ - */ - -/* Exported types -----------------------------------------------------------*/ -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Exported_Types ICACHE Exported Types - * @{ - */ - -/** - * @brief HAL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ - - uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ - - uint32_t Size; /*!< Configures the Region size. - This parameter can be a value of @ref ICACHE_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_Output_Burst_Type */ -} ICACHE_RegionConfigTypeDef; -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_WaysSelection Ways selection - * @{ - */ -#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ -#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_Monitor_Type Monitor type - * @{ - */ -#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ -#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ -#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Region Remapped Region number - * @{ - */ -#define ICACHE_REGION_0 0U /*!< Region 0 */ -#define ICACHE_REGION_1 1U /*!< Region 1 */ -#define ICACHE_REGION_2 2U /*!< Region 2 */ -#define ICACHE_REGION_3 3U /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_Region_Size Remapped Region size - * @{ - */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_Traffic_Route Remapped Traffic route - * @{ - */ -#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ -#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ -#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** @defgroup ICACHE_Interrupts Interrupts - * @{ - */ -#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -/** @defgroup ICACHE_Flags Flags - * @{ - */ -#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ -#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management - * @brief macros to manage the specified ICACHE flags and interrupts. - * @{ - */ - -/** @brief Enable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Disable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Check whether the specified ICACHE interrupt source is enabled or not. - * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - * @retval The state of __INTERRUPT__ (0 or 1). - */ -#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ - ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) - -/** @brief Check whether the selected ICACHE flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref ICACHE_FLAG_BUSY Busy flag - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - * @retval The state of __FLAG__ (0 or 1). - */ -#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) - -/** @brief Clear the selected ICACHE flags. - * @param __FLAG__ specifies the ICACHE flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - */ -#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @addtogroup ICACHE_Exported_Functions - * @{ - */ - -/** @addtogroup ICACHE_Exported_Functions_Group1 - * @brief Initialization and control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_ICACHE_Enable(void); -HAL_StatusTypeDef HAL_ICACHE_Disable(void); -uint32_t HAL_ICACHE_IsEnabled(void); -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); -HAL_StatusTypeDef HAL_ICACHE_DeInit(void); - -/******* Invalidate in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); -/******* Invalidate in non-blocking mode (Interrupt) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); -/******* Wait for Invalidate complete in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); - -/******* Performance instruction cache monitoring functions */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); -uint32_t HAL_ICACHE_Monitor_GetHitValue(void); -uint32_t HAL_ICACHE_Monitor_GetMissValue(void); - -/** - * @} - */ - -/** @addtogroup ICACHE_Exported_Functions_Group2 - * @brief IRQ and callback functions - * @{ - */ -/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ -void HAL_ICACHE_IRQHandler(void); -void HAL_ICACHE_InvalidateCompleteCallback(void); -void HAL_ICACHE_ErrorCallback(void); - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @addtogroup ICACHE_Exported_Functions_Group3 - * @brief Memory remapped regions functions - * @{ - */ -/******* Memory remapped regions functions */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* ICACHE */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32H5xx_HAL_ICACHE_H */ diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h new file mode 100644 index 0000000..e643f6a --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h @@ -0,0 +1,1775 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart.h + * @author MCD Application Team + * @brief Header file of UART HAL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_UART_H +#define STM32H5xx_HAL_UART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UART + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UART_Exported_Types UART Exported Types + * @{ + */ + +/** + * @brief UART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + @note For LPUART : + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ + +} UART_InitTypeDef; + +/** + * @brief UART Advanced Features initialization structure definition + */ +typedef struct +{ + uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several + Advanced Features may be initialized at the same time . + This parameter can be a value of + @ref UART_Advanced_Features_Initialization_Type. */ + + uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. + This parameter can be a value of @ref UART_Tx_Inv. */ + + uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. + This parameter can be a value of @ref UART_Rx_Inv. */ + + uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic + vs negative/inverted logic). + This parameter can be a value of @ref UART_Data_Inv. */ + + uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. + This parameter can be a value of @ref UART_Rx_Tx_Swap. */ + + uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. + This parameter can be a value of @ref UART_Overrun_Disable. */ + +#if defined(HAL_DMA_MODULE_ENABLED) + uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. + This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. + This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ + + uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate + detection is carried out. + This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ + + uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. + This parameter can be a value of @ref UART_MSB_First. */ +} UART_AdvFeatureInitTypeDef; + +/** + * @brief HAL UART State definition + * @note HAL UART State value is a combination of 2 different substates: + * gState and RxState (see @ref UART_State_Definition). + * - gState contains UART state information related to global Handle management + * and also information related to Tx operations. + * gState value coding follow below described bitmap : + * b7-b6 Error information + * 00 : No Error + * 01 : (Not Used) + * 10 : Timeout + * 11 : Error + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized. HAL UART Init function already called) + * b4-b3 (not used) + * xx : Should be set to 00 + * b2 Intrinsic process state + * 0 : Ready + * 1 : Busy (Peripheral busy with some configuration or internal operations) + * b1 (not used) + * x : Should be set to 0 + * b0 Tx state + * 0 : Ready (no Tx operation ongoing) + * 1 : Busy (Tx operation ongoing) + * - RxState contains information related to Rx operations. + * RxState value coding follow below described bitmap : + * b7-b6 (not used) + * xx : Should be set to 00 + * b5 Peripheral initialization status + * 0 : Reset (Peripheral not initialized) + * 1 : Init done (Peripheral initialized) + * b4-b2 (not used) + * xxx : Should be set to 000 + * b1 Rx state + * 0 : Ready (no Rx operation ongoing) + * 1 : Busy (Rx operation ongoing) + * b0 (not used) + * x : Should be set to 0. + */ +typedef uint32_t HAL_UART_StateTypeDef; + +/** + * @brief UART clock sources definition + */ +typedef enum +{ + UART_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */ + UART_CLOCKSOURCE_PLL2Q = 0x01U, /*!< PLL2Q clock source */ + UART_CLOCKSOURCE_PLL3Q = 0x02U, /*!< PLL3Q clock source */ + UART_CLOCKSOURCE_HSI = 0x04U, /*!< HSI clock source */ + UART_CLOCKSOURCE_CSI = 0x08U, /*!< CSI clock source */ + UART_CLOCKSOURCE_LSE = 0x10U, /*!< LSE clock source */ + UART_CLOCKSOURCE_UNDEFINED = 0x20U /*!< Undefined clock source */ +} UART_ClockSourceTypeDef; + +/** + * @brief HAL UART Reception type definition + * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. + * This parameter can be a value of @ref UART_Reception_Type_Values : + * HAL_UART_RECEPTION_STANDARD = 0x00U, + * HAL_UART_RECEPTION_TOIDLE = 0x01U, + * HAL_UART_RECEPTION_TORTO = 0x02U, + * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, + */ +typedef uint32_t HAL_UART_RxTypeTypeDef; + +/** + * @brief HAL UART Rx Event type definition + * @note HAL UART Rx Event type value aims to identify which type of Event has occurred + * leading to call of the RxEvent callback. + * This parameter can be a value of @ref UART_RxEvent_Type_Values : + * HAL_UART_RXEVENT_TC = 0x00U, + * HAL_UART_RXEVENT_HT = 0x01U, + * HAL_UART_RXEVENT_IDLE = 0x02U, + */ +typedef uint32_t HAL_UART_RxEventTypeTypeDef; + +/** + * @brief UART handle Structure definition + */ +typedef struct __UART_HandleTypeDef +{ + USART_TypeDef *Instance; /*!< UART registers base address */ + + UART_InitTypeDef Init; /*!< UART communication parameters */ + + UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ + + const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ + + uint16_t TxXferSize; /*!< UART Tx Transfer size */ + + __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ + + uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ + + uint16_t RxXferSize; /*!< UART Rx Transfer size */ + + __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ + + uint16_t Mask; /*!< UART Rx RDR register mask */ + + uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. + This parameter can be a value of @ref UARTEx_FIFO_mode. */ + + uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ + + uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ + + __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ + + __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ + + void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ + + void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ + +#if defined(HAL_DMA_MODULE_ENABLED) + DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ + + DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ + +#endif /* HAL_DMA_MODULE_ENABLED */ + HAL_LockTypeDef Lock; /*!< Locking object */ + + __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management + and also related to Tx operations. This parameter + can be a value of @ref HAL_UART_StateTypeDef */ + + __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This + parameter can be a value of @ref HAL_UART_StateTypeDef */ + + __IO uint32_t ErrorCode; /*!< UART Error code */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ + void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ + void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ + void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ + void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ + void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ + void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ + void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ + void (* WakeupCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Wakeup Callback */ + void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ + void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ + void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ + + void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ + void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +} UART_HandleTypeDef; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief HAL UART Callback ID enumeration definition + */ +typedef enum +{ + HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ + HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ + HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ + HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ + HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ + HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ + HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ + HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ + HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ + HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ + HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ + + HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ + HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ + +} HAL_UART_CallbackIDTypeDef; + +/** + * @brief HAL UART Callback pointer definition + */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UART_Exported_Constants UART Exported Constants + * @{ + */ + +/** @defgroup UART_State_Definition UART State Code Definition + * @{ + */ +#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use + Value is allowed for gState and RxState */ +#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing + Value is allowed for gState only */ +#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing + Value is allowed for RxState only */ +#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing + Not to be used for neither gState nor RxState.Value is result + of combination (Or) between gState and RxState values */ +#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state + Value is allowed for gState only */ +#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error + Value is allowed for gState only */ +/** + * @} + */ + +/** @defgroup UART_Error_Definition UART Error Definition + * @{ + */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +/** + * @} + */ + +/** @defgroup UART_Stop_Bits UART Number of Stop Bits + * @{ + */ +#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ +#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ +#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ +#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ +/** + * @} + */ + +/** @defgroup UART_Parity UART Parity + * @{ + */ +#define UART_PARITY_NONE 0x00000000U /*!< No parity */ +#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ +#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ +/** + * @} + */ + +/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control + * @{ + */ +#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ +#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ +#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ +#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ +/** + * @} + */ + +/** @defgroup UART_Mode UART Transfer Mode + * @{ + */ +#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ +#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ +#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ +/** + * @} + */ + +/** @defgroup UART_State UART State + * @{ + */ +#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ +#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ +/** + * @} + */ + +/** @defgroup UART_Over_Sampling UART Over Sampling + * @{ + */ +#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method + * @{ + */ +#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ +#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ +/** + * @} + */ + +/** @defgroup UART_ClockPrescaler UART Clock Prescaler + * @{ + */ +#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ +#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ +#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ +#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ +#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ +#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ +#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ +#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ +#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ +#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ +#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ +#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ +/** + * @} + */ + +/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection + on start bit */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection + on falling edge */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection + on 0x7F frame detection */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection + on 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup UART_Receiver_Timeout UART Receiver Timeout + * @{ + */ +#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ +#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ +/** + * @} + */ + +/** @defgroup UART_LIN UART Local Interconnection Network mode + * @{ + */ +#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ +#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ +/** + * @} + */ + +/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection + * @{ + */ +#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ +#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Tx UART DMA Tx + * @{ + */ +#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ +#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ +/** + * @} + */ + +/** @defgroup UART_DMA_Rx UART DMA Rx + * @{ + */ +#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ +#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection + * @{ + */ +#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ +#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_Methods UART WakeUp Methods + * @{ + */ +#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ +#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ +/** + * @} + */ + +/** @defgroup UART_Request_Parameters UART Request Parameters + * @{ + */ +#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ +#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ +#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ +#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ +#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ +/** + * @} + */ + +/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type + * @{ + */ +#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ +#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ +#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ +#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ +#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ +#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ +#endif /* HAL_DMA_MODULE_ENABLED */ +#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ +#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ +/** + * @} + */ + +/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ +#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion + * @{ + */ +#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ +#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion + * @{ + */ +#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ +#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ +/** + * @} + */ + +/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap + * @{ + */ +#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ +#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ +/** + * @} + */ + +/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable + * @{ + */ +#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ +#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ +/** + * @} + */ + +/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable + * @{ + */ +#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ +#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ +/** + * @} + */ + +#if defined(HAL_DMA_MODULE_ENABLED) +/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error + * @{ + */ +#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ +#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ +/** + * @} + */ +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** @defgroup UART_MSB_First UART Advanced Feature MSB First + * @{ + */ +#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received + first disable */ +#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received + first enable */ +/** + * @} + */ + +/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable + * @{ + */ +#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ +#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ +/** + * @} + */ + +/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable + * @{ + */ +#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ +#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ +/** + * @} + */ + +/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register + * @{ + */ +#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ +/** + * @} + */ + +/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection + * @{ + */ +#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ +#define UART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< UART wake-up on start bit */ +#define UART_WAKEUP_ON_READDATA_NONEMPTY USART_CR3_WUS /*!< UART wake-up on receive data register + not empty or RXFIFO is not empty */ +/** + * @} + */ + +/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity + * @{ + */ +#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ +#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register + * @{ + */ +#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB + position in CR1 register */ +/** + * @} + */ + +/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask + * @{ + */ +#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ +/** + * @} + */ + +/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value + * @{ + */ +#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ +/** + * @} + */ + +/** @defgroup UART_Flags UART Status Flags + * Elements values convention: 0xXXXX + * - 0xXXXX : Flag mask in the ISR register + * @{ + */ +#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ +#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ +#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ +#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ +#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ +#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ +#define UART_FLAG_WUF USART_ISR_WUF /*!< UART wake-up from stop mode flag */ +#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ +#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ +#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ +#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ +#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ +#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ +#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ +#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ +#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ +#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ +#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ +#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ +#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ +#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ +#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ +#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ +#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ +#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ +#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ +#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ +/** + * @} + */ + +/** @defgroup UART_Interrupt_definition UART Interrupts Definition + * Elements values convention: 000ZZZZZ0XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * - ZZZZZ : Flag position in the ISR register(5bits) + * Elements values convention: 000000000XXYYYYYb + * - YYYYY : Interrupt source position in the XX register (5bits) + * - XX : Interrupt source register (2bits) + * - 01: CR1 register + * - 10: CR2 register + * - 11: CR3 register + * Elements values convention: 0000ZZZZ00000000b + * - ZZZZ : Flag position in the ISR register(4bits) + * @{ + */ +#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ +#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ +#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ +#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ +#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ +#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ +#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ +#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ +#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ +#define UART_IT_CM 0x112EU /*!< UART character match interruption */ +#define UART_IT_WUF 0x1476U /*!< UART wake-up from stop mode interruption */ +#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ +#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ +#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ +#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ +#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ + +#define UART_IT_ERR 0x0060U /*!< UART error interruption */ + +#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ +#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ +#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ +/** + * @} + */ + +/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags + * @{ + */ +#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ +#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ +#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ +#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ +#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ +#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ +#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ +#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ +#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ +#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ +#define UART_CLEAR_WUF USART_ICR_WUCF /*!< Wake Up from stop mode Clear Flag */ +#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ +/** + * @} + */ + +/** @defgroup UART_Reception_Type_Values UART Reception type values + * @{ + */ +#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ +#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ +#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ +#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ +/** + * @} + */ + +/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values + * @{ + */ +#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ +#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ +#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/** @defgroup UART_Exported_Macros UART Exported Macros + * @{ + */ + +/** @brief Reset UART handle states. + * @param __HANDLE__ UART handle. + * @retval None + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0U) +#else +#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ + (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ + (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ + } while(0U) +#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ + +/** @brief Flush the UART Data registers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ + do{ \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ + SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ + } while(0U) + +/** @brief Clear the specified UART pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be any combination of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) + +/** @brief Clear the UART PE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) + +/** @brief Clear the UART FE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) + +/** @brief Clear the UART NE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) + +/** @brief Clear the UART ORE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) + +/** @brief Clear the UART IDLE pending flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) + +/** @brief Clear the UART TX FIFO empty clear flag. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) + +/** @brief Check whether the specified UART flag is set or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __FLAG__ specifies the flag to check. + * This parameter can be one of the following values: + * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag + * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag + * @arg @ref UART_FLAG_RXFF RXFIFO Full flag + * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag + * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag + * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag + * @arg @ref UART_FLAG_WUF Wake up from stop mode flag + * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) + * @arg @ref UART_FLAG_SBKF Send Break flag + * @arg @ref UART_FLAG_CMF Character match flag + * @arg @ref UART_FLAG_BUSY Busy flag + * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag + * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag + * @arg @ref UART_FLAG_CTS CTS Change flag + * @arg @ref UART_FLAG_LBDF LIN Break detection flag + * @arg @ref UART_FLAG_TXE Transmit data register empty flag + * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag + * @arg @ref UART_FLAG_TC Transmission Complete flag + * @arg @ref UART_FLAG_RXNE Receive data register not empty flag + * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag + * @arg @ref UART_FLAG_RTOF Receiver Timeout flag + * @arg @ref UART_FLAG_IDLE Idle Line detection flag + * @arg @ref UART_FLAG_ORE Overrun Error flag + * @arg @ref UART_FLAG_NE Noise Error flag + * @arg @ref UART_FLAG_FE Framing Error flag + * @arg @ref UART_FLAG_PE Parity Error flag + * @retval The new state of __FLAG__ (TRUE or FALSE). + */ +#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) + +/** @brief Enable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to enable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Disable the specified UART interrupt. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to disable. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval None + */ +#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__INTERRUPT__) & UART_IT_MASK)))) + +/** @brief Check whether the specified UART interrupt has occurred or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ + & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) + +/** @brief Check whether the specified UART interrupt source is enabled or not. + * @param __HANDLE__ specifies the UART Handle. + * @param __INTERRUPT__ specifies the UART interrupt source to check. + * This parameter can be one of the following values: + * @arg @ref UART_IT_RXFF RXFIFO Full interrupt + * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt + * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt + * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt + * @arg @ref UART_IT_WUF Wakeup from stop mode interrupt + * @arg @ref UART_IT_CM Character match interrupt + * @arg @ref UART_IT_CTS CTS change interrupt + * @arg @ref UART_IT_LBD LIN Break detection interrupt + * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt + * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt + * @arg @ref UART_IT_TC Transmission complete interrupt + * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt + * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt + * @arg @ref UART_IT_RTO Receive Timeout interrupt + * @arg @ref UART_IT_IDLE Idle line detection interrupt + * @arg @ref UART_IT_PE Parity Error interrupt + * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) + * @retval The new state of __INTERRUPT__ (SET or RESET). + */ +#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (1U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + UART_IT_MASK))) != RESET) ? SET : RESET) + +/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set + * to clear the corresponding interrupt + * This parameter can be one of the following values: + * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag + * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag + * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag + * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag + * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag + * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag + * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag + * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag + * @arg @ref UART_CLEAR_CMF Character Match Clear Flag + * @arg @ref UART_CLEAR_WUF Wake Up from stop mode Clear Flag + * @retval None + */ +#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) + +/** @brief Set a specific UART request flag. + * @param __HANDLE__ specifies the UART Handle. + * @param __REQ__ specifies the request flag to set + * This parameter can be one of the following values: + * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request + * @arg @ref UART_SENDBREAK_REQUEST Send Break Request + * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request + * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request + * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request + * @retval None + */ +#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) + +/** @brief Enable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) + +/** @brief Disable the UART one bit sample method. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) + +/** @brief Enable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) + +/** @brief Disable UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) + +/** @brief Enable CTS flow control. + * @note This macro allows to enable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ + } while(0U) + +/** @brief Disable CTS flow control. + * @note This macro allows to disable CTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ + } while(0U) + +/** @brief Enable RTS flow control. + * @note This macro allows to enable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ + do{ \ + ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ + (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ + } while(0U) + +/** @brief Disable RTS flow control. + * @note This macro allows to disable RTS hardware flow control for a given UART instance, + * without need to call HAL_UART_Init() function. + * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. + * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need + * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : + * - UART instance should have already been initialised (through call of HAL_UART_Init() ) + * - macro could only be called when corresponding UART instance is disabled + * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable + * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). + * @param __HANDLE__ specifies the UART Handle. + * @retval None + */ +#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ + do{ \ + ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ + (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ + } while(0U) +/** + * @} + */ + +/* Private macros --------------------------------------------------------*/ +/** @defgroup UART_Private_Macros UART Private Macros + * @{ + */ +/** @brief Get UART clock division factor from clock prescaler value. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval UART clock division factor + */ +#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ + (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) + +/** @brief BRR division operation to set BRR register with LPUART. + * @param __PCLK__ LPUART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ + ) + +/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. + * @param __PCLK__ UART clock. + * @param __BAUD__ Baud rate set by the user. + * @param __CLOCKPRESCALER__ UART prescaler value. + * @retval Division result + */ +#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ + ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) + +/** @brief Check whether or not UART instance is Low Power UART. + * @param __HANDLE__ specifies the UART Handle. + * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) + */ +#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) + +/** @brief Check UART Baud rate. + * @param __BAUDRATE__ Baudrate specified by the user. + * The maximum Baud Rate is derived from the maximum clock on H5 (i.e. 250 MHz) + * divided by the smallest oversampling used on the USART (i.e. 8) + * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) + */ +#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U) + +/** @brief Check UART assertion time. + * @param __TIME__ 5-bit value assertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** @brief Check UART deassertion time. + * @param __TIME__ 5-bit value deassertion time. + * @retval Test result (TRUE or FALSE). + */ +#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) + +/** + * @brief Ensure that UART frame number of stop bits is valid. + * @param __STOPBITS__ UART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ + ((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_1_5) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that LPUART frame number of stop bits is valid. + * @param __STOPBITS__ LPUART frame number of stop bits. + * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) + */ +#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ + ((__STOPBITS__) == UART_STOPBITS_2)) + +/** + * @brief Ensure that UART frame parity is valid. + * @param __PARITY__ UART frame parity. + * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) + */ +#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ + ((__PARITY__) == UART_PARITY_EVEN) || \ + ((__PARITY__) == UART_PARITY_ODD)) + +/** + * @brief Ensure that UART hardware flow control is valid. + * @param __CONTROL__ UART hardware flow control. + * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) + */ +#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ + (((__CONTROL__) == UART_HWCONTROL_NONE) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS) || \ + ((__CONTROL__) == UART_HWCONTROL_CTS) || \ + ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) + +/** + * @brief Ensure that UART communication mode is valid. + * @param __MODE__ UART communication mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) + +/** + * @brief Ensure that UART state is valid. + * @param __STATE__ UART state. + * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) + */ +#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ + ((__STATE__) == UART_STATE_ENABLE)) + +/** + * @brief Ensure that UART oversampling is valid. + * @param __SAMPLING__ UART oversampling. + * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) + */ +#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ + ((__SAMPLING__) == UART_OVERSAMPLING_8)) + +/** + * @brief Ensure that UART frame sampling is valid. + * @param __ONEBIT__ UART frame sampling. + * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) + */ +#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ + ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) + +/** + * @brief Ensure that UART auto Baud rate detection mode is valid. + * @param __MODE__ UART auto Baud rate detection mode. + * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ + ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) + +/** + * @brief Ensure that UART receiver timeout setting is valid. + * @param __TIMEOUT__ UART receiver timeout setting. + * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) + */ +#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ + ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) + +/** @brief Check the receiver timeout value. + * @note The maximum UART receiver timeout value is 0xFFFFFF. + * @param __TIMEOUTVALUE__ receiver timeout value. + * @retval Test result (TRUE or FALSE) + */ +#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) + +/** + * @brief Ensure that UART LIN state is valid. + * @param __LIN__ UART LIN state. + * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) + */ +#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ + ((__LIN__) == UART_LIN_ENABLE)) + +/** + * @brief Ensure that UART LIN break detection length is valid. + * @param __LENGTH__ UART LIN break detection length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ + ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA TX state is valid. + * @param __DMATX__ UART DMA TX state. + * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) + */ +#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ + ((__DMATX__) == UART_DMA_TX_ENABLE)) + +/** + * @brief Ensure that UART DMA RX state is valid. + * @param __DMARX__ UART DMA RX state. + * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) + */ +#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ + ((__DMARX__) == UART_DMA_RX_ENABLE)) + +#endif /* HAL_DMA_MODULE_ENABLED */ +/** + * @brief Ensure that UART half-duplex state is valid. + * @param __HDSEL__ UART half-duplex state. + * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) + */ +#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ + ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) + +/** + * @brief Ensure that UART wake-up method is valid. + * @param __WAKEUP__ UART wake-up method . + * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) + */ +#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ + ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) + +/** + * @brief Ensure that UART request parameter is valid. + * @param __PARAM__ UART request parameter. + * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) + */ +#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ + ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ + ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ + ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ + ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) + +/** + * @brief Ensure that UART advanced features initialization is valid. + * @param __INIT__ UART advanced features initialization. + * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) + */ +#if defined(HAL_DMA_MODULE_ENABLED) +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#else +#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ + UART_ADVFEATURE_TXINVERT_INIT | \ + UART_ADVFEATURE_RXINVERT_INIT | \ + UART_ADVFEATURE_DATAINVERT_INIT | \ + UART_ADVFEATURE_SWAP_INIT | \ + UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ + UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ + UART_ADVFEATURE_MSBFIRST_INIT)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame TX inversion setting is valid. + * @param __TXINV__ UART frame TX inversion setting. + * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ + ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX inversion setting is valid. + * @param __RXINV__ UART frame RX inversion setting. + * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ + ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) + +/** + * @brief Ensure that UART frame data inversion setting is valid. + * @param __DATAINV__ UART frame data inversion setting. + * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) + */ +#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ + ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) + +/** + * @brief Ensure that UART frame RX/TX pins swap setting is valid. + * @param __SWAP__ UART frame RX/TX pins swap setting. + * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) + */ +#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ + ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) + +/** + * @brief Ensure that UART frame overrun setting is valid. + * @param __OVERRUN__ UART frame overrun setting. + * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) + */ +#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ + ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) + +/** + * @brief Ensure that UART auto Baud rate state is valid. + * @param __AUTOBAUDRATE__ UART auto Baud rate state. + * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) + */ +#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ + UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ + ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Ensure that UART DMA enabling or disabling on error setting is valid. + * @param __DMA__ UART DMA enabling or disabling on error setting. + * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) + */ +#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ + ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Ensure that UART frame MSB first setting is valid. + * @param __MSBFIRST__ UART frame MSB first setting. + * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) + */ +#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ + ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) + +/** + * @brief Ensure that UART stop mode state is valid. + * @param __STOPMODE__ UART stop mode state. + * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) + */ +#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ + ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) + +/** + * @brief Ensure that UART mute mode state is valid. + * @param __MUTE__ UART mute mode state. + * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) + */ +#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ + ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) + +/** + * @brief Ensure that UART wake-up selection is valid. + * @param __WAKE__ UART wake-up selection. + * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) + */ +#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ + ((__WAKE__) == UART_WAKEUP_ON_STARTBIT) || \ + ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) + +/** + * @brief Ensure that UART driver enable polarity is valid. + * @param __POLARITY__ UART driver enable polarity. + * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) + */ +#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ + ((__POLARITY__) == UART_DE_POLARITY_LOW)) + +/** + * @brief Ensure that UART Prescaler is valid. + * @param __CLOCKPRESCALER__ UART Prescaler value. + * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) + */ +#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) + +/** + * @} + */ + +/* Include UART HAL Extended module */ +#include "stm32h5xx_hal_uart_ex.h" + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); +void HAL_UART_MspInit(UART_HandleTypeDef *huart); +void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); + +/* Callbacks Register/UnRegister functions ***********************************/ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); + +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group2 IO operation functions + * @{ + */ + +/* IO operation functions *****************************************************/ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); +#endif /* HAL_DMA_MODULE_ENABLED */ +/* Transfer Abort functions */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); + +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); +void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); +void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions + * @{ + */ + +/* Peripheral Control functions ************************************************/ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @{ + */ + +/* Peripheral State and Errors functions **************************************************/ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** + * @} + */ + +/* Private functions -----------------------------------------------------------*/ +/** @addtogroup UART_Private_Functions UART Private Functions + * @{ + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout); +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_UART_H */ + diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h new file mode 100644 index 0000000..5a3343b --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h @@ -0,0 +1,437 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart_ex.h + * @author MCD Application Team + * @brief Header file of UART HAL Extended module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_HAL_UART_EX_H +#define STM32H5xx_HAL_UART_EX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal_def.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @addtogroup UARTEx + * @{ + */ + +/* Exported types ------------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Types UARTEx Exported Types + * @{ + */ + +/** + * @brief UART wake up from stop mode parameters + */ +typedef struct +{ + uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). + This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. + If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must + be filled up. */ + + uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. + This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ + + uint8_t Address; /*!< UART/USART node address (7-bit long max). */ +} UART_WakeUpTypeDef; + +/** + * @} + */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants + * @{ + */ + +/** @defgroup UARTEx_Word_Length UARTEx Word Length + * @{ + */ +#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ +#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ +#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ +/** + * @} + */ + +/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length + * @{ + */ +#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ +#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ +/** + * @} + */ + +/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode + * @brief UART FIFO mode + * @{ + */ +#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ +#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ +/** + * @} + */ + +/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level + * @brief UART TXFIFO threshold level + * @{ + */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ +/** + * @} + */ + +/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level + * @brief UART RXFIFO threshold level + * @{ + */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macros -----------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UARTEx_Exported_Functions + * @{ + */ + +/** @addtogroup UARTEx_Exported_Functions_Group1 + * @{ + */ + +/* Initialization and de-initialization functions ****************************/ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group2 + * @{ + */ + +void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); + +void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); +void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); + +/** + * @} + */ + +/** @addtogroup UARTEx_Exported_Functions_Group3 + * @{ + */ + +/* Peripheral Control functions **********************************************/ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); + +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); + +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); + +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#if defined(HAL_DMA_MODULE_ENABLED) +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +#endif /* HAL_DMA_MODULE_ENABLED */ + +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); + + +/** + * @} + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup UARTEx_Private_Macros UARTEx Private Macros + * @{ + */ + +/** @brief Report the UART clock source. + * @param __HANDLE__ specifies the UART Handle. + * @param __CLOCKSOURCE__ output variable. + * @retval UART clocking source, written in __CLOCKSOURCE__. + */ +#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx)) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == UART7) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART7; \ + } \ + else if((__HANDLE__)->Instance == UART8) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART8; \ + } \ + else if((__HANDLE__)->Instance == UART9) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART9; \ + } \ + else if((__HANDLE__)->Instance == USART10) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART10; \ + } \ + else if((__HANDLE__)->Instance == USART11) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART11; \ + } \ + else if((__HANDLE__)->Instance == UART12) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART12; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#elif (defined(STM32H523xx) || defined(STM32H533xx)) +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == UART4) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ + } \ + else if((__HANDLE__)->Instance == UART5) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ + } \ + else if((__HANDLE__)->Instance == USART6) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#else +#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ + do { \ + if((__HANDLE__)->Instance == USART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ + } \ + else if((__HANDLE__)->Instance == USART2) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ + } \ + else if((__HANDLE__)->Instance == USART3) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ + } \ + else if((__HANDLE__)->Instance == LPUART1) \ + { \ + (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ + } \ + else \ + { \ + (__CLOCKSOURCE__) = 0U; \ + } \ + } while(0U) +#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */ + + +/** @brief Report the UART mask to apply to retrieve the received data + * according to the word length and to the parity bits activation. + * @note If PCE = 1, the parity bit is not included in the data extracted + * by the reception API(). + * This masking operation is not carried out in the case of + * DMA transfers. + * @param __HANDLE__ specifies the UART Handle. + * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. + */ +#define UART_MASK_COMPUTATION(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x01FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x00FFU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + } \ + else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ + { \ + if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ + { \ + (__HANDLE__)->Mask = 0x007FU ; \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x003FU ; \ + } \ + } \ + else \ + { \ + (__HANDLE__)->Mask = 0x0000U; \ + } \ + } while(0U) + +/** + * @brief Ensure that UART frame length is valid. + * @param __LENGTH__ UART frame length. + * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) + */ +#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ + ((__LENGTH__) == UART_WORDLENGTH_8B) || \ + ((__LENGTH__) == UART_WORDLENGTH_9B)) + +/** + * @brief Ensure that UART wake-up address length is valid. + * @param __ADDRESS__ UART wake-up address length. + * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) + */ +#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ + ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) + +/** + * @brief Ensure that UART TXFIFO threshold level is valid. + * @param __THRESHOLD__ UART TXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) + +/** + * @brief Ensure that UART RXFIFO threshold level is valid. + * @param __THRESHOLD__ UART RXFIFO threshold level. + * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) + */ +#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ + ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) + +/** + * @} + */ + +/* Private functions ---------------------------------------------------------*/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_HAL_UART_EX_H */ + diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h deleted file mode 100644 index ce663d6..0000000 --- a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h +++ /dev/null @@ -1,788 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_ll_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32H5xx_LL_ICACHE_H -#define STM32H5xx_LL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32h5xx.h" - -/** @addtogroup STM32H5xx_LL_Driver - * @{ - */ - -#if defined(ICACHE) - -/** @defgroup ICACHE_LL ICACHE - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure - * @{ - */ - -/** - * @brief LL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ - - uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ - - uint32_t Size; /*!< Configures the region size. - This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ -} LL_ICACHE_RegionTypeDef; - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection - * @{ - */ -#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ -#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type - * @{ - */ -#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ -#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ -#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_ReadReg function - * @{ - */ -#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ -#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_WriteReg function - * @{ - */ -#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ -#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions - * @{ - */ -#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_EC_Region Remapped Region number - * @{ - */ -#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ -#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ -#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ -#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size - * @{ - */ -#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route - * @{ - */ -#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ -#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ -#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ICACHE register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ICACHE register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Enable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Disable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Disable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Disable(void) -{ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Return if ICACHE is enabled or not. - * @rmtoll CR EN LL_ICACHE_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); -} - -/** - * @brief Select the ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_SetMode - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) -{ - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); -} - -/** - * @brief Get the selected ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_GetMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) -{ - return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); -} - -/** - * @brief Invalidate the ICACHE. - * @note Until the BSYEND flag is set, the cache is bypassed. - * @rmtoll CR CACHEINV LL_ICACHE_Invalidate - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Invalidate(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_Monitors Monitors - * @{ - */ - -/** - * @brief Enable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) -{ - SET_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Disable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) -{ - CLEAR_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Check if the monitor(s) is(are) enabled or disabled. - * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors - * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval State of parameter value (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) -{ - return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); -} - -/** - * @brief Reset the hit/miss monitor(s). - * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors - * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) -{ - /* Reset */ - SET_BIT(ICACHE->CR, (Monitors << 2U)); - /* Release reset */ - CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); -} - -/** - * @brief Get the Hit monitor. - * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. - * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Miss monitor. - * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. - * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Disable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Check if the BSYEND Interrupt is enabled or disabled. - * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Disable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Check if the ERR Interrupt is enabled or disabled. - * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Indicate the status of an ongoing operation flag. - * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an operation end flag. - * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an error flag. - * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear busy end of operation flag. - * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); -} - -/** - * @brief Clear error flag. - * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); -} - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management - * @{ - */ - -/** - * @brief Enable the remapped memory region. - * @note The region must have been already configured. - * @rmtoll CRRx REN LL_ICACHE_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) -{ - SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Disable the remapped memory region. - * @rmtoll CRRx REN LL_ICACHE_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) -{ - CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Return if remapped memory region is enabled or not. - * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); -} - -/** - * @brief Select the memory remapped region base address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Alias address in the Code region - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); -} - -/** - * @brief Get the memory remapped region base address. - * @note The base address is the alias in the Code region. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Alias address in the Code region - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR) << 21U); -} - -/** - * @brief Select the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Memory address to remap - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); -} - -/** - * @brief Get the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Remapped memory address - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); -} - -/** - * @brief Select the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); -} - -/** - * @brief Get the selected the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); -} - -/** - * @brief Select the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Type This parameter can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST, Type); -} - -/** - * @brief Get the selected the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST)); -} - -/** - * @brief Select the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Port This parameter can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL, Port); -} - -/** - * @brief Get the selected the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions - * @{ - */ - -void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -#endif /* ICACHE_CRRx_REN */ -/** - * @} - */ - -/** - * @} - */ - -#endif /* ICACHE */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32H5xx_LL_ICACHE_H */ diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h new file mode 100644 index 0000000..c195e2e --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_lpuart.h @@ -0,0 +1,2662 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_lpuart.h + * @author MCD Application Team + * @brief Header file of LPUART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_LPUART_H +#define STM32H5xx_LL_LPUART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined (LPUART1) + +/** @defgroup LPUART_LL LPUART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables + * @{ + */ +/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ +static const uint16_t LPUART_PRESCALER_TAB[] = +{ + (uint16_t)1, + (uint16_t)2, + (uint16_t)4, + (uint16_t)6, + (uint16_t)8, + (uint16_t)10, + (uint16_t)12, + (uint16_t)16, + (uint16_t)32, + (uint16_t)64, + (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256 +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants + * @{ + */ +/* Defines used in Baud Rate related macros and corresponding register setting computation */ +#define LPUART_LPUARTDIV_FREQ_MUL 256U +#define LPUART_BRR_MASK 0x000FFFFFU +#define LPUART_BRR_MIN_VALUE 0x00000300U +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures + * @{ + */ + +/** + * @brief LL LPUART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref LPUART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_LPUART_SetHWFlowCtrl().*/ + +} LL_LPUART_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants + * @{ + */ + +/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_LPUART_WriteReg function + * @{ + */ +#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_LPUART_ReadReg function + * @{ + */ +#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions + * @{ + */ +#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty + interrupt enable */ +#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO + not full interrupt enable */ +#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DIRECTION Direction + * @{ + */ +#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ +#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ + USART_PRESC_PRESCALER_1 |\ + USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received + in positive/direct logic. (1=H, 0=L) */ +#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received + in negative/inverse logic. (1=L, 0=H). + The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, + following the start bit */ +#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, + following the start bit */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested + when there is space in the receive buffer */ +#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted + when the nCTS input is asserted (tied to 0)*/ +#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros + * @{ + */ + +/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in LPUART register + * @param __INSTANCE__ LPUART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros + * @{ + */ + +/** + * @brief Compute LPUARTDIV value according to Peripheral Clock and + * expected Baud Rate (20-bit value of LPUARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud Rate value to achieve + * @retval LPUARTDIV value to be used for BRR register filling + */ +#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ + ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ + * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions + * @{ + */ + +/** @defgroup LPUART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief LPUART Enable + * @rmtoll CR1 UE LL_LPUART_Enable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief LPUART Disable + * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the LPUART is kept, but all the status + * flags, in the LPUARTx_ISR are set to their default values. + * @note In order to go into low-power mode without generating errors on the line, + * the TE bit must be reset before and the software must wait + * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. + * The DMA requests are also reset when UE = 0 so the DMA channel must + * be disabled before resetting the UE bit. + * @rmtoll CR1 UE LL_LPUART_Disable + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if LPUART is enabled + * @rmtoll CR1 UE LL_LPUART_IsEnabled + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold + * @param LPUARTx LPUART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief LPUART enabled in STOP Mode + * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that + * LPUART clock selection is HSI or LSE in RCC. + * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief LPUART disabled in STOP Mode + * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode + * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if LPUART is enabled in STOP Mode + * (able to wake up MCU from Stop mode or not) + * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n + * CR1 TE LL_LPUART_SetTransferDirection + * @param LPUARTx LPUART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n + * CR1 TE LL_LPUART_GetTransferDirection + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DIRECTION_NONE + * @arg @ref LL_LPUART_DIRECTION_RX + * @arg @ref LL_LPUART_DIRECTION_TX + * @arg @ref LL_LPUART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled) + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_LPUART_SetParity\n + * CR1 PCE LL_LPUART_SetParity + * @param LPUARTx LPUART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_LPUART_GetParity\n + * CR1 PCE LL_LPUART_GetParity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod + * @param LPUARTx LPUART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_IDLELINE + * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_SetDataWidth + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_LPUART_GetDataWidth + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_LPUART_EnableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_LPUART_DisableMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler + * @param LPUARTx LPUART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength + * @param LPUARTx LPUART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function + * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n + * CR1 PCE LL_LPUART_ConfigCharacter\n + * CR1 M LL_LPUART_ConfigCharacter\n + * CR2 STOP LL_LPUART_ConfigCharacter + * @param LPUARTx LPUART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_LPUART_DATAWIDTH_7B + * @arg @ref LL_LPUART_DATAWIDTH_8B + * @arg @ref LL_LPUART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_LPUART_PARITY_NONE + * @arg @ref LL_LPUART_PARITY_EVEN + * @arg @ref LL_LPUART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_LPUART_STOPBITS_1 + * @arg @ref LL_LPUART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap + * @param LPUARTx LPUART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXRX_STANDARD + * @arg @ref LL_LPUART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel + * @param LPUARTx LPUART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder + * @param LPUARTx LPUART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_BITORDER_LSBFIRST + * @arg @ref LL_LPUART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Set Address of the LPUART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n + * CR2 ADDM7 LL_LPUART_ConfigNodeAddress + * @param LPUARTx LPUART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the LPUART node. + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress + * @param LPUARTx LPUART Instance + * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_ADDRESS_DETECT_4B + * @arg @ref LL_LPUART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_SetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n + * CR3 CTSE LL_LPUART_GetHWFlowCtrl + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_HWCONTROL_NONE + * @arg @ref LL_LPUART_HWCONTROL_RTS + * @arg @ref LL_LPUART_HWCONTROL_CTS + * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_SetWKUPType + * @param LPUARTx LPUART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @rmtoll CR3 WUS LL_LPUART_GetWKUPType + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS + * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT + * @arg @ref LL_LPUART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure LPUART BRR register for achieving expected Baud Rate value. + * + * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock and expected Baud Rate values + * @note Peripheral clock and Baud Rate values provided as function parameters should be valid + * (Baud rate value != 0). + * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, + * a care should be taken when generating high baud rates using high PeriphClk + * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. + * @rmtoll BRR BRR LL_LPUART_SetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t BaudRate) +{ + if (BaudRate != 0U) + { + LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); + } +} + +/** + * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_LPUART_GetBaudRate + * @param LPUARTx LPUART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_LPUART_PRESCALER_DIV1 + * @arg @ref LL_LPUART_PRESCALER_DIV2 + * @arg @ref LL_LPUART_PRESCALER_DIV4 + * @arg @ref LL_LPUART_PRESCALER_DIV6 + * @arg @ref LL_LPUART_PRESCALER_DIV8 + * @arg @ref LL_LPUART_PRESCALER_DIV10 + * @arg @ref LL_LPUART_PRESCALER_DIV12 + * @arg @ref LL_LPUART_PRESCALER_DIV16 + * @arg @ref LL_LPUART_PRESCALER_DIV32 + * @arg @ref LL_LPUART_PRESCALER_DIV64 + * @arg @ref LL_LPUART_PRESCALER_DIV128 + * @arg @ref LL_LPUART_PRESCALER_DIV256 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, + uint32_t PrescalerValue) +{ + uint32_t lpuartdiv; + uint32_t brrresult; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); + + lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; + + if (lpuartdiv >= LPUART_BRR_MIN_VALUE) + { + brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); + } + else + { + brrresult = 0x0UL; + } + + return (brrresult); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : c + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime + * @param LPUARTx LPUART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) +{ + MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime + * @param LPUARTx LPUART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_EnableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @rmtoll CR3 DEM LL_LPUART_DisableDEMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity + * @param LPUARTx LPUART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) +{ + MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity + * @param LPUARTx LPUART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LPUART_DE_POLARITY_HIGH + * @arg @ref LL_LPUART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) +{ + return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the LPUART Parity Error Flag is set or not + * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Framing Error Flag is set or not + * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not + * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not + * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS interrupt Flag is set or not + * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Flag is set or not + * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Busy Flag is set or not + * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Flag is set or not + * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from stop mode Flag is set or not + * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Flag is set or not + * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Flag is set or not + * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Threshold Flag is set or not + * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Threshold Flag is set or not + * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise detected Flag + * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) +{ + WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); +} + +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). + * - 0: Interrupt is inhibited + * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. + * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled + * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled + * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled + * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART CTS Interrupt is enabled or disabled. + * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled + * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) +{ + ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) +{ + CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr + * @param LPUARTx LPUART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) +{ + return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the LPUART data register address used for DMA transfer + * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr + * @param LPUARTx LPUART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(LPUARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData8 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) +{ + return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_LPUART_ReceiveData9 + * @param LPUARTx LPUART Instance + * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) +{ + return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData8 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) +{ + LPUARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_LPUART_TransmitData9 + * @param LPUARTx LPUART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) +{ + LPUARTx->TDR = Value & 0x1FFUL; +} + +/** + * @} + */ + +/** @defgroup LPUART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put LPUART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); +ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); +void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* LPUART1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_LPUART_H */ + diff --git a/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h new file mode 100644 index 0000000..389f0ae --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_usart.h @@ -0,0 +1,4405 @@ +/** + ****************************************************************************** + * @file stm32h5xx_ll_usart.h + * @author MCD Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef STM32H5xx_LL_USART_H +#define STM32H5xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx.h" + +/** @addtogroup STM32H5xx_LL_Driver + * @{ + */ + +#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) || defined(USART6) \ + || defined(UART7) || defined(UART8) || defined(UART9) || defined(USART10) || defined(USART11) || defined(UART12) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Variables USART Private Variables + * @{ + */ +/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ +static const uint32_t USART_PRESCALER_TAB[] = +{ + 1UL, + 2UL, + 4UL, + 6UL, + 8UL, + 10UL, + 12UL, + 16UL, + 32UL, + 64UL, + 128UL, + 256UL, + 256UL, + 256UL, + 256UL, + 256UL +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. + This parameter can be a value of @ref USART_LL_EC_PRESCALER. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetPrescaler().*/ + + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary + function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary + functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_USART_WriteReg function + * @{ + */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ +#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ +#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ +#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ +#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ +#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ +#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ +#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ +#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ +#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ +#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ +#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ +#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ +#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ +#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ +#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ +#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ +#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ +#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ +#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ +#define LL_USART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ +#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ +#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ +#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ +#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ +#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ +#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ +#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ +#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ +#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ +#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ +#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +#define LL_USART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ +#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ +#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ +#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold + * @{ + */ +#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ +#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ +#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ +#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler + * @{ + */ +#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ +#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ +#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ +#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ +#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ +#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ +#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ +#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ +#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ +#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ +#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ +#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap + * @{ + */ +#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ +#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion + * @{ + */ +#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ +#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion + * @{ + */ +#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ +#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion + * @{ + */ +#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ +#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_BITORDER Bit Order + * @{ + */ +#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ +#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection + * @{ + */ +#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ +#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ +#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ +#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection + * @{ + */ +#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ +#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation + * @{ + */ +#define LL_USART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ +#define LL_USART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ +#define LL_USART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power + * @{ + */ +#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ +#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length + * @{ + */ +#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ +#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity + * @{ + */ +#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ +#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data + * @{ + */ +#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ +#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_ISR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); +} + +/** + * @brief FIFO Mode Enable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief FIFO Mode Disable + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); +} + +/** + * @brief Indicate if FIFO Mode is enabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); +} + +/** + * @brief Configure TX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Return TX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); +} + +/** + * @brief Configure RX FIFO Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold + * @param USARTx USART Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Return RX FIFO Threshold Configuration + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); +} + +/** + * @brief Configure TX and RX FIFOs Threshold + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n + * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold + * @param USARTx USART Instance + * @param TXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @param RXThreshold This parameter can be one of the following values: + * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 + * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 + * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 + * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) +{ + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); +} + +/** + * @brief USART enabled in STOP Mode. + * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that + * USART clock selection is HSI or LSE in RCC. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_EnableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief USART disabled in STOP Mode. + * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_DisableInStopMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); +} + +/** + * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_SetDataWidth\n + * CR1 M1 LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M0 LL_USART_GetDataWidth\n + * CR1 M1 LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +/** + * @brief Allow switch between Mute Mode and Active mode + * @rmtoll CR1 MME LL_USART_EnableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. + * @rmtoll CR1 MME LL_USART_DisableMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); +} + +/** + * @brief Indicate if switch between Mute Mode and Active mode is allowed + * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); +} + +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); +} + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Configure Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler + * @param USARTx USART Instance + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); +} + +/** + * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M0 LL_USART_ConfigCharacter\n + * CR1 M1 LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_7B + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_0_5 + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_1_5 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Configure TX/RX pins swapping setting. + * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap + * @param USARTx USART Instance + * @param SwapConfig This parameter can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); +} + +/** + * @brief Retrieve TX/RX pins swapping configuration. + * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXRX_STANDARD + * @arg @ref LL_USART_TXRX_SWAPPED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); +} + +/** + * @brief Configure RX pin active level logic + * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); +} + +/** + * @brief Retrieve RX pin active level logic configuration + * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); +} + +/** + * @brief Configure TX pin active level logic + * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel + * @param USARTx USART Instance + * @param PinInvMethod This parameter can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); +} + +/** + * @brief Retrieve TX pin active level logic configuration + * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD + * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED + */ +__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); +} + +/** + * @brief Configure Binary data logic. + * @note Allow to define how Logical data from the data register are send/received : + * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) + * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic + * @param USARTx USART Instance + * @param DataLogic This parameter can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); +} + +/** + * @brief Retrieve Binary data configuration + * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE + * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE + */ +__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); +} + +/** + * @brief Configure transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder + * @param USARTx USART Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); +} + +/** + * @brief Return transfer bit order (either Less or Most Significant Bit First) + * @note MSB First means data is transmitted/received with the MSB first, following the start bit. + * LSB First means data is transmitted/received with data bit 0 first, following the start bit. + * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_BITORDER_LSBFIRST + * @arg @ref LL_USART_BITORDER_MSBFIRST + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); +} + +/** + * @brief Enable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Disable Auto Baud-Rate Detection + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); +} + +/** + * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); +} + +/** + * @brief Set Auto Baud-Rate mode bits + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode + * @param USARTx USART Instance + * @param AutoBaudRateMode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); +} + +/** + * @brief Return Auto Baud-Rate mode + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME + * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); +} + +/** + * @brief Enable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Disable Receiver Timeout + * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); +} + +/** + * @brief Indicate if Receiver Timeout feature is enabled + * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. + * (b7-b4 should be set to 0) + * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. + * (This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with 7-bit address mark detection. + * The MSB of the character sent by the transmitter should be equal to 1. + * It may also be used for character detection during normal reception, + * Mute mode inactive (for example, end of block detection in ModBus protocol). + * In this case, the whole received character (8-bit) is compared to the ADD[7:0] + * value and CMF flag is set on match) + * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n + * CR2 ADDM7 LL_USART_ConfigNodeAddress + * @param USARTx USART Instance + * @param AddressLen This parameter can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + * @param NodeAddress 4 or 7 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, + (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); +} + +/** + * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. + * @note If 4-bit Address Detection is selected in ADDM7, + * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * If 7-bit Address Detection is selected in ADDM7, + * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); +} + +/** + * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) + * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_ADDRESS_DETECT_4B + * @arg @ref LL_USART_ADDRESS_DETECT_7B + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Enable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Disable One bit sampling method + * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); +} + +/** + * @brief Indicate if One bit sampling method is enabled + * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); +} + +/** + * @brief Enable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Disable Overrun detection + * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); +} + +/** + * @brief Indicate if Overrun detection is enabled + * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); +} + +/** + * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_SetWKUPType + * @param USARTx USART Instance + * @param Type This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type); +} + +/** + * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUS LL_USART_GetWKUPType + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_ON_ADDRESS + * @arg @ref LL_USART_WAKEUP_ON_STARTBIT + * @arg @ref LL_USART_WAKEUP_ON_RXNE + */ +__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS)); +} + +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling, + uint32_t BaudRate) +{ + uint32_t usartdiv; + uint32_t brrtemp; + + if (PrescalerValue > LL_USART_PRESCALER_DIV256) + { + /* Do not overstep the size of USART_PRESCALER_TAB */ + } + else if (BaudRate == 0U) + { + /* Can Not divide per 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + brrtemp = usartdiv & 0xFFF0U; + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + USARTx->BRR = brrtemp; + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param PrescalerValue This parameter can be one of the following values: + * @arg @ref LL_USART_PRESCALER_DIV1 + * @arg @ref LL_USART_PRESCALER_DIV2 + * @arg @ref LL_USART_PRESCALER_DIV4 + * @arg @ref LL_USART_PRESCALER_DIV6 + * @arg @ref LL_USART_PRESCALER_DIV8 + * @arg @ref LL_USART_PRESCALER_DIV10 + * @arg @ref LL_USART_PRESCALER_DIV12 + * @arg @ref LL_USART_PRESCALER_DIV16 + * @arg @ref LL_USART_PRESCALER_DIV32 + * @arg @ref LL_USART_PRESCALER_DIV64 + * @arg @ref LL_USART_PRESCALER_DIV128 + * @arg @ref LL_USART_PRESCALER_DIV256 + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, + uint32_t OverSampling) +{ + uint32_t usartdiv; + uint32_t brrresult = 0x0U; + uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); + + usartdiv = USARTx->BRR; + + if (usartdiv == 0U) + { + /* Do not perform a division by 0 */ + } + else if (OverSampling == LL_USART_OVERSAMPLING_8) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + if (usartdiv != 0U) + { + brrresult = (periphclkpresc * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = periphclkpresc / usartdiv; + } + } + return (brrresult); +} + +/** + * @brief Set Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_SetRxTimeout + * @param USARTx USART Instance + * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); +} + +/** + * @brief Get Receiver Time Out Value (expressed in nb of bits duration) + * @rmtoll RTOR RTO LL_USART_GetRxTimeout + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF + */ +__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); +} + +/** + * @brief Set Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_SetBlockLength + * @param USARTx USART Instance + * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) +{ + MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); +} + +/** + * @brief Get Block Length value in reception + * @rmtoll RTOR BLEN LL_USART_GetBlockLength + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature + * @{ + */ + +/** + * @brief Enable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_EnableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Disable IrDA mode + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_DisableIrda + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Indicate if IrDA mode is enabled + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IREN LL_USART_IsEnabledIrda + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); +} + +/** + * @brief Configure IrDA Power Mode (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode + * @param USARTx USART Instance + * @param PowerMode This parameter can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_IRDA_POWER_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); +} + +/** + * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_IRDA_POWER_NORMAL + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); +} + +/** + * @brief Set Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Irda prescaler value, used for dividing the USART clock source + * to achieve the Irda Low Power frequency (8 bits value) + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler + * @param USARTx USART Instance + * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature + * @{ + */ + +/** + * @brief Enable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Disable Smartcard NACK transmission + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); +} + +/** + * @brief Indicate if Smartcard NACK transmission is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); +} + +/** + * @brief Enable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_EnableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Disable Smartcard mode + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_DisableSmartcard + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Indicate if Smartcard mode is enabled + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); +} + +/** + * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. + * In transmission mode, it specifies the number of automatic retransmission retries, before + * generating a transmission error (FE bit set). + * In reception mode, it specifies the number or erroneous reception trials, before generating a + * reception error (RXNE and PE bits set) + * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount + * @param USARTx USART Instance + * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); +} + +/** + * @brief Set Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler + * @param USARTx USART Instance + * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); +} + +/** + * @brief Return Smartcard prescaler value, used for dividing the USART clock + * source to provide the SMARTCARD Clock (5 bits value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler + * @param USARTx USART Instance + * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); +} + +/** + * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime + * @param USARTx USART Instance + * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) +{ + MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); +} + +/** + * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods + * (GT[7:0] bits : Guard time value) + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime + * @param USARTx USART Instance + * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) + */ +__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature + * @{ + */ +/** + * @brief Enable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Disable SPI Synchronous Slave mode + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); +} + +/** + * @brief Indicate if SPI Synchronous Slave mode is enabled + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave Selection depends on NSS input pin + * (The slave is selected when NSS is low and deselected when NSS is high). + * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Disable SPI Slave Selection using NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @note SPI Slave will be always selected and NSS input pin will be ignored. + * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); +} + +/** + * @brief Indicate if SPI Slave Selection depends on NSS input pin + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature + * @{ + */ + +/** + * @brief Set LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen + * @param USARTx USART Instance + * @param LINBDLength This parameter can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); +} + +/** + * @brief Return LIN Break Detection Length + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LINBREAK_DETECT_10B + * @arg @ref LL_USART_LINBREAK_DETECT_11B + */ +__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); +} + +/** + * @brief Enable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_EnableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Disable LIN mode + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_DisableLIN + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Indicate if LIN mode is enabled + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature + * @{ + */ + +/** + * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); +} + +/** + * @brief Return DEDT (Driver Enable De-Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); +} + +/** + * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime + * @param USARTx USART Instance + * @param Time Value between Min_Data=0 and Max_Data=31 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); +} + +/** + * @brief Return DEAT (Driver Enable Assertion Time) + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime + * @param USARTx USART Instance + * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 + */ +__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); +} + +/** + * @brief Enable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_EnableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Disable Driver Enable (DE) Mode + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_DisableDEMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); +} + +/** + * @brief Indicate if Driver Enable (DE) Mode is enabled + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); +} + +/** + * @brief Select Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity + * @param USARTx USART Instance + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); +} + +/** + * @brief Return Driver Enable Polarity + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * Driver Enable feature is supported by the USARTx instance. + * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DE_POLARITY_HIGH + * @arg @ref LL_USART_DE_POLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n + * CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 SCEN LL_USART_ConfigAsyncMode\n + * CR3 IREN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - LINEN, CLKEN bits in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n + * CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 SCEN LL_USART_ConfigSyncMode\n + * CR3 IREN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in LIN Mode + * @note In LIN mode, the following bits must be kept cleared: + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also set the UART/USART in LIN mode. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function + * @note Other remaining configurations items related to LIN Mode + * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n + * CR2 STOP LL_USART_ConfigLINMode\n + * CR2 LINEN LL_USART_ConfigLINMode\n + * CR3 IREN LL_USART_ConfigLINMode\n + * CR3 SCEN LL_USART_ConfigLINMode\n + * CR3 HDSEL LL_USART_ConfigLINMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) +{ + /* In LIN mode, the following bits must be kept cleared: + - STOP and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); + /* Set the UART/USART in LIN mode */ + SET_BIT(USARTx->CR2, USART_CR2_LINEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n + * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n + * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n + * CR3 IREN LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Smartcard Mode + * @note In Smartcard mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also configures Stop bits to 1.5 bits and + * sets the USART in Smartcard mode (SCEN bit). + * Clock Output is also enabled (CLKEN). + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function + * @note Other remaining configurations items related to Smartcard Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n + * CR2 STOP LL_USART_ConfigSmartcardMode\n + * CR2 CLKEN LL_USART_ConfigSmartcardMode\n + * CR3 HDSEL LL_USART_ConfigSmartcardMode\n + * CR3 SCEN LL_USART_ConfigSmartcardMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) +{ + /* In Smartcard mode, the following bits must be kept cleared: + - LINEN bit in the USART_CR2 register, + - IREN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); + /* Configure Stop bits to 1.5 bits */ + /* Synchronous mode is activated by default */ + SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); + /* set the UART/USART in Smartcard mode */ + SET_BIT(USARTx->CR3, USART_CR3_SCEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Irda Mode + * @note In IRDA mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - STOP and CLKEN bits in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * This function also sets the UART/USART in IRDA mode (IREN bit). + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * IrDA feature is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function + * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function + * @note Other remaining configurations items related to Irda Mode + * (as Baud Rate, Word length, Power mode, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n + * CR2 CLKEN LL_USART_ConfigIrdaMode\n + * CR2 STOP LL_USART_ConfigIrdaMode\n + * CR3 SCEN LL_USART_ConfigIrdaMode\n + * CR3 HDSEL LL_USART_ConfigIrdaMode\n + * CR3 IREN LL_USART_ConfigIrdaMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) +{ + /* In IRDA mode, the following bits must be kept cleared: + - LINEN, STOP and CLKEN bits in the USART_CR2 register, + - SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); + /* set the UART/USART in IRDA mode */ + SET_BIT(USARTx->CR3, USART_CR3_IREN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - LINEN bit in the USART_CR2 register, + * - CLKEN bit in the USART_CR2 register, + * - SCEN bit in the USART_CR3 register, + * - IREN bit in the USART_CR3 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function + * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n + * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 SCEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n + * CR3 IREN LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ + CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll ISR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll ISR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll ISR NE LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll ISR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); +} + +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Flag is set or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS interrupt Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Time Out Flag is set or not + * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Flag is set or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the SPI Slave Underrun error flag is set or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Error Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Auto-Baud Rate Flag is set or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Busy Flag is set or not + * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Flag is set or not + * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from stop mode Flag is set or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not + * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receive Enable Acknowledge Flag is set or not + * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not + * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Threshold Flag is set or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); +} + +/** + * @brief Clear Parity Error Flag + * @rmtoll ICR PECF LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_PECF); +} + +/** + * @brief Clear Framing Error Flag + * @rmtoll ICR FECF LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_FECF); +} + +/** + * @brief Clear Noise Error detected Flag + * @rmtoll ICR NECF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_NECF); +} + +/** + * @brief Clear OverRun Error Flag + * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_ORECF); +} + +/** + * @brief Clear IDLE line detected Flag + * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); +} + +/** + * @brief Clear TX FIFO Empty Flag + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll ICR TCCF LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCCF); +} + +/** + * @brief Clear Smartcard Transmission Complete Before Guard Time Flag + * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); +} + +/** + * @brief Clear LIN Break Detection Flag + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); +} + +/** + * @brief Clear Receiver Time Out Flag + * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); +} + +/** + * @brief Clear End Of Block Flag + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); +} + +/** + * @brief Clear SPI Slave Underrun Flag + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * SPI Slave mode feature is supported by the USARTx instance. + * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); +} + +/** + * @brief Clear Character Match Flag + * @rmtoll ICR CMCF LL_USART_ClearFlag_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_CMCF); +} + +/** + * @brief Clear Wake Up from stop mode Flag + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->ICR, USART_ICR_WUCF); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Enable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_EnableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Enable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Enable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Enable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Enable RX FIFO Full Interrupt + * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Enable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Enable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Enable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Enable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Disable TX Empty and TX FIFO Not Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Character Match Interrupt + * @rmtoll CR1 CMIE LL_USART_DisableIT_CM + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); +} + +/** + * @brief Disable Receiver Timeout Interrupt + * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); +} + +/** + * @brief Disable End Of Block Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); +} + +/** + * @brief Disable TX FIFO Empty Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); +} + +/** + * @brief Disable RX FIFO Full Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); +} + +/** + * @brief Disable LIN Break Detection Interrupt + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable Wake Up from Stop Mode Interrupt + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE); +} + +/** + * @brief Disable TX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); +} + +/** + * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); +} + +/** + * @brief Disable RX FIFO Threshold Interrupt + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); +} + +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ + +/** + * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Character Match Interrupt is enabled or disabled. + * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. + * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART End Of Block Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * LIN feature is supported by the USARTx instance. + * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * Wake-up from Stop mode feature is supported by the USARTx instance. + * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * Smartcard feature is supported by the USARTx instance. + * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Disable DMA Disabling on Reception Error + * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); +} + +/** + * @brief Indicate if DMA Disabling on Reception Error is disabled + * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) +{ + return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); +} + +/** + * @brief Get the data register address used for DMA transfer + * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n + * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr + * @param USARTx USART Instance + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT + * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) +{ + uint32_t data_reg_addr; + + if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) + { + /* return address of TDR register */ + data_reg_addr = (uint32_t) &(USARTx->TDR); + } + else + { + /* return address of RDR register */ + data_reg_addr = (uint32_t) &(USARTx->RDR); + } + + return data_reg_addr; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll RDR RDR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll TDR TDR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->TDR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll TDR TDR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->TDR = (uint16_t)(Value & 0x1FFUL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request an Automatic Baud Rate measurement on next received data frame + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * Auto Baud Rate detection feature is supported by the USARTx instance. + * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); +} + +/** + * @brief Request Break sending + * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); +} + +/** + * @brief Put USART in mute mode and set the RWU flag + * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); +} + +/** + * @brief Request a Receive Data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @note Allows to discard the received data without reading them, and avoid an overrun + * condition. + * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); +} + +/** + * @brief Request a Transmit data and FIFO flush + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 || USART6 + || UART7 || UART8 || UART9 || USART10 || USART11 || UART12 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* STM32H5xx_LL_USART_H */ + diff --git a/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c b/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c deleted file mode 100644 index 4ce76ea..0000000 --- a/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c +++ /dev/null @@ -1,657 +0,0 @@ -/** - ****************************************************************************** - * @file stm32h5xx_hal_icache.c - * @author MCD Application Team - * @brief ICACHE HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Instruction Cache (ICACHE). - * + Initialization and Configuration - * + Invalidate functions - * + Monitoring management - * + Memory address remap management - ****************************************************************************** - * @attention - * - * Copyright (c) 2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ICACHE main features ##### - ============================================================================== - [..] - The Instruction Cache (ICACHE) is introduced on C-AHB code bus of - Cortex-M33 processor to improve performance when fetching instruction - and data from both internal and external memories. It allows close to - zero wait states performance. - - (+) The ICACHE provides two performance counters (Hit and Miss), - cache invalidate maintenance operation, error management and TrustZone - security support. - - (+) The ICACHE provides additionally the possibility to remap input address - falling into up to four memory regions (used to remap aliased code in - external memories to the internal Code region, for execution) - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The ICACHE HAL driver can be used as follows: - - (#) Optionally configure the Instruction Cache mode with - HAL_ICACHE_ConfigAssociativityMode() if the default configuration - does not suit the application requirements. - - (#) Enable and disable the Instruction Cache with respectively - HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). - Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. - To ensure a deterministic cache behavior after power on, system reset or after - a call to @ref HAL_ICACHE_Disable(), the application must call - @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset - or cache disable, an automatic cache invalidation procedure is launched and the - cache is bypassed until the operation completes. - - (#) Initiate the cache maintenance invalidation procedure with either - HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() - (interrupt mode). When interrupt mode is used, the callback function - HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate - procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() - may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). - The cache operation is bypassed during the invalidation procedure. - - (#) Use the performance monitoring counters for Hit and Miss with the following - functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), - HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and - HAL_ICACHE_Monitor_GetMissValue() - - (#) Enable and disable up to four regions to remap input address from external - memories to the internal Code region for execution with - HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32h5xx_hal.h" - -/** @addtogroup STM32H5xx_HAL_Driver - * @{ - */ - -/** @defgroup ICACHE ICACHE - * @brief HAL ICACHE module driver - * @{ - */ -#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants - * @{ - */ -#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ -#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ICACHE_Private_Macros ICACHE Private Macros - * @{ - */ - -#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ - ((__MODE__) == ICACHE_2WAYS)) - -#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ - ((__TYPE__) == ICACHE_MONITOR_HIT) || \ - ((__TYPE__) == ICACHE_MONITOR_MISS)) - -#if defined(ICACHE_CRRx_REN) -#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) - -#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) - -#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ - ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) - -#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ - ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) - -#endif /* ICACHE_CRRx_REN */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions - * @brief Initialization and control functions - * - @verbatim - ============================================================================== - ##### Initialization and control functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize and control the - Instruction Cache (mode, invalidate procedure, performance counters). - @endverbatim - * @{ - */ - -/** - * @brief Configure the Instruction Cache cache associativity mode selection. - * @param AssociativityMode Associativity mode selection - * This parameter can be one of the following values: - * @arg ICACHE_1WAY 1-way cache (direct mapped cache) - * @arg ICACHE_2WAYS 2-ways set associative cache (default) - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); - } - - return status; -} - -/** - * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_DeInit(void) -{ - /* Reset interrupt enable value */ - WRITE_REG(ICACHE->IER, 0U); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - /* Disable cache then set default associative mode value */ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); - - /* Stop monitor and reset monitor values */ - CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); - SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - -#if defined(ICACHE_CRRx_REN) - /* Reset regions configuration values */ - WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); -#endif /* ICACHE_CRRx_REN */ - - return HAL_OK; -} - -/** - * @brief Enable the Instruction Cache. - * @note This function always returns HAL_OK even if there is any ongoing - * cache operation. The Instruction Cache is bypassed until the - * cache operation completes. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); - - return HAL_OK; -} - -/** - * @brief Disable the Instruction Cache. - * @note This function waits for the cache being disabled but - * not for the end of the automatic cache invalidation procedure. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Disable(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Make sure BSYENDF is reset before to disable the instruction cache */ - /* as it automatically starts a cache invalidation procedure */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for instruction cache being disabled */ - while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Check whether the Instruction Cache is enabled or not. - * @retval Status (0: disabled, 1: enabled) - */ -uint32_t HAL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); -} - -/** - * @brief Invalidate the Instruction Cache. - * @note This function waits for the end of cache invalidation procedure - * and clears the associated BSYENDF flag. - * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) -{ - HAL_StatusTypeDef status; - - /* Check if no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) - { - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - status = HAL_ICACHE_WaitForInvalidateComplete(); - - return status; -} - -/** - * @brief Invalidate the Instruction Cache with interrupt. - * @note This function launches cache invalidation and returns. - * User application shall resort to interrupt generation to check - * the end of the cache invalidation with the BSYENDF flag and the - * HAL_ICACHE_InvalidateCompleteCallback() callback. - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Enable end of cache invalidation interrupt */ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - return status; -} - -/** - * @brief Wait for the end of the Instruction Cache invalidate procedure. - * @note This function checks and clears the BSYENDF flag when set. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Check if ongoing invalidation operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for end of cache invalidation */ - while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - } - - /* Clear BSYENDF */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - return status; -} - - -/** - * @brief Start the Instruction Cache performance monitoring. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - SET_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Stop the Instruction Cache performance monitoring. - * @note Stopping the monitoring does not reset the values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - CLEAR_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Reset the Instruction Cache performance monitoring values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - /* Force/Release reset */ - SET_BIT(ICACHE->CR, (MonitorType << 2U)); - CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); - - return HAL_OK; -} - -/** - * @brief Get the Instruction Cache performance Hit monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Hit monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetHitValue(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Instruction Cache performance Miss monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Miss monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetMissValue(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions - * @brief IRQ and callback functions - * - @verbatim - ============================================================================== - ##### IRQ and callback functions ##### - ============================================================================== - [..] - This section provides functions allowing to handle ICACHE global interrupt - and the associated callback functions. - @endverbatim - * @{ - */ - -/** - * @brief Handle the Instruction Cache interrupt request. - * @note This function should be called under the ICACHE_IRQHandler(). - * @note This function respectively disables the interrupt and clears the - * flag of any pending flag before calling the associated user callback. - * @retval None - */ -void HAL_ICACHE_IRQHandler(void) -{ - /* Get current interrupt flags and interrupt sources value */ - uint32_t itflags = READ_REG(ICACHE->SR); - uint32_t itsources = READ_REG(ICACHE->IER); - - /* Check Instruction cache Error interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) - { - /* Disable error interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); - - /* Clear ERR pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); - - /* Instruction cache error interrupt user callback */ - HAL_ICACHE_ErrorCallback(); - } - - /* Check Instruction cache BusyEnd interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) - { - /* Disable end of cache invalidation interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Clear BSYENDF pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Instruction cache busyend interrupt user callback */ - HAL_ICACHE_InvalidateCompleteCallback(); - } -} - -/** - * @brief Cache invalidation complete callback. - */ -__weak void HAL_ICACHE_InvalidateCompleteCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file - */ -} - -/** - * @brief Error callback. - */ -__weak void HAL_ICACHE_ErrorCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_ErrorCallback() should be implemented in the user file - */ -} - -/** - * @} - */ - -#if defined(ICACHE_CRRx_REN) -/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions - * @brief Memory remapped regions functions - * - @verbatim - ============================================================================== - ##### Memory remapped regions functions ##### - ============================================================================== - [..] - This section provides functions allowing to manage the remapping of - external memories to internal Code for execution. - @endverbatim - * @{ - */ - -/** - * @brief Configure and enable a region for memory remapping. - * @note The Instruction Cache and the region must be disabled. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - uint32_t value; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); - assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); - assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - /* Check region is not already enabled */ - if ((*p_reg & ICACHE_CRRx_REN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ - /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ - /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ - /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ - /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ - /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ - /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ - value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ - (0xFFU & ~(pRegionConfig->Size - 1U)); - value |= ((pRegionConfig->RemapAddress >> 5U) & \ - ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); - value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ - pRegionConfig->OutputBurstType; - *p_reg = (value | ICACHE_CRRx_REN); - } - } - - return status; -} - -/** - * @brief Disable the memory remapping for a predefined region. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - *p_reg &= ~ICACHE_CRRx_REN; - } - - return status; -} - - -/** - * @} - */ -#endif /* ICACHE_CRRx_REN */ - -/** - * @} - */ - -#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c b/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c new file mode 100644 index 0000000..0520304 --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c @@ -0,0 +1,4880 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart.c + * @author MCD Application Team + * @brief UART HAL module driver. + * This file provides firmware functions to manage the following + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + IO operation functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + =============================================================================== + ##### How to use this driver ##### + =============================================================================== + [..] + The UART HAL driver can be used as follows: + + (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). + (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: + (++) Enable the USARTx interface clock. + (++) UART pins configuration: + (+++) Enable the clock for the UART GPIOs. + (+++) Configure these UART pins as alternate function pull-up. + (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() + and HAL_UART_Receive_IT() APIs): + (+++) Configure the USARTx interrupt priority. + (+++) Enable the NVIC USART IRQ handle. + (++) UART interrupts handling: + -@@- The specific UART interrupts (Transmission complete interrupt, + RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) + are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() + inside the transmit and receive processes. + (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() + and HAL_UART_Receive_DMA() APIs): + (+++) Declare a DMA handle structure for the Tx/Rx channel. + (+++) Enable the DMAx interface clock. + (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. + (+++) Configure the DMA Tx/Rx channel. + (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. + (+++) Configure the priority and enable the NVIC for the transfer complete + interrupt on the DMA Tx/Rx channel. + + (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware + flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. + + (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) + in the huart handle AdvancedInit structure. + + (#) For the UART asynchronous mode, initialize the UART registers by calling + the HAL_UART_Init() API. + + (#) For the UART Half duplex mode, initialize the UART registers by calling + the HAL_HalfDuplex_Init() API. + + (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers + by calling the HAL_LIN_Init() API. + + (#) For the UART Multiprocessor mode, initialize the UART registers + by calling the HAL_MultiProcessor_Init() API. + + (#) For the UART RS485 Driver Enabled mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + [..] + (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), + also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by + calling the customized HAL_UART_MspInit() API. + + ##### Callback registration ##### + ================================== + + [..] + The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 + allows the user to configure dynamically the driver callbacks. + + [..] + Use Function HAL_UART_RegisterCallback() to register a user callback. + Function HAL_UART_RegisterCallback() allows to register following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + This function takes as parameters the HAL peripheral handle, the Callback ID + and a pointer to the user callback function. + + [..] + Use function HAL_UART_UnRegisterCallback() to reset a callback to the default + weak function. + HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, + and the Callback ID. + This function allows to reset following callbacks: + (+) TxHalfCpltCallback : Tx Half Complete Callback. + (+) TxCpltCallback : Tx Complete Callback. + (+) RxHalfCpltCallback : Rx Half Complete Callback. + (+) RxCpltCallback : Rx Complete Callback. + (+) ErrorCallback : Error Callback. + (+) AbortCpltCallback : Abort Complete Callback. + (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. + (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. + (+) WakeupCallback : Wakeup Callback. + (+) RxFifoFullCallback : Rx Fifo Full Callback. + (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. + (+) MspInitCallback : UART MspInit. + (+) MspDeInitCallback : UART MspDeInit. + + [..] + For specific callback RxEventCallback, use dedicated registration/reset functions: + respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). + + [..] + By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET + all callbacks are set to the corresponding weak functions: + examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). + Exception done for MspInit and MspDeInit functions that are respectively + reset to the legacy weak functions in the HAL_UART_Init() + and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). + If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() + keep and use the user MspInit/MspDeInit callbacks (registered beforehand). + + [..] + Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. + Exception done MspInit/MspDeInit that can be registered/unregistered + in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) + MspInit/DeInit callbacks can be used during the Init/DeInit. + In that case first register the MspInit/MspDeInit user callbacks + using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() + or HAL_UART_Init() function. + + [..] + When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or + not defined, the callback registration feature is not available + and weak callbacks are used. + + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup UART UART + * @brief HAL UART module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UART_Private_Constants UART Private Constants + * @{ + */ +#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ + USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ + +#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ + USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ + +#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ +#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ + +#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ +#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @addtogroup UART_Private_Functions + * @{ + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart); +#if defined(HAL_DMA_MODULE_ENABLED) +static void UART_EndTxTransfer(UART_HandleTypeDef *huart); +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); +static void UART_DMAError(DMA_HandleTypeDef *hdma); +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); +#endif /* HAL_DMA_MODULE_ENABLED */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Private variables ---------------------------------------------------------*/ +/** @addtogroup UART_Private_variables + * @{ + */ +const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; +/** + * @} + */ + +/* Exported Constants --------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UART_Exported_Functions UART Exported Functions + * @{ + */ + +/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Initialization and Configuration functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API + follow respectively the UART asynchronous, UART Half duplex, UART LIN mode + and UART multiprocessor mode configuration procedures (details for the procedures + are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the UART mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) + { + /* Check the parameters */ + assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); + } + else + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Initialize the half-duplex mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check UART instance */ + assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In half-duplex mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the LIN mode according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param BreakDetectLength Specifies the LIN break detection length. + * This parameter can be one of the following values: + * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection + * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the LIN UART instance */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + /* Check the Break detection length parameter */ + assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); + + /* LIN mode limited to 16-bit oversampling only */ + if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + return HAL_ERROR; + } + /* LIN mode limited to 8-bit data length */ + if (huart->Init.WordLength != UART_WORDLENGTH_8B) + { + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In LIN mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); + + /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ + SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); + + /* Set the USART LIN Break detection length. */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief Initialize the multiprocessor mode according to the specified + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod Specifies the UART wakeup method. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection + * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark + * @note If the user resorts to idle line detection wake up, the Address parameter + * is useless and ignored by the initialization function. + * @note If the user resorts to address mark wake up, the address length detection + * is configured by default to 4 bits only. For the UART to be able to + * manage 6-, 7- or 8-bit long addresses detection, the API + * HAL_MultiProcessorEx_AddressLength_Set() must be called after + * HAL_MultiProcessor_Init(). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the wake up method parameter */ + assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* In multiprocessor mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + + if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) + { + /* If address mark wake up method is chosen, set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); + } + + /* Set the wake up method by setting the WAKE bit in the CR1 register */ + MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); + + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + + +/** + * @brief DeInitialize the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + + huart->gState = HAL_UART_STATE_BUSY; + + __HAL_UART_DISABLE(huart); + + huart->Instance->CR1 = 0x0U; + huart->Instance->CR2 = 0x0U; + huart->Instance->CR3 = 0x0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + if (huart->MspDeInitCallback == NULL) + { + huart->MspDeInitCallback = HAL_UART_MspDeInit; + } + /* DeInit the low level hardware */ + huart->MspDeInitCallback(huart); +#else + /* DeInit the low level hardware */ + HAL_UART_MspDeInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_RESET; + huart->RxState = HAL_UART_STATE_RESET; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Initialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspInit can be implemented in the user file + */ +} + +/** + * @brief DeInitialize the UART MSP. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_MspDeInit can be implemented in the user file + */ +} + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +/** + * @brief Register a User UART Callback + * To be used to override the weak predefined callback + * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be registered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @param pCallback pointer to the Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, + pUART_CallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->gState == HAL_UART_STATE_READY) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = pCallback; + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = pCallback; + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = pCallback; + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = pCallback; + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = pCallback; + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = pCallback; + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = pCallback; + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = pCallback; + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = pCallback; + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = pCallback; + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (huart->gState == HAL_UART_STATE_RESET) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = pCallback; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = pCallback; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Unregister an UART Callback + * UART callaback is redirected to the weak predefined callback + * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), + * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register + * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID + * @param huart uart handle + * @param CallbackID ID of the callback to be unregistered + * This parameter can be one of the following values: + * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID + * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID + * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID + * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID + * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID + * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID + * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID + * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID + * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID + * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID + * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID + * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID + * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (HAL_UART_STATE_READY == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_TX_HALFCOMPLETE_CB_ID : + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + break; + + case HAL_UART_TX_COMPLETE_CB_ID : + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + break; + + case HAL_UART_RX_HALFCOMPLETE_CB_ID : + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + break; + + case HAL_UART_RX_COMPLETE_CB_ID : + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + break; + + case HAL_UART_ERROR_CB_ID : + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + break; + + case HAL_UART_ABORT_COMPLETE_CB_ID : + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + break; + + case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak + AbortTransmitCpltCallback */ + break; + + case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak + AbortReceiveCpltCallback */ + break; + + case HAL_UART_WAKEUP_CB_ID : + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + break; + + case HAL_UART_RX_FIFO_FULL_CB_ID : + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + break; + + case HAL_UART_TX_FIFO_EMPTY_CB_ID : + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + break; + + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else if (HAL_UART_STATE_RESET == huart->gState) + { + switch (CallbackID) + { + case HAL_UART_MSPINIT_CB_ID : + huart->MspInitCallback = HAL_UART_MspInit; + break; + + case HAL_UART_MSPDEINIT_CB_ID : + huart->MspDeInitCallback = HAL_UART_MspDeInit; + break; + + default : + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + break; + } + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief Register a User UART Rx Event Callback + * To be used instead of the weak predefined callback + * @param huart Uart handle + * @param pCallback Pointer to the Rx Event Callback function + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (pCallback == NULL) + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + return HAL_ERROR; + } + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = pCallback; + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +/** + * @brief UnRegister the UART Rx Event Callback + * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback + * @param huart Uart handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) +{ + HAL_StatusTypeDef status = HAL_OK; + + if (huart->RxState == HAL_UART_STATE_READY) + { + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ + } + else + { + huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; + + status = HAL_ERROR; + } + + return status; +} + +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group2 IO operation functions + * @brief UART Transmit/Receive functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to manage the UART asynchronous + and Half duplex data transfers. + + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + + (#) Blocking mode API's are : + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() + + (#) Non-Blocking mode API's with Interrupt are : + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() + + (#) Non-Blocking mode API's with DMA are : + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() + + (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() + + (#) Non-Blocking mode transfers could be aborted using Abort API's : + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() + + (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() + + (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced + reception services: + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + + (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. + Errors are handled as follows : + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. + + -@- In the Half duplex communication, it is forbidden to run the transmit + and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. + +@endverbatim + * @{ + */ + +/** + * @brief Send an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @note When FIFO mode is enabled, writing a data in the TDR register adds one + * data to the TXFIFO. Write operations to the TDR register are performed + * when TXFNF flag is set. From hardware perspective, TXFNF flag and + * TXE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + const uint8_t *pdata8bits; + const uint16_t *pdata16bits; + uint32_t tickstart; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (const uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + while (huart->TxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) + { + + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); + pdata16bits++; + } + else + { + huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); + pdata8bits++; + } + huart->TxXferCount--; + } + + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) + { + huart->gState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in blocking mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + huart->RxXferCount--; + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Send an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + huart->TxISR = NULL; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + + /* Configure Tx interrupt processing */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT_FIFOEN; + } + else + { + huart->TxISR = UART_TxISR_8BIT_FIFOEN; + } + + /* Enable the TX FIFO threshold interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + } + else + { + /* Set the Tx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->TxISR = UART_TxISR_16BIT; + } + else + { + huart->TxISR = UART_TxISR_8BIT; + } + + /* Enable the Transmit Data Register Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + } + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Send an amount of data in DMA mode. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the sent data is handled as a set of u16. In this case, Size must indicate the number + * of u16 provided through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + huart->pTxBuffPtr = pData; + huart->TxXferSize = Size; + huart->TxXferCount = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->gState = HAL_UART_STATE_BUSY_TX; + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; + + /* Set DMA destination address */ + huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->TDR; + + /* Enable the UART transmit DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmatx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART transmit DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in DMA mode. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of u16. In this case, Size must indicate the number + * of u16 available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + return (UART_Start_Receive_DMA(huart, pData, Size)); + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Pause the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) +{ + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmatx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Set the UART DMA Suspend callback to Null. + No call back execution at end of DMA Suspend procedure */ + huart->hdmarx->XferSuspendCallback = NULL; + + if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + return HAL_OK; +} + +/** + * @brief Resume the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) +{ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + /* Resume the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + /* Clear the Overrun flag before resuming the Rx transfer */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Resume the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_ERROR; + } + } + } + + return HAL_OK; +} + +/** + * @brief Stop the DMA Transfer. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) +{ + /* The Lock is not implemented on this API to allow the user application + to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / + HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: + indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete + interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of + the stream and the corresponding call back is executed. */ + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + + /* Abort the UART DMA Tx channel */ + if (huart->hdmatx != NULL) + { + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + + UART_EndRxTransfer(huart); + } + + return HAL_OK; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Abort ongoing transfers (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) +{ + /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) +{ + /* Disable TCIE, TXEIE and TXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (blocking mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) + * - Set handle State to READY + * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) +{ + /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback to Null. + No call back execution at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = NULL; + + if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) + { + if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + return HAL_TIMEOUT; + } + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + return HAL_OK; +} + +/** + * @brief Abort ongoing transfers (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx and Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) +{ + uint32_t abortcplt = 1U; + + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised + before any call to DMA Abort functions */ + /* DMA Tx Handle is valid */ + if (huart->hdmatx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { + huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; + } + else + { + huart->hdmatx->XferAbortCallback = NULL; + } + } + /* DMA Rx Handle is valid */ + if (huart->hdmarx != NULL) + { + /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. + Otherwise, set it to NULL */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; + } + else + { + huart->hdmarx->XferAbortCallback = NULL; + } + } + + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable DMA Tx at UART level */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* UART Tx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + huart->hdmatx->XferAbortCallback = NULL; + } + else + { + abortcplt = 0U; + } + } + } + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* UART Rx DMA Abort callback has already been initialised : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + huart->hdmarx->XferAbortCallback = NULL; + abortcplt = 1U; + } + else + { + abortcplt = 0U; + } + } + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ + if (abortcplt == 1U) + { + /* Reset Tx and Rx transfer counters */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Transmit transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Tx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Tx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Tx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmatx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; + + /* Abort DMA TX */ + if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) + { + /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ + huart->hdmatx->XferAbortCallback(huart->hdmatx); + } + } + else + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Tx transfer counter */ + huart->TxXferCount = 0U; + + /* Clear TxISR function pointers */ + huart->TxISR = NULL; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Abort ongoing Receive transfer (Interrupt mode). + * @param huart UART handle. + * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. + * This procedure performs following operations : + * - Disable UART Interrupts (Rx) + * - Disable the DMA transfer in the peripheral register (if enabled) + * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) + * - Set handle State to READY + * - At abort completion, call user abort complete callback + * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be + * considered as completed only when user abort complete callback is executed (not when exiting function). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Reset Rx transfer counter */ + huart->RxXferCount = 0U; + + /* Clear RxISR function pointer */ + huart->pRxBuffPtr = NULL; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* As no DMA to be aborted, call directly user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + + return HAL_OK; +} + +/** + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + if (errorflags == 0U) + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + return; + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + { + if (huart->RxISR != NULL) + { + huart->RxISR(huart); + } + } + + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + } + } + else + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + + } + } + else +#endif /* HAL_DMA_MODULE_ENABLED */ + { + /* Call user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + else + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + return; + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + && ((isrflags & USART_ISR_IDLE) != 0U) + && ((cr1its & USART_ISR_IDLE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + +#if defined(HAL_DMA_MODULE_ENABLED) + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + if ((nb_remaining_rx_data > 0U) + && (nb_remaining_rx_data < huart->RxXferSize)) + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (huart->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } + return; + } + else + { +#endif /* HAL_DMA_MODULE_ENABLED */ + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + if ((huart->RxXferCount > 0U) + && (nb_rx_data > 0U)) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; +#if defined(HAL_DMA_MODULE_ENABLED) + } +#endif /* HAL_DMA_MODULE_ENABLED */ + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + + /* UART Rx state is not reset as a reception process might be ongoing. + If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */ + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + { + if (huart->TxISR != NULL) + { + huart->TxISR(huart); + } + return; + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + { + UART_EndTransmit_IT(huart); + return; + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + } +} + +/** + * @brief Tx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_TxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_RxCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Rx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_RxHalfCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief UART Abort Receive Complete callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. + */ +} + +/** + * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). + * @param huart UART handle + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions + * @brief UART control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to control the UART. + (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly + (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature + (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature + (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode + (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode + (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode + (+) UART_SetConfig() API configures the UART peripheral + (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features + (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization + (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter + (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver + (+) HAL_LIN_SendBreak() API transmits the break characters +@endverbatim + * @{ + */ + +/** + * @brief Update on the fly the receiver timeout value in RTOR register. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout + * value must be less or equal to 0x0FFFFFFFF. + * @retval None + */ +void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); + MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); + } +} + +/** + * @brief Enable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Set the USART RTOEN bit */ + SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Disable the UART receiver timeout feature. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) +{ + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + if (huart->gState == HAL_UART_STATE_READY) + { + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear the USART RTOEN bit */ + CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; + } + else + { + return HAL_BUSY; + } + } + else + { + return HAL_ERROR; + } +} + +/** + * @brief Enable UART in mute mode (does not mean UART enters mute mode; + * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Enable USART mute mode by setting the MME bit in the CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Disable UART mute mode (does not mean the UART actually exits mute mode + * as it may not have been in mute mode at this very moment). + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable USART mute mode by clearing the MME bit in the CR1 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); + + huart->gState = HAL_UART_STATE_READY; + + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Enter UART mute mode (means UART actually enters mute mode). + * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. + * @param huart UART handle. + * @retval None + */ +void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) +{ + __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); +} + +/** + * @brief Enable the UART transmitter and disable the UART receiver. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the UART receiver and disable the UART transmitter. + * @param huart UART handle. + * @retval HAL status. + */ +HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) +{ + __HAL_LOCK(huart); + huart->gState = HAL_UART_STATE_BUSY; + + /* Clear TE and RE bits */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); + + /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + + +/** + * @brief Transmit break characters. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) +{ + /* Check the parameters */ + assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); + + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Send break characters */ + __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @} + */ + +/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions + * @brief UART Peripheral State functions + * +@verbatim + ============================================================================== + ##### Peripheral State and Error functions ##### + ============================================================================== + [..] + This subsection provides functions allowing to : + (+) Return the UART handle state. + (+) Return the UART handle error code + +@endverbatim + * @{ + */ + +/** + * @brief Return the UART handle state. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval HAL state + */ +HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) +{ + uint32_t temp1; + uint32_t temp2; + temp1 = huart->gState; + temp2 = huart->RxState; + + return (HAL_UART_StateTypeDef)(temp1 | temp2); +} + +/** + * @brief Return the UART handle error code. + * @param huart Pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART. + * @retval UART Error Code + */ +uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) +{ + return huart->ErrorCode; +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup UART_Private_Functions UART Private Functions + * @{ + */ + +/** + * @brief Initialize the callbacks to their default values. + * @param huart UART handle. + * @retval none + */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) +void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) +{ + /* Init the UART Callback settings */ + huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ + huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ + huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ + huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ + huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ + huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ + huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ + huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ + huart->WakeupCallback = HAL_UARTEx_WakeupCallback; /* Legacy weak WakeupCallback */ + huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ + huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ + huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ + +} +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + +/** + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + uint32_t tmpreg; + uint16_t brrtemp; + uint32_t clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + uint32_t lpuart_ker_ck_pres; + uint32_t pclk; + + /* Check the parameters */ + assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); + assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); + if (UART_INSTANCE_LOWPOWER(huart)) + { + assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); + } + else + { + assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); + assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); + } + + assert_param(IS_UART_PARITY(huart->Init.Parity)); + assert_param(IS_UART_MODE(huart->Init.Mode)); + assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); + assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); + assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); + + /*-------------------------- USART CR1 Configuration -----------------------*/ + /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + + /*-------------------------- USART CR3 Configuration -----------------------*/ + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + + if (!(UART_INSTANCE_LOWPOWER(huart))) + { + tmpreg |= huart->Init.OneBitSampling; + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + { + /* Retrieve frequency clock */ + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* If proper clock source reported */ + if (pclk != 0U) + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + { + ret = HAL_ERROR; + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + { + huart->Instance->BRR = usartdiv; + } + else + { + ret = HAL_ERROR; + } + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + huart->Instance->BRR = brrtemp; + } + else + { + ret = HAL_ERROR; + } + } + } + else + { + pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); + + if (pclk != 0U) + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + { + huart->Instance->BRR = (uint16_t)usartdiv; + } + else + { + ret = HAL_ERROR; + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + huart->NbRxDataToProcess = 1; + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + huart->TxISR = NULL; + + return ret; +} + +/** + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + } + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + } + +#if defined(HAL_DMA_MODULE_ENABLED) + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + } +#endif /* HAL_DMA_MODULE_ENABLED */ + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + } +} + +/** + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable TXE interrupt for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); + + huart->gState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + huart->RxState = HAL_UART_STATE_READY; + + __HAL_UNLOCK(huart); + + /* Timeout occurred */ + return HAL_TIMEOUT; + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief This function handles UART Communication Timeout. It waits + * until a flag is no longer in the specified status. + * @param huart UART handle. + * @param Flag Specifies the UART flag to check + * @param Status The actual Flag status (SET or RESET) + * @param Tickstart Tick start value + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + { + + return HAL_TIMEOUT; + } + + if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) + { + /* Clear Overrun Error flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_ORE; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_ERROR; + } + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts if ongoing */ + UART_EndRxTransfer(huart); + + huart->ErrorCode = HAL_UART_ERROR_RTO; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_TIMEOUT; + } + } + } + } + return HAL_OK; +} + +/** + * @brief Start Receive operation in interrupt mode. + * @note This function could be called by all HAL UART API providing reception in Interrupt mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + huart->RxXferCount = Size; + huart->RxISR = NULL; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + huart->RxISR = UART_RxISR_16BIT; + } + else + { + huart->RxISR = UART_RxISR_8BIT; + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + return HAL_OK; +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Start Receive operation in DMA mode. + * @note This function could be called by all HAL UART API providing reception in DMA mode. + * @note When calling this function, parameters validity is considered as already checked, + * i.e. Rx State, buffer address, ... + * UART Handle is assumed as Locked. + * @param huart UART handle. + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + uint16_t nbByte = Size; + + huart->pRxBuffPtr = pData; + huart->RxXferSize = Size; + + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + + if (huart->hdmarx != NULL) + { + /* Set the UART DMA transfer complete callback */ + huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; + + /* Set the DMA error callback */ + huart->hdmarx->XferErrorCallback = UART_DMAError; + + /* Set the DMA abort callback */ + huart->hdmarx->XferAbortCallback = NULL; + + /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter + should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + nbByte = Size * 2U; + } + + /* Check linked list mode */ + if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) + { + if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) + { + /* Set DMA data size */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; + + /* Set DMA source address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = + (uint32_t)&huart->Instance->RDR; + + /* Set DMA destination address */ + huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; + + /* Enable the UART receive DMA channel */ + status = HAL_DMAEx_List_Start_IT(huart->hdmarx); + } + else + { + /* Update status */ + status = HAL_ERROR; + } + } + else + { + /* Enable the UART receive DMA channel */ + status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); + } + + if (status != HAL_OK) + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + + /* Restore huart->RxState to ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_ERROR; + } + } + + /* Enable the UART Parity Error Interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + } + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Enable the DMA transfer for the receiver request by setting the DMAR bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); + + return HAL_OK; +} + + +/** + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; +} +#endif /* HAL_DMA_MODULE_ENABLED */ + + +/** + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; +} + + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->TxXferCount = 0U; + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + /* DMA Circular mode */ + else + { +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART receive process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Check if DMA in circular mode */ + if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) + { + huart->RxXferCount = 0U; + + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + +#if !defined(USART_DMAREQUESTS_SW_WA) + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + +#endif /* !USART_DMAREQUESTS_SW_WA */ + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = 0; + + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART receive process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Half Transfer */ + huart->RxEventType = HAL_UART_RXEVENT_HT; + + /* Check current reception Mode : + If Reception till IDLE event has been selected : use Rx Event callback */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + else + { + /* In other cases : use Rx Half Complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Half complete callback*/ + huart->RxHalfCpltCallback(huart); +#else + /*Call legacy weak Rx Half complete callback*/ + HAL_UART_RxHalfCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + +/** + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + const HAL_UART_StateTypeDef gstate = huart->gState; + const HAL_UART_StateTypeDef rxstate = huart->RxState; + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + UART_EndTxTransfer(huart); + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + UART_EndRxTransfer(huart); + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART communication abort callback, when initiated by HAL services on Error + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + huart->RxXferCount = 0U; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user + * (To be called at end of DMA Tx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Rx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmatx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmarx != NULL) + { + if (huart->hdmarx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user + * (To be called at end of DMA Rx Abort procedure following user abort request). + * @note When this callback is executed, User Abort complete call back is called only if no + * Abort still ongoing for Tx DMA Handle. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->hdmarx->XferAbortCallback = NULL; + + /* Check if an Abort process is still ongoing */ + if (huart->hdmatx != NULL) + { + if (huart->hdmatx->XferAbortCallback != NULL) + { + return; + } + } + + /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ + huart->TxXferCount = 0U; + huart->RxXferCount = 0U; + + /* Reset errorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->gState and huart->RxState to Ready */ + huart->gState = HAL_UART_STATE_READY; + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort complete callback */ + huart->AbortCpltCallback(huart); +#else + /* Call legacy weak Abort complete callback */ + HAL_UART_AbortCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + + +/** + * @brief DMA UART Tx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) + * (This callback is executed at end of DMA Tx Abort procedure following user abort request, + * and leads to user Tx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + + huart->TxXferCount = 0U; + + /* Flush the whole TX FIFO (if needed) */ + if (huart->FifoMode == UART_FIFOMODE_ENABLE) + { + __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); + } + + /* Restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Transmit Complete Callback */ + huart->AbortTransmitCpltCallback(huart); +#else + /* Call legacy weak Abort Transmit Complete Callback */ + HAL_UART_AbortTransmitCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief DMA UART Rx communication abort callback, when initiated by user by a call to + * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) + * (This callback is executed at end of DMA Rx Abort procedure following user abort request, + * and leads to user Rx Abort Complete callback execution). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) +{ + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; + + huart->RxXferCount = 0U; + + /* Clear the Error flags in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); + + /* Discard the received data */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + + /* Restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Call user Abort complete callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Abort Receive Complete Callback */ + huart->AbortReceiveCpltCallback(huart); +#else + /* Call legacy weak Abort Receive Complete Callback */ + HAL_UART_AbortReceiveCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) +{ + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + if (huart->TxXferCount == 0U) + { + /* Disable the UART Transmit Data Register Empty Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + } + else + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + } +} + +/** + * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); + huart->pTxBuffPtr++; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Transmit_IT(). + * @param huart UART handle. + * @retval None + */ +static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + const uint16_t *tmp; + uint16_t nb_tx_data; + + /* Check that a Tx process is ongoing */ + if (huart->gState == HAL_UART_STATE_BUSY_TX) + { + for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) + { + if (huart->TxXferCount == 0U) + { + /* Disable the TX FIFO threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + break; /* force exit loop */ + } + else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) + { + tmp = (const uint16_t *) huart->pTxBuffPtr; + huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); + huart->pTxBuffPtr += 2U; + huart->TxXferCount--; + } + else + { + /* Nothing to do */ + } + } + } +} + +/** + * @brief Wrap up transmission in non-blocking mode. + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length . + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + huart->pRxBuffPtr++; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. + * @note Function is called under interruption only, once + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + uint32_t cr1its = READ_REG(huart->Instance->CR1); + uint32_t cr3its = READ_REG(huart->Instance->CR3); + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + nb_rx_data = huart->NbRxDataToProcess; + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + tmp = (uint16_t *) huart->pRxBuffPtr ; + *tmp = (uint16_t)(uhdata & uhMask); + huart->pRxBuffPtr += 2U; + huart->RxXferCount--; + isrflags = READ_REG(huart->Instance->ISR); + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + + huart->ErrorCode |= HAL_UART_ERROR_PE; + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + + huart->ErrorCode |= HAL_UART_ERROR_FE; + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + + huart->ErrorCode |= HAL_UART_ERROR_NE; + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + { + /* Non Blocking error : transfer could go on. + Error is notified to user through user error callback */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + } + } + + if (huart->RxXferCount == 0U) + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + } + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + else + { + /* Standard reception API called */ +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } + break; + } + } + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + } + } + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ +/** + * @} + */ + +/** + * @} + */ + diff --git a/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c b/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c new file mode 100644 index 0000000..bf5efdb --- /dev/null +++ b/Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c @@ -0,0 +1,1056 @@ +/** + ****************************************************************************** + * @file stm32h5xx_hal_uart_ex.c + * @author MCD Application Team + * @brief Extended UART HAL module driver. + * This file provides firmware functions to manage the following extended + * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). + * + Initialization and de-initialization functions + * + Peripheral Control functions + * + * + ****************************************************************************** + * @attention + * + * Copyright (c) 2023 STMicroelectronics. + * All rights reserved. + * + * This software is licensed under terms that can be found in the LICENSE file + * in the root directory of this software component. + * If no LICENSE file comes with this software, it is provided AS-IS. + * + ****************************************************************************** + @verbatim + ============================================================================== + ##### UART peripheral extended features ##### + ============================================================================== + [..] + (#) Declare a UART_HandleTypeDef handle structure. + + (#) For the UART RS485 Driver Enable mode, initialize the UART registers + by calling the HAL_RS485Ex_Init() API. + + (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. + + -@- When UART operates in FIFO mode, FIFO mode must be enabled prior + starting RX/TX transfers. Also RX/TX FIFO thresholds must be + configured prior starting RX/TX transfers. + + @endverbatim + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "stm32h5xx_hal.h" + +/** @addtogroup STM32H5xx_HAL_Driver + * @{ + */ + +/** @defgroup UARTEx UARTEx + * @brief UART Extended HAL module driver + * @{ + */ + +#ifdef HAL_UART_MODULE_ENABLED + +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/** @defgroup UARTEX_Private_Constants UARTEx Private Constants + * @{ + */ +/* UART RX FIFO depth */ +#define RX_FIFO_DEPTH 8U + +/* UART TX FIFO depth */ +#define TX_FIFO_DEPTH 8U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup UARTEx_Private_Functions UARTEx Private Functions + * @{ + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions + * @{ + */ + +/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions + * @brief Extended Initialization and Configuration Functions + * +@verbatim +=============================================================================== + ##### Initialization and Configuration functions ##### + =============================================================================== + [..] + This subsection provides a set of functions allowing to initialize the USARTx or the UARTy + in asynchronous mode. + (+) For the asynchronous mode the parameters below can be configured: + (++) Baud Rate + (++) Word Length + (++) Stop Bit + (++) Parity: If the parity is enabled, then the MSB bit of the data written + in the data register is transmitted but is changed by the parity bit. + (++) Hardware flow control + (++) Receiver/transmitter modes + (++) Over Sampling Method + (++) One-Bit Sampling Method + (+) For the asynchronous mode, the following advanced features can be configured as well: + (++) TX and/or RX pin level inversion + (++) data logical level inversion + (++) RX and TX pins swap + (++) RX overrun detection disabling + (++) DMA disabling on RX error + (++) MSB first on communication line + (++) auto Baud rate detection + [..] + The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration + procedures (details for the procedures are available in reference manual). + +@endverbatim + + Depending on the frame length defined by the M1 and M0 bits (7-bit, + 8-bit or 9-bit), the possible UART formats are listed in the + following table. + + Table 1. UART frame format. + +-----------------------------------------------------------------------+ + | M1 bit | M0 bit | PCE bit | UART frame | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 0 | | SB | 8 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 0 | | SB | 9 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 0 | | SB | 7 bit data | STB | | + |---------|---------|-----------|---------------------------------------| + | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | + +-----------------------------------------------------------------------+ + + * @{ + */ + +/** + * @brief Initialize the RS485 Driver enable feature according to the specified + * parameters in the UART_InitTypeDef and creates the associated handle. + * @param huart UART handle. + * @param Polarity Select the driver enable polarity. + * This parameter can be one of the following values: + * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high + * @arg @ref UART_DE_POLARITY_LOW DE signal is active low + * @param AssertionTime Driver Enable assertion time: + * 5-bit value defining the time between the activation of the DE (Driver Enable) + * signal and the beginning of the start bit. It is expressed in sample time + * units (1/8 or 1/16 bit time, depending on the oversampling rate) + * @param DeassertionTime Driver Enable deassertion time: + * 5-bit value defining the time between the end of the last stop bit, in a + * transmitted message, and the de-activation of the DE (Driver Enable) signal. + * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the + * oversampling rate). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, + uint32_t DeassertionTime) +{ + uint32_t temp; + + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + /* Check the Driver Enable UART instance */ + assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); + + /* Check the Driver Enable polarity */ + assert_param(IS_UART_DE_POLARITY(Polarity)); + + /* Check the Driver Enable assertion time */ + assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); + + /* Check the Driver Enable deassertion time */ + assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); + + if (huart->gState == HAL_UART_STATE_RESET) + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + UART_InitCallbacksToDefault(huart); + + if (huart->MspInitCallback == NULL) + { + huart->MspInitCallback = HAL_UART_MspInit; + } + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK, CORTEX */ + HAL_UART_MspInit(huart); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Perform advanced settings configuration */ + /* For some items, configuration requires to be done prior TE and RE bits are set */ + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + { + UART_AdvFeatureConfig(huart); + } + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + { + return HAL_ERROR; + } + + /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ + SET_BIT(huart->Instance->CR3, USART_CR3_DEM); + + /* Set the Driver Enable polarity */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); + + /* Set the Driver Enable assertion and deassertion times */ + temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); + temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); + MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions + * @brief Extended functions + * +@verbatim + =============================================================================== + ##### IO operation functions ##### + =============================================================================== + [..] + This subsection provides a set of Wakeup and FIFO mode related callback functions. + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() + (#) TX/RX Fifos Callbacks: + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() +@endverbatim + * @{ + */ + +/** + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + +/** + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + +/** + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + /* Prevent unused argument(s) compilation warning */ + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + +/** + * @} + */ + +/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions + * @brief Extended Peripheral Control functions + * +@verbatim + =============================================================================== + ##### Peripheral Control functions ##### + =============================================================================== + [..] This section provides the following functions: + (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address + detection length to more than 4 bits for multiprocessor address mark wake up. + (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode + trigger: address match, Start Bit detection or RXNE bit status. + (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode + (+) HAL_UARTEx_DisableStopMode() API disables the above functionality + (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode + (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode + (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold + (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold + + [..] This subsection also provides a set of additional functions providing enhanced reception + services to user. (For example, these functions allow application to handle use cases + where number of data to be received is unknown). + + (#) Compared to standard reception services which only consider number of received + data elements as reception completion criteria, these functions also consider additional events + as triggers for updating reception status to caller : + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + for 1 frame time, after last received byte. + (+++) RX inactivity detected by RTO, i.e. line has been in idle state + for a programmable time, after last received byte. + (++) Detection that a specific character has been received. + + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + or till IDLE event occurs. Reception is handled only during function execution. + When function exits, no data reception could occur. HAL status and number of actually received data elements, + are returned by function after finishing transfer. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. + These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. + The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. + + (#) Blocking mode API: + (++) HAL_UARTEx_ReceiveToIdle() + + (#) Non-Blocking mode API with Interrupt: + (++) HAL_UARTEx_ReceiveToIdle_IT() + + (#) Non-Blocking mode API with DMA: + (++) HAL_UARTEx_ReceiveToIdle_DMA() + +@endverbatim + * @{ + */ + +/** + * @brief By default in multiprocessor mode, when the wake up method is set + * to address mark, the UART handles only 4-bit long addresses detection; + * this API allows to enable longer addresses detection (6-, 7- or 8-bit + * long). + * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, + * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. + * @param huart UART handle. + * @param AddressLength This parameter can be one of the following values: + * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address + * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address + * @retval HAL status + */ +HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) +{ + /* Check the UART handle allocation */ + if (huart == NULL) + { + return HAL_ERROR; + } + + /* Check the address length parameter */ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* TEACK and/or REACK to check before moving huart->gState to Ready */ + return (UART_CheckIdleState(huart)); +} + +/** + * @brief Set Wakeup from Stop mode interrupt flag selection. + * @note It is the application responsibility to enable the interrupt used as + * usart_wkup interrupt source before entering low-power mode. + * @param huart UART handle. + * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. + * This parameter can be one of the following values: + * @arg @ref UART_WAKEUP_ON_ADDRESS + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + HAL_StatusTypeDef status = HAL_OK; + uint32_t tickstart; + + /* check the wake-up from stop mode UART instance */ + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + { + status = HAL_TIMEOUT; + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return status; +} + +/** + * @brief Enable UART Stop Mode. + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + /* Process Locked */ + __HAL_LOCK(huart); + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_ENABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Disable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + huart->FifoMode = UART_FIFOMODE_DISABLE; + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the TXFIFO threshold. + * @param huart UART handle. + * @param Threshold TX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_TXFIFO_THRESHOLD_1_8 + * @arg @ref UART_TXFIFO_THRESHOLD_1_4 + * @arg @ref UART_TXFIFO_THRESHOLD_1_2 + * @arg @ref UART_TXFIFO_THRESHOLD_3_4 + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Set the RXFIFO threshold. + * @param huart UART handle. + * @param Threshold RX FIFO threshold value + * This parameter can be one of the following values: + * @arg @ref UART_RXFIFO_THRESHOLD_1_8 + * @arg @ref UART_RXFIFO_THRESHOLD_1_4 + * @arg @ref UART_RXFIFO_THRESHOLD_1_2 + * @arg @ref UART_RXFIFO_THRESHOLD_3_4 + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + + huart->gState = HAL_UART_STATE_BUSY; + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + + huart->gState = HAL_UART_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + + return HAL_OK; +} + +/** + * @brief Receive an amount of data in blocking mode till either the expected number of data + * is received or an IDLE event occurs. + * @note HAL_OK is returned if reception is completed (expected number of data has been received) + * or if reception is stopped after IDLE event (less than the expected number of data has been received) + * In this case, RxLen output parameter indicates number of data available in reception buffer. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO + * is not empty. Read operations from the RDR register are performed when + * RXFNE flag is set. From hardware perspective, RXFNE flag and + * RXNE are mapped on the same bit-field. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @param RxLen Number of data elements finally received + * (could be lower than Size, in case reception ends on IDLE event) + * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout) +{ + uint8_t *pdata8bits; + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + huart->RxState = HAL_UART_STATE_BUSY_RX; + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + + huart->RxXferSize = Size; + huart->RxXferCount = Size; + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + uhMask = huart->Mask; + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + { + pdata8bits = NULL; + pdata16bits = (uint16_t *) pData; + } + else + { + pdata8bits = pData; + pdata16bits = NULL; + } + + /* Initialize output number of received elements */ + *RxLen = 0U; + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + { + /* Check if IDLE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) + { + /* Clear IDLE flag in ISR */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + + /* If Set, but no data ever received, clear flag without exiting loop */ + /* If Set, and data has already been received, this means Idle Event is valid : End reception */ + if (*RxLen > 0U) + { + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + } + + /* Check if RXNE flag is set */ + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) + { + if (pdata8bits == NULL) + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + pdata16bits++; + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + pdata8bits++; + } + /* Increment number of received elements */ + *RxLen += 1U; + huart->RxXferCount--; + } + + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + { + if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) + { + huart->RxState = HAL_UART_STATE_READY; + + return HAL_TIMEOUT; + } + } + } + + /* Set number of received elements in output parameter : RxLen */ + *RxLen = huart->RxXferSize - huart->RxXferCount; + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + + return HAL_OK; + } + else + { + return HAL_BUSY; + } +} + +/** + * @brief Receive an amount of data in interrupt mode till either the expected number of data + * is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating + * number of received data elements. + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status = HAL_OK; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + +#if defined(USART_DMAREQUESTS_SW_WA) + /* Disable the UART DMA Rx request if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + { + CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + } + +#endif /* USART_DMAREQUESTS_SW_WA */ + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + (void)UART_Start_Receive_IT(huart, pData, Size); + + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + + return status; + } + else + { + return HAL_BUSY; + } +} + +#if defined(HAL_DMA_MODULE_ENABLED) +/** + * @brief Receive an amount of data in DMA mode till either the expected number + * of data is received or an IDLE event occurs. + * @note Reception is initiated by this function call. Further progress of reception is achieved thanks + * to DMA services, transferring automatically received data elements in user reception buffer and + * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider + * reception phase as ended. In all cases, callback execution will indicate number of received data elements. + * @note When the UART parity is enabled (PCE = 1), the received data contain + * the parity bit (MSB position). + * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), + * the received data is handled as a set of uint16_t. In this case, Size must indicate the number + * of uint16_t available through pData. + * @param huart UART handle. + * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). + * @param Size Amount of data elements (uint8_t or uint16_t) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + HAL_StatusTypeDef status; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + { + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; + } + + /* Set Reception type to reception till IDLE Event*/ + huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; + huart->RxEventType = HAL_UART_RXEVENT_TC; + + status = UART_Start_Receive_DMA(huart, pData, Size); + + /* Check Rx process has been successfully started */ + if (status == HAL_OK) + { + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + } + else + { + /* In case of errors already pending when reception is started, + Interrupts may have already been raised and lead to reception abortion. + (Overrun error for instance). + In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ + status = HAL_ERROR; + } + } + + return status; + } + else + { + return HAL_BUSY; + } +} +#endif /* HAL_DMA_MODULE_ENABLED */ + +/** + * @brief Provide Rx Event type that has lead to RxEvent callback execution. + * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress + * of reception process is provided to application through calls of Rx Event callback (either default one + * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, + * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead + * to Rx Event callback execution. + * @note This function is expected to be called within the user implementation of Rx Event Callback, + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; + * When DMA is configured in Normal Mode, HT event does not stop Reception process; + * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; + * @param huart UART handle. + * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) + */ +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) +{ + /* Return Rx Event type value, as stored in UART handle */ + return (huart->RxEventType); +} + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup UARTEx_Private_Functions + * @{ + */ + +/** + * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); +} + +/** + * @brief Calculate the number of data to process in RX/TX ISR. + * @note The RX FIFO depth and the TX FIFO depth is extracted from + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + uint8_t rx_fifo_depth; + uint8_t tx_fifo_depth; + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + { + huart->NbTxDataToProcess = 1U; + huart->NbRxDataToProcess = 1U; + } + else + { + rx_fifo_depth = RX_FIFO_DEPTH; + tx_fifo_depth = TX_FIFO_DEPTH; + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} +/** + * @} + */ + +#endif /* HAL_UART_MODULE_ENABLED */ + +/** + * @} + */ + +/** + * @} + */ + diff --git a/MDK-ARM/.vscode/c_cpp_properties.json b/MDK-ARM/.vscode/c_cpp_properties.json index d2e0c42..999cc32 100644 --- a/MDK-ARM/.vscode/c_cpp_properties.json +++ b/MDK-ARM/.vscode/c_cpp_properties.json @@ -11,6 +11,7 @@ "d:\\advance_stick\\AutoGuideStick\\Drivers\\CMSIS\\Device\\ST\\STM32H5xx\\Include", "d:\\advance_stick\\AutoGuideStick\\Middlewares\\ST\\threadx\\ports\\cortex_m33\\ac6\\inc", "d:\\advance_stick\\AutoGuideStick\\Drivers\\CMSIS\\Include", + "d:\\advance_stick\\AutoGuideStick\\fun", "D:\\keil5\\ARM\\ARMCLANG\\include", "D:\\keil5\\ARM\\ARMCLANG\\include\\arm_linux", "D:\\keil5\\ARM\\ARMCLANG\\include\\arm_linux_compat", diff --git a/MDK-ARM/.vscode/keil-assistant.log b/MDK-ARM/.vscode/keil-assistant.log index e69de29..691d59f 100644 --- a/MDK-ARM/.vscode/keil-assistant.log +++ b/MDK-ARM/.vscode/keil-assistant.log @@ -0,0 +1,35 @@ +[info] Log at : 2025/6/4|21:10:03|GMT+0800 + +[info] Log at : 2025/6/6|21:03:44|GMT+0800 + +[info] Log at : 2025/6/7|15:16:44|GMT+0800 + +[info] Log at : 2025/6/7|16:13:28|GMT+0800 + +[info] Log at : 2025/6/7|22:48:28|GMT+0800 + +[info] Log at : 2025/6/7|22:48:50|GMT+0800 + +[info] Log at : 2025/6/7|23:59:46|GMT+0800 + +[info] Log at : 2025/6/8|20:26:47|GMT+0800 + +[info] Log at : 2025/6/8|20:30:10|GMT+0800 + +[info] Log at : 2025/6/8|20:31:15|GMT+0800 + +[info] Log at : 2025/6/8|20:32:47|GMT+0800 + +[info] project closed: AutoGuideStick +[info] Log at : 2025/6/8|20:33:15|GMT+0800 + +[info] Log at : 2025/6/8|20:34:25|GMT+0800 + +[info] project closed: AutoGuideStick +[info] Log at : 2025/6/8|20:51:48|GMT+0800 + +[info] project closed: AutoGuideStick +[info] Log at : 2025/6/8|20:57:54|GMT+0800 + +[info] Log at : 2025/6/8|21:00:00|GMT+0800 + diff --git a/MDK-ARM/.vscode/uv4.log b/MDK-ARM/.vscode/uv4.log new file mode 100644 index 0000000..6f290fb --- /dev/null +++ b/MDK-ARM/.vscode/uv4.log @@ -0,0 +1,189 @@ +*** Using Compiler 'V6.21', folder: 'D:\keil5\ARM\ARMCLANG\Bin' +Build target 'AutoGuideStick' +compiling main.c... +compiling usart.c... +compiling app_threadx.c... +compiling stm32h5xx_hal_rcc.c... +compiling gpio.c... +compiling stm32h5xx_hal_rcc_ex.c... +compiling stm32h5xx_hal_cortex.c... +compiling memorymap.c... +compiling stm32h5xx_hal_msp.c... +compiling stm32h5xx_hal_timebase_tim.c... +compiling stm32h5xx_it.c... +compiling app_azure_rtos.c... +compiling stm32h5xx_hal_tim_ex.c... +compiling stm32h5xx_hal_flash.c... +compiling stm32h5xx_hal_flash_ex.c... +compiling stm32h5xx_hal_tim.c... +compiling stm32h5xx_hal_gpio.c... +compiling stm32h5xx_hal_dma.c... +compiling stm32h5xx_hal_pwr.c... +compiling stm32h5xx_hal_pwr_ex.c... +compiling stm32h5xx_hal_dma_ex.c... +compiling stm32h5xx_hal.c... +compiling stm32h5xx_hal_exti.c... +compiling stm32h5xx_hal_uart_ex.c... +compiling system_stm32h5xx.c... +compiling stm32h5xx_hal_uart.c... +compiling tx_initialize_high_level.c... +compiling tx_initialize_kernel_enter.c... +compiling tx_initialize_kernel_setup.c... +compiling tx_thread_stack_error_handler.c... +compiling tx_thread_stack_error_notify.c... +compiling tx_thread_system_resume.c... +compiling tx_block_allocate.c... +compiling tx_block_pool_cleanup.c... +compiling tx_block_pool_create.c... +compiling tx_block_pool_delete.c... +compiling tx_block_pool_info_get.c... +compiling tx_block_pool_initialize.c... +compiling tx_block_pool_prioritize.c... +compiling tx_block_release.c... +compiling tx_byte_allocate.c... +compiling tx_byte_pool_cleanup.c... +compiling tx_byte_pool_create.c... +compiling tx_byte_pool_delete.c... +compiling tx_byte_pool_info_get.c... +compiling tx_byte_pool_initialize.c... +compiling tx_byte_pool_prioritize.c... +compiling tx_byte_pool_search.c... +compiling tx_byte_release.c... +compiling tx_event_flags_cleanup.c... +compiling tx_event_flags_create.c... +compiling tx_event_flags_delete.c... +compiling tx_event_flags_get.c... +compiling tx_event_flags_info_get.c... +compiling tx_event_flags_initialize.c... +compiling tx_event_flags_set.c... +compiling tx_mutex_cleanup.c... +compiling tx_event_flags_set_notify.c... +compiling tx_mutex_create.c... +compiling tx_mutex_delete.c... +compiling tx_mutex_get.c... +compiling tx_mutex_info_get.c... +compiling tx_mutex_initialize.c... +compiling tx_mutex_prioritize.c... +compiling tx_mutex_priority_change.c... +compiling tx_mutex_put.c... +compiling tx_queue_cleanup.c... +compiling tx_queue_create.c... +compiling tx_queue_delete.c... +compiling tx_queue_flush.c... +compiling tx_queue_front_send.c... +compiling tx_queue_info_get.c... +compiling tx_queue_initialize.c... +compiling tx_queue_prioritize.c... +compiling tx_queue_receive.c... +compiling tx_queue_send.c... +compiling tx_queue_send_notify.c... +compiling tx_semaphore_ceiling_put.c... +compiling tx_semaphore_cleanup.c... +compiling tx_semaphore_create.c... +compiling tx_semaphore_delete.c... +compiling tx_semaphore_get.c... +compiling tx_semaphore_info_get.c... +compiling tx_semaphore_initialize.c... +compiling tx_semaphore_prioritize.c... +compiling tx_semaphore_put.c... +compiling tx_semaphore_put_notify.c... +compiling tx_thread_create.c... +compiling tx_thread_delete.c... +compiling tx_thread_entry_exit_notify.c... +compiling tx_thread_identify.c... +compiling tx_thread_info_get.c... +compiling tx_thread_initialize.c... +compiling tx_thread_preemption_change.c... +compiling tx_thread_priority_change.c... +compiling tx_thread_relinquish.c... +compiling tx_thread_reset.c... +compiling tx_thread_resume.c... +compiling tx_thread_shell_entry.c... +compiling tx_thread_sleep.c... +compiling tx_thread_stack_analyze.c... +compiling tx_thread_suspend.c... +compiling tx_thread_system_preempt_check.c... +compiling tx_thread_system_suspend.c... +compiling tx_thread_terminate.c... +compiling tx_thread_time_slice.c... +compiling tx_thread_time_slice_change.c... +compiling tx_thread_timeout.c... +compiling tx_thread_wait_abort.c... +compiling tx_time_get.c... +compiling tx_time_set.c... +compiling txe_block_allocate.c... +compiling txe_block_pool_create.c... +compiling txe_block_pool_delete.c... +compiling txe_block_pool_info_get.c... +compiling txe_block_pool_prioritize.c... +compiling txe_block_release.c... +compiling txe_byte_allocate.c... +compiling txe_byte_pool_create.c... +compiling txe_byte_pool_delete.c... +compiling txe_byte_pool_info_get.c... +compiling txe_byte_pool_prioritize.c... +compiling txe_byte_release.c... +compiling txe_event_flags_create.c... +compiling txe_event_flags_delete.c... +compiling txe_event_flags_get.c... +compiling txe_event_flags_info_get.c... +compiling txe_event_flags_set.c... +compiling txe_event_flags_set_notify.c... +compiling txe_mutex_create.c... +compiling txe_mutex_delete.c... +compiling txe_mutex_get.c... +compiling txe_mutex_info_get.c... +compiling txe_mutex_prioritize.c... +compiling txe_mutex_put.c... +compiling txe_queue_create.c... +compiling txe_queue_delete.c... +compiling txe_queue_flush.c... +compiling txe_queue_front_send.c... +compiling txe_queue_info_get.c... +compiling txe_queue_prioritize.c... +compiling txe_queue_receive.c... +compiling txe_queue_send.c... +compiling txe_queue_send_notify.c... +compiling txe_semaphore_ceiling_put.c... +compiling txe_semaphore_create.c... +compiling txe_semaphore_delete.c... +compiling txe_semaphore_get.c... +compiling txe_semaphore_info_get.c... +compiling txe_semaphore_prioritize.c... +compiling txe_semaphore_put.c... +compiling txe_semaphore_put_notify.c... +compiling txe_thread_create.c... +compiling txe_thread_delete.c... +compiling txe_thread_entry_exit_notify.c... +compiling txe_thread_info_get.c... +compiling txe_thread_preemption_change.c... +compiling txe_thread_priority_change.c... +compiling txe_thread_relinquish.c... +compiling txe_thread_reset.c... +compiling txe_thread_resume.c... +compiling txe_thread_suspend.c... +compiling txe_thread_terminate.c... +compiling txe_thread_time_slice_change.c... +compiling txe_thread_wait_abort.c... +compiling tx_timer_activate.c... +compiling tx_timer_change.c... +compiling tx_timer_create.c... +compiling tx_timer_deactivate.c... +compiling tx_timer_delete.c... +compiling tx_timer_expiration_process.c... +compiling tx_timer_info_get.c... +compiling tx_timer_initialize.c... +compiling tx_timer_system_activate.c... +compiling tx_timer_system_deactivate.c... +compiling tx_timer_thread_entry.c... +compiling txe_timer_activate.c... +compiling txe_timer_change.c... +compiling txe_timer_create.c... +compiling txe_timer_deactivate.c... +compiling txe_timer_delete.c... +compiling txe_timer_info_get.c... +linking... +Program Size: Code=40362 RO-data=726 RW-data=16 ZI-data=4536 +FromELF: creating hex file... +"AutoGuideStick\AutoGuideStick.axf" - 0 Error(s), 0 Warning(s). +Build Time Elapsed: 00:00:24 diff --git a/MDK-ARM/.vscode/uv4.log.lock b/MDK-ARM/.vscode/uv4.log.lock index e69de29..4a1fdf0 100644 --- a/MDK-ARM/.vscode/uv4.log.lock +++ b/MDK-ARM/.vscode/uv4.log.lock @@ -0,0 +1 @@ +2025/6/8 21:00:51 \ No newline at end of file diff --git a/MDK-ARM/AutoGuideStick.uvguix.madao b/MDK-ARM/AutoGuideStick.uvguix.madao new file mode 100644 index 0000000..1921a08 --- /dev/null +++ b/MDK-ARM/AutoGuideStick.uvguix.madao @@ -0,0 +1,1896 @@ + + + + -6.1 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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+ ../Middlewares/ST/threadx/common/src/txe_event_flags_create.c + txe_event_flags_create.c + 0 + 0 + + + 6 + 136 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_event_flags_delete.c + txe_event_flags_delete.c + 0 + 0 + + + 6 + 137 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_event_flags_get.c + txe_event_flags_get.c + 0 + 0 + + + 6 + 138 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_event_flags_info_get.c + txe_event_flags_info_get.c + 0 + 0 + + + 6 + 139 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_event_flags_set.c + txe_event_flags_set.c + 0 + 0 + + + 6 + 140 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_event_flags_set_notify.c + txe_event_flags_set_notify.c + 0 + 0 + + + 6 + 141 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_mutex_create.c + txe_mutex_create.c + 0 + 0 + + + 6 + 142 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_mutex_delete.c + txe_mutex_delete.c + 0 + 0 + + + 6 + 143 + 1 + 0 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1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/tx_timer_info_get.c + tx_timer_info_get.c + 0 + 0 + + + 6 + 184 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/tx_timer_initialize.c + tx_timer_initialize.c + 0 + 0 + + + 6 + 185 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/tx_timer_system_activate.c + tx_timer_system_activate.c + 0 + 0 + + + 6 + 186 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/tx_timer_system_deactivate.c + tx_timer_system_deactivate.c + 0 + 0 + + + 6 + 187 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/tx_timer_thread_entry.c + tx_timer_thread_entry.c + 0 + 0 + + + 6 + 188 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_activate.c + txe_timer_activate.c + 0 + 0 + + + 6 + 189 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_change.c + txe_timer_change.c + 0 + 0 + + + 6 + 190 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_create.c + txe_timer_create.c + 0 + 0 + + + 6 + 191 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_deactivate.c + txe_timer_deactivate.c + 0 + 0 + + + 6 + 192 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_delete.c + txe_timer_delete.c + 0 + 0 + + + 6 + 193 + 1 + 0 + 0 + 0 + ../Middlewares/ST/threadx/common/src/txe_timer_info_get.c + txe_timer_info_get.c + 0 + 0 + + + + + fun + 1 + 0 + 0 + 0 + + 7 + 194 + 1 + 0 + 0 + 0 + ..\fun\HCBle.c + HCBle.c + 0 + 0 + + + 7 + 195 + 5 + 0 + 0 + 0 + ..\fun\HCBle.h + HCBle.h + 0 + 0 + + + 7 + 196 + 5 + 0 + 0 + 0 + ..\fun\headfile.h + headfile.h + 0 + 0 + + + + + ::CMSIS + 0 + 0 + 0 + 1 + +
diff --git a/MDK-ARM/AutoGuideStick.uvprojx b/MDK-ARM/AutoGuideStick.uvprojx index 597521c..7525c4f 100644 --- a/MDK-ARM/AutoGuideStick.uvprojx +++ b/MDK-ARM/AutoGuideStick.uvprojx @@ -1,41 +1,46 @@ - - + + + 2.1 +
### uVision Project, (C) Keil Software
+ AutoGuideStick 0x4 ARM-ADS - 6140001::V6.14.1::ARMCLANG + 6210000::V6.21::ARMCLANG 1 STM32H563ZITx STMicroelectronics + Keil.STM32H5xx_DFP.1.3.0 + https://www.keil.com/pack/ IRAM(0x20000000-0x2009FFFF) IROM(0x08000000-0x81FFFFF) CLOCK(8000000) FPU3(SFPU) CPUTYPE("Cortex-M33") ELITTLE TZ DSP - - - + + + 0 - - - - - - - - - - - + + + + + + + + + + + $$Device:STM32H563ZITx$CMSIS\SVD\STM32H563.svd 0 0 - - - - - + + + + + 0 0 @@ -50,15 +55,15 @@ 1 1 1 - ./AutoGuideStick/ + 1 0 0 0 0 - - + + 0 0 0 @@ -67,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -77,15 +82,15 @@ 0 1 - - + + 0 0 0 0 1 - + 0 @@ -99,15 +104,15 @@ 0 0 3 - - + + 0 - - - - + + + + SARMV8M.DLL -MPU TCM.DLL @@ -133,11 +138,11 @@ 1 BIN\UL2V8M.DLL - - - - - + + + + + 0 @@ -170,7 +175,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -181,8 +186,9 @@ 2 0 0 + 0 0 - 1 + 0 8 0 0 @@ -201,7 +207,7 @@ 0 0 1 - 1 + 0 0 0 0 @@ -240,13 +246,13 @@ 0 - 0x0 - 0x0 + 0x20000000 + 0xa0000 1 - 0x0 - 0x0 + 0x8000000 + 0x200000 0 @@ -270,8 +276,8 @@ 1 - - + 0x8000000 + 0x200000 1 @@ -295,8 +301,8 @@ 0 - - + 0x20000000 + 0xa0000 0 @@ -304,11 +310,11 @@ 0x0 - + 1 - 4 + 1 0 0 1 @@ -331,10 +337,10 @@ 0 0 - + TX_INCLUDE_USER_DEFINE_FILE,TX_SINGLE_MODE_NON_SECURE=1,USE_HAL_DRIVER,STM32H563xx - - ../Core/Inc;../AZURE_RTOS/App;../Drivers/STM32H5xx_HAL_Driver/Inc;../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;../Middlewares/ST/threadx/common/inc;../Drivers/CMSIS/Device/ST/STM32H5xx/Include;../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc;../Drivers/CMSIS/Include + + ../Core/Inc;../AZURE_RTOS/App;../Drivers/STM32H5xx_HAL_Driver/Inc;../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;../Middlewares/ST/threadx/common/inc;../Drivers/CMSIS/Device/ST/STM32H5xx/Include;../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc;../Drivers/CMSIS/Include;..\fun @@ -349,9 +355,9 @@ 0 1 - + TX_SINGLE_MODE_NON_SECURE=1 - + ../Core/Inc;../AZURE_RTOS/App;../Drivers/STM32H5xx_HAL_Driver/Inc;../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy;../Middlewares/ST/threadx/common/inc;../Drivers/CMSIS/Device/ST/STM32H5xx/Include;../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc;../Drivers/CMSIS/Include @@ -362,15 +368,15 @@ 0 1 0 - - - - - - - - - + + + + + + + + + @@ -403,11 +409,6 @@ 1 ../Core/Src/gpio.c - - icache.c - 1 - ../Core/Src/icache.c - memorymap.c 1 @@ -418,6 +419,62 @@ 1 ../Core/Src/app_threadx.c + + usart.c + 1 + ../Core/Src/usart.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + stm32h5xx_it.c 1 @@ -519,9 +576,116 @@ ../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_exti.c - stm32h5xx_hal_icache.c + stm32h5xx_hal_uart.c 1 - ../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_icache.c + ../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + + + + stm32h5xx_hal_uart_ex.c + 1 + ../Drivers/STM32H5xx_HAL_Driver/Src/stm32h5xx_hal_uart_ex.c + + + 2 + 0 + 0 + 0 + 0 + 1 + 2 + 2 + 2 + 2 + 11 + + + 1 + + + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 + + + + + + + + + @@ -1365,20 +1529,44 @@ + + fun + + + HCBle.c + 1 + ..\fun\HCBle.c + + + HCBle.h + 5 + ..\fun\HCBle.h + + + headfile.h + 5 + ..\fun\headfile.h + + + + + ::CMSIS + + - + - + - + - + -
+
diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.axf b/MDK-ARM/AutoGuideStick/AutoGuideStick.axf new file mode 100644 index 0000000..f9099d9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/AutoGuideStick.axf differ diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm b/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm new file mode 100644 index 0000000..a7a32ad --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.build_log.htm @@ -0,0 +1,57 @@ + + +
+

礦ision Build Log

+

Tool Versions:

+IDE-Version: μVision V5.39.0.0 +Copyright (C) 2023 ARM Ltd and ARM Germany GmbH. All rights reserved. +License Information: manba man, fffffff, LIC=IK1BF-6Y3R7-CXQU6-DU1PR-6YJSL-ZDVC8 + +Tool Versions: +Toolchain: MDK-ARM Plus Version: 5.39.0.0 +Toolchain Path: D:\keil5\ARM\ARMCLANG\Bin +C Compiler: ArmClang.exe V6.21 +Assembler: Armasm.exe V6.21 +Linker/Locator: ArmLink.exe V6.21 +Library Manager: ArmAr.exe V6.21 +Hex Converter: FromElf.exe V6.21 +CPU DLL: +Dialog DLL: +Target DLL: STLink\ST-LINKIII-KEIL_SWO.dll V3.2.0.0 +Dialog DLL: TCM.DLL V1.56.4.0 + +

Project:

+D:\advance_stick\AutoGuideStick\MDK-ARM\AutoGuideStick.uvprojx +Project File Date: 06/08/2025 + +

Output:

+*** Using Compiler 'V6.21', folder: 'D:\keil5\ARM\ARMCLANG\Bin' +Build target 'AutoGuideStick' +"AutoGuideStick\AutoGuideStick.axf" - 0 Error(s), 0 Warning(s). + +

Software Packages used:

+ +Package Vendor: ARM + http://www.keil.com/pack/ARM.CMSIS.5.9.0.pack + ARM::CMSIS@5.9.0 + CMSIS (Common Microcontroller Software Interface Standard) + * Component: CORE Version: 5.6.0 + +Package Vendor: Keil + https://www.keil.com/pack/Keil.STM32H5xx_DFP.1.3.0.pack + Keil::STM32H5xx_DFP@1.3.0 + STMicroelectronics STM32H5 Series Device Support + +

Collection of Component include folders:

+ ./RTE/_AutoGuideStick + D:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include + D:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include + +

Collection of Component Files used:

+ + * Component: ARM::CMSIS:CORE@5.6.0 + Include file: CMSIS/Core/Include/tz_context.h +Build Time Elapsed: 00:00:01 +
+ + diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.hex b/MDK-ARM/AutoGuideStick/AutoGuideStick.hex new file mode 100644 index 0000000..1625ae1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.hex @@ -0,0 +1,2572 @@ +:020000040800F2 +:10000000C811002019030008CD7A0008E97900081A +:10001000C97A0008B9070008D58C00082B0300082E +:100020000000000000000000000000002D03000898 +:10003000BD0700080000000001040008AD0300082F +:1000400035030008350300083503000835030008B0 +:1000500035030008350300083503000835030008A0 +:100060003503000835030008350300083503000890 +:100070003503000835030008350300083503000880 +:100080003503000835030008350300083503000870 +:100090003503000835030008350300083503000860 +:1000A0003503000835030008350300083503000850 +:1000B0003503000835030008350300083503000840 +:1000C0003503000835030008350300083503000830 +:1000D0000000000035030008350300083503000860 +:1000E00035030008350300081580000835030008B3 +:1000F0003503000835030008350300083503000800 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+:10A080000090D003F0F0F0F001000000100000009C +:040000050800024DA0 +:00000001FF diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.htm b/MDK-ARM/AutoGuideStick/AutoGuideStick.htm new file mode 100644 index 0000000..dff9c8a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.htm @@ -0,0 +1,1688 @@ + + +Static Call Graph - [AutoGuideStick\AutoGuideStick.axf] +
+

Static Call Graph for image AutoGuideStick\AutoGuideStick.axf


+

#<CALLGRAPH># ARM Linker, 6210000: Last Updated: Sun Jun 8 22:25:39 2025 +

+

Maximum Stack Usage = 568 bytes + Unknown(Functions without stacksize, Cycles, Untraceable Function Pointers)

+Call chain for Maximum Stack Depth:

+__rt_entry_main ⇒ main ⇒ MX_USART1_UART_Init ⇒ HAL_UART_Init ⇒ HAL_UART_MspInit ⇒ HAL_RCCEx_PeriphCLKConfig ⇒ RCCEx_PLL3_Config +

+

+Functions with no stack information +

+ +

+

+Mutually Recursive functions +

  • SecureFault_Handler   ⇒   SecureFault_Handler
    +
  • SVC_Handler   ⇒   SVC_Handler
    +
  • ADC1_IRQHandler   ⇒   ADC1_IRQHandler
    + +

    +

    +Function Pointers +

    +

    +

    +Global Symbols +

    +

    __main (Thumb, 8 bytes, Stack size 0 bytes, __main.o(!!!main)) +

    [Calls]

    +
    [Address Reference Count : 1] +

    __scatterload (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter)) +

    [Called By]

    + +

    __scatterload_rt2 (Thumb, 84 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) +

    [Calls]

    + +

    __scatterload_rt2_thumb_only (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_loop (Thumb, 0 bytes, Stack size unknown bytes, __scatter.o(!!!scatter), UNUSED) + +

    __scatterload_copy (Thumb, 26 bytes, Stack size unknown bytes, __scatter_copy.o(!!handler_copy), UNUSED) +

    [Calls]

    +
    [Called By] + +

    __scatterload_null (Thumb, 2 bytes, Stack size unknown bytes, __scatter.o(!!handler_null), UNUSED) + +

    __scatterload_zeroinit (Thumb, 28 bytes, Stack size unknown bytes, __scatter_zi.o(!!handler_zi), UNUSED) + +

    __rt_lib_init (Thumb, 0 bytes, Stack size unknown bytes, libinit.o(.ARM.Collect$$libinit$$00000000)) +

    [Called By]

    + +

    __rt_lib_init_fp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000001)) +

    [Calls]

    + +

    __rt_lib_init_alloca_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000030)) + +

    __rt_lib_init_argv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000002E)) + +

    __rt_lib_init_atexit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001D)) + +

    __rt_lib_init_clock_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000023)) + +

    __rt_lib_init_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000034)) + +

    __rt_lib_init_exceptions_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000032)) + +

    __rt_lib_init_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000021)) + +

    __rt_lib_init_getenv_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000025)) + +

    __rt_lib_init_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000C)) + +

    __rt_lib_init_lc_collate_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000013)) + +

    __rt_lib_init_lc_ctype_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000015)) + +

    __rt_lib_init_lc_monetary_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000017)) + +

    __rt_lib_init_lc_numeric_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000019)) + +

    __rt_lib_init_lc_time_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001B)) + +

    __rt_lib_init_preinit_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000006)) + +

    __rt_lib_init_rand_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000010)) + +

    __rt_lib_init_relocate_pie_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000004)) + +

    __rt_lib_init_return (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000035)) + +

    __rt_lib_init_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000001F)) + +

    __rt_lib_init_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$00000027)) + +

    __rt_lib_init_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libinit2.o(.ARM.Collect$$libinit$$0000000E)) + +

    __rt_lib_shutdown (Thumb, 0 bytes, Stack size unknown bytes, libshutdown.o(.ARM.Collect$$libshutdown$$00000000)) +

    [Called By]

    + +

    __rt_lib_shutdown_cpp_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000002)) + +

    __rt_lib_shutdown_fp_trap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000007)) + +

    __rt_lib_shutdown_heap_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F)) + +

    __rt_lib_shutdown_return (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000010)) + +

    __rt_lib_shutdown_signal_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A)) + +

    __rt_lib_shutdown_stdio_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$00000004)) + +

    __rt_lib_shutdown_user_alloc_1 (Thumb, 0 bytes, Stack size unknown bytes, libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C)) + +

    __rt_entry (Thumb, 0 bytes, Stack size unknown bytes, __rtentry.o(.ARM.Collect$$rtentry$$00000000)) +

    [Called By]

    + +

    __rt_entry_presh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000002)) + +

    __rt_entry_sh (Thumb, 0 bytes, Stack size unknown bytes, __rtentry4.o(.ARM.Collect$$rtentry$$00000004)) +

    [Stack]

    +
    [Calls] + +

    __rt_entry_li (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000A)) +

    [Calls]

    + +

    __rt_entry_postsh_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$00000009)) + +

    __rt_entry_main (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000D)) +

    [Stack]

    +
    [Calls] + +

    __rt_entry_postli_1 (Thumb, 0 bytes, Stack size unknown bytes, __rtentry2.o(.ARM.Collect$$rtentry$$0000000C)) + +

    __rt_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit.o(.ARM.Collect$$rtexit$$00000000)) +

    [Called By]

    + +

    __rt_exit_ls (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000003)) +

    [Calls]

    + +

    __rt_exit_prels_1 (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000002)) + +

    __rt_exit_exit (Thumb, 0 bytes, Stack size unknown bytes, rtexit2.o(.ARM.Collect$$rtexit$$00000004)) +

    [Calls]

    + +

    Reset_Handler (Thumb, 8 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SecureFault_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    SVC_Handler (Thumb, 2 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    ADC1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +

    [Calls]

    +
    [Called By] +
    [Address Reference Count : 1] +

    ADC2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    CEC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    CORDIC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    CRS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    DAC1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    DCACHE1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    DCMI_PSSI_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    DTS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    ETH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    ETH_WKUP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI8_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    EXTI9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FDCAN1_IT0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FDCAN1_IT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FDCAN2_IT0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FDCAN2_IT1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FLASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FLASH_S_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FMAC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FMC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    FPU_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA1_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel0_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GPDMA2_Channel7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    GTZC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    HASH_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C2_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C2_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C3_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C3_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C4_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I2C4_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I3C1_ER_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    I3C1_EV_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    ICACHE_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    IWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPTIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    LPUART1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    OCTOSPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    PVD_AVD_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RAMCFG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RCC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RCC_S_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RNG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RTC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    RTC_S_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SAI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SAI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SDMMC1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SDMMC2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    SPI6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TAMP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM13_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM14_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM15_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM16_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM17_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM1_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM1_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM1_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM8_BRK_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM8_CC_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM8_TRG_COM_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    TIM8_UP_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART12_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART4_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART5_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART7_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART8_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UART9_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    UCPD1_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USART10_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USART11_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USART2_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USART3_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USART6_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    USB_DRD_FS_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    WWDG_IRQHandler (Thumb, 0 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +
    [Address Reference Count : 1]

    +

    __user_initial_stackheap (Thumb, 10 bytes, Stack size 0 bytes, startup_stm32h563xx.o(.text)) +

    [Called By]

    + +

    _tx_initialize_low_level (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text)) +

    [Called By]

    + +

    __tx_BadHandler (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED) +

    [Calls]

    +
    [Called By] + +

    __tx_IntHandler (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED) + +

    SysTick_Handler (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    __tx_NMIHandler (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED) +

    [Calls]

    +
    [Called By] + +

    __tx_DBGHandler (Thumb, 0 bytes, Stack size unknown bytes, tx_initialize_low_level.o(.text), UNUSED) +

    [Calls]

    +
    [Called By] + +

    _tx_thread_schedule (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text)) +

    [Called By]

    + +

    PendSV_Handler (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text)) +
    [Address Reference Count : 1]

    +

    _tx_vfp_access (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_schedule.o(.text), UNUSED) + +

    _tx_thread_stack_build (Thumb, 0 bytes, Stack size unknown bytes, tx_thread_stack_build.o(.text)) +

    [Called By]

    + +

    _tx_timer_interrupt (Thumb, 0 bytes, Stack size unknown bytes, tx_timer_interrupt.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    __aeabi_uldivmod (Thumb, 0 bytes, Stack size 48 bytes, lludivv7m.o(.text)) +

    [Stack]

    +
    [Called By] + +

    _ll_udiv (Thumb, 240 bytes, Stack size 48 bytes, lludivv7m.o(.text), UNUSED) + +

    __aeabi_memset (Thumb, 16 bytes, Stack size 0 bytes, aeabi_memset.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    __aeabi_memclr (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text), UNUSED) + +

    __rt_memclr (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr.o(.text), UNUSED) + +

    _memset (Thumb, 64 bytes, Stack size 0 bytes, rt_memclr.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    __aeabi_memclr4 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    + +

    __aeabi_memclr8 (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text)) +

    [Called By]

    + +

    __rt_memclr_w (Thumb, 0 bytes, Stack size unknown bytes, rt_memclr_w.o(.text), UNUSED) + +

    _memset_w (Thumb, 74 bytes, Stack size 4 bytes, rt_memclr_w.o(.text)) +

    [Stack]

    +
    [Called By] + +

    __use_two_region_memory (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_escrow$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __rt_heap_expand$2region (Thumb, 2 bytes, Stack size 0 bytes, heapauxi.o(.text), UNUSED) + +

    __user_setup_stackheap (Thumb, 74 bytes, Stack size 8 bytes, sys_stackheap_outer.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    exit (Thumb, 18 bytes, Stack size 8 bytes, exit.o(.text)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    __user_libspace (Thumb, 8 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    __user_perproc_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text)) +

    [Called By]

    + +

    __user_perthread_libspace (Thumb, 0 bytes, Stack size 0 bytes, libspace.o(.text), UNUSED) + +

    _sys_exit (Thumb, 8 bytes, Stack size 0 bytes, sys_exit.o(.text)) +

    [Called By]

    + +

    __I$use$semihosting (Thumb, 0 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __use_no_semihosting_swi (Thumb, 2 bytes, Stack size 0 bytes, use_no_semi.o(.text), UNUSED) + +

    __semihosting_library_function (Thumb, 0 bytes, Stack size unknown bytes, indicate_semi.o(.text), UNUSED) + +

    App_ThreadX_Init (Thumb, 14 bytes, Stack size 8 bytes, app_threadx.o(.text.App_ThreadX_Init)) +

    [Stack]

    +
    [Called By] + +

    BusFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.BusFault_Handler)) +
    [Address Reference Count : 1]

    +

    DebugMon_Handler (Thumb, 2 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.DebugMon_Handler)) +
    [Address Reference Count : 1]

    +

    Error_Handler (Thumb, 6 bytes, Stack size 0 bytes, main.o(.text.Error_Handler)) +

    [Called By]

    + +

    HAL_DMA_Abort (Thumb, 278 bytes, Stack size 24 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_DMA_Abort_IT (Thumb, 84 bytes, Stack size 8 bytes, stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT)) +

    [Stack]

    +
    [Called By] + +

    HAL_GPIO_Init (Thumb, 746 bytes, Stack size 20 bytes, stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init)) +

    [Stack]

    +
    [Called By] + +

    HAL_GetTick (Thumb, 12 bytes, Stack size 0 bytes, stm32h5xx_hal.o(.text.HAL_GetTick)) +

    [Called By]

    + +

    HAL_IncTick (Thumb, 26 bytes, Stack size 0 bytes, stm32h5xx_hal.o(.text.HAL_IncTick)) +

    [Called By]

    + +

    HAL_Init (Thumb, 94 bytes, Stack size 16 bytes, stm32h5xx_hal.o(.text.HAL_Init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_InitTick (Thumb, 206 bytes, Stack size 56 bytes, stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_MspInit (Thumb, 2 bytes, Stack size 0 bytes, stm32h5xx_hal_msp.o(.text.HAL_MspInit)) +

    [Called By]

    + +

    HAL_NVIC_EnableIRQ (Thumb, 20 bytes, Stack size 16 bytes, stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_NVIC_SetPriority (Thumb, 46 bytes, Stack size 32 bytes, stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_NVIC_SetPriorityGrouping (Thumb, 16 bytes, Stack size 16 bytes, stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCCEx_GetPLL1ClockFreq (Thumb, 748 bytes, Stack size 36 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq)) +

    [Stack]

    +
    [Called By] + +

    HAL_RCCEx_GetPLL2ClockFreq (Thumb, 748 bytes, Stack size 36 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq)) +

    [Stack]

    +
    [Called By] + +

    HAL_RCCEx_GetPLL3ClockFreq (Thumb, 748 bytes, Stack size 36 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq)) +

    [Stack]

    +
    [Called By] + +

    HAL_RCCEx_GetPeriphCLKFreq (Thumb, 10488 bytes, Stack size 120 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCCEx_PeriphCLKConfig (Thumb, 6382 bytes, Stack size 184 bytes, stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_ClockConfig (Thumb, 1172 bytes, Stack size 32 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_GetClockConfig (Thumb, 108 bytes, Stack size 12 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig)) +

    [Stack]

    +
    [Called By] + +

    HAL_RCC_GetHCLKFreq (Thumb, 52 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_GetPCLK1Freq (Thumb, 38 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_GetPCLK2Freq (Thumb, 38 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_GetPCLK3Freq (Thumb, 38 bytes, Stack size 8 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_RCC_GetSysClockFreq (Thumb, 700 bytes, Stack size 36 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq)) +

    [Stack]

    +
    [Called By] + +

    HAL_RCC_OscConfig (Thumb, 2556 bytes, Stack size 40 bytes, stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_SYSTICK_CLKSourceConfig (Thumb, 154 bytes, Stack size 8 bytes, stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_Break2Callback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_BreakCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_CommutCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_DirectionChangeCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_EncoderIndexCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_IndexErrorCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIMEx_TransitionErrorCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_Base_Init (Thumb, 168 bytes, Stack size 16 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_TIM_Base_MspInit (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_Base_Start_IT (Thumb, 402 bytes, Stack size 12 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_IC_CaptureCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_IRQHandler (Thumb, 768 bytes, Stack size 24 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_TIM_OC_DelayElapsedCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_PWM_PulseFinishedCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_TIM_PeriodElapsedCallback (Thumb, 34 bytes, Stack size 16 bytes, main.o(.text.HAL_TIM_PeriodElapsedCallback)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_TIM_TriggerCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UARTEx_DisableFifoMode (Thumb, 124 bytes, Stack size 12 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode)) +

    [Stack]

    +
    [Called By] + +

    HAL_UARTEx_RxEventCallback (Thumb, 12 bytes, Stack size 8 bytes, stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UARTEx_RxFifoFullCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UARTEx_SetRxFifoThreshold (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_UARTEx_SetTxFifoThreshold (Thumb, 140 bytes, Stack size 24 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_UARTEx_TxFifoEmptyCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UARTEx_WakeupCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UART_ErrorCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback)) +

    [Stack]

    +
    [Called By] + +

    HAL_UART_IRQHandler (Thumb, 1346 bytes, Stack size 64 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_UART_Init (Thumb, 170 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_Init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_UART_MspInit (Thumb, 192 bytes, Stack size 312 bytes, usart.o(.text.HAL_UART_MspInit)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    HAL_UART_TxCpltCallback (Thumb, 8 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback)) +

    [Stack]

    +
    [Called By] + +

    HardFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.HardFault_Handler)) +
    [Address Reference Count : 1]

    +

    MX_GPIO_Init (Thumb, 66 bytes, Stack size 8 bytes, gpio.o(.text.MX_GPIO_Init)) +

    [Stack]

    +
    [Called By] + +

    MX_ThreadX_Init (Thumb, 8 bytes, Stack size 8 bytes, app_threadx.o(.text.MX_ThreadX_Init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    MX_USART1_UART_Init (Thumb, 142 bytes, Stack size 16 bytes, usart.o(.text.MX_USART1_UART_Init)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    MemManage_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.MemManage_Handler)) +
    [Address Reference Count : 1]

    +

    NMI_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.NMI_Handler)) +
    [Address Reference Count : 1]

    +

    SystemClock_Config (Thumb, 198 bytes, Stack size 120 bytes, main.o(.text.SystemClock_Config)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    SystemInit (Thumb, 310 bytes, Stack size 8 bytes, system_stm32h5xx.o(.text.SystemInit)) +

    [Stack]

    +
    [Address Reference Count : 1] +

    TIM1_UP_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.TIM1_UP_IRQHandler)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    TIM_Base_SetConfig (Thumb, 858 bytes, Stack size 12 bytes, stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig)) +

    [Stack]

    +
    [Called By] + +

    UART_AdvFeatureConfig (Thumb, 328 bytes, Stack size 4 bytes, stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig)) +

    [Stack]

    +
    [Called By] + +

    UART_CheckIdleState (Thumb, 326 bytes, Stack size 40 bytes, stm32h5xx_hal_uart.o(.text.UART_CheckIdleState)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    UART_SetConfig (Thumb, 1048 bytes, Stack size 48 bytes, stm32h5xx_hal_uart.o(.text.UART_SetConfig)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    UART_WaitOnFlagUntilTimeout (Thumb, 268 bytes, Stack size 32 bytes, stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    USART1_IRQHandler (Thumb, 16 bytes, Stack size 8 bytes, stm32h5xx_it.o(.text.USART1_IRQHandler)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    UsageFault_Handler (Thumb, 4 bytes, Stack size 0 bytes, stm32h5xx_it.o(.text.UsageFault_Handler)) +
    [Address Reference Count : 1]

    +

    _tx_byte_pool_create (Thumb, 304 bytes, Stack size 64 bytes, tx_byte_pool_create.o(.text._tx_byte_pool_create)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_initialize_high_level (Thumb, 134 bytes, Stack size 8 bytes, tx_initialize_high_level.o(.text._tx_initialize_high_level)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_initialize_kernel_enter (Thumb, 104 bytes, Stack size 16 bytes, tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_thread_create (Thumb, 538 bytes, Stack size 80 bytes, tx_thread_create.o(.text._tx_thread_create)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_thread_initialize (Thumb, 126 bytes, Stack size 16 bytes, tx_thread_initialize.o(.text._tx_thread_initialize)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_thread_shell_entry (Thumb, 148 bytes, Stack size 40 bytes, tx_thread_shell_entry.o(.text._tx_thread_shell_entry)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    _tx_thread_system_preempt_check (Thumb, 112 bytes, Stack size 28 bytes, tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check)) +

    [Stack]

    +
    [Called By] + +

    _tx_thread_system_resume (Thumb, 584 bytes, Stack size 96 bytes, tx_thread_system_resume.o(.text._tx_thread_system_resume)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_thread_system_suspend (Thumb, 640 bytes, Stack size 120 bytes, tx_thread_system_suspend.o(.text._tx_thread_system_suspend)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_thread_time_slice (Thumb, 162 bytes, Stack size 20 bytes, tx_thread_time_slice.o(.text._tx_thread_time_slice)) +

    [Stack]

    +
    [Called By] + +

    _tx_thread_timeout (Thumb, 114 bytes, Stack size 48 bytes, tx_thread_timeout.o(.text._tx_thread_timeout)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    _tx_timer_expiration_process (Thumb, 60 bytes, Stack size 24 bytes, tx_timer_expiration_process.o(.text._tx_timer_expiration_process)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_timer_initialize (Thumb, 286 bytes, Stack size 48 bytes, tx_timer_initialize.o(.text._tx_timer_initialize)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _tx_timer_system_activate (Thumb, 212 bytes, Stack size 28 bytes, tx_timer_system_activate.o(.text._tx_timer_system_activate)) +

    [Stack]

    +
    [Called By] + +

    _tx_timer_system_deactivate (Thumb, 112 bytes, Stack size 16 bytes, tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate)) +

    [Stack]

    +
    [Called By] + +

    _tx_timer_thread_entry (Thumb, 536 bytes, Stack size 104 bytes, tx_timer_thread_entry.o(.text._tx_timer_thread_entry)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    _txe_byte_pool_create (Thumb, 372 bytes, Stack size 80 bytes, txe_byte_pool_create.o(.text._txe_byte_pool_create)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    main (Thumb, 32 bytes, Stack size 16 bytes, main.o(.text.main)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    tx_application_define (Thumb, 88 bytes, Stack size 24 bytes, app_azure_rtos.o(.text.tx_application_define)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    _fp_init (Thumb, 26 bytes, Stack size 0 bytes, fpinit.o(x$fpl$fpinit)) +

    [Called By]

    + +

    __fplib_config_fpu_vfp (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) + +

    __fplib_config_pureend_doubles (Thumb, 0 bytes, Stack size unknown bytes, fpinit.o(x$fpl$fpinit), UNUSED) +

    +

    +Local Symbols +

    +

    __NVIC_SetPriorityGrouping (Thumb, 60 bytes, Stack size 12 bytes, stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping)) +

    [Stack]

    +
    [Called By] + +

    __NVIC_GetPriorityGrouping (Thumb, 16 bytes, Stack size 0 bytes, stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping)) +

    [Called By]

    + +

    NVIC_EncodePriority (Thumb, 108 bytes, Stack size 32 bytes, stm32h5xx_hal_cortex.o(.text.NVIC_EncodePriority)) +

    [Stack]

    +
    [Called By] + +

    __NVIC_SetPriority (Thumb, 66 bytes, Stack size 8 bytes, stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriority)) +

    [Stack]

    +
    [Called By] + +

    __NVIC_EnableIRQ (Thumb, 48 bytes, Stack size 4 bytes, stm32h5xx_hal_cortex.o(.text.__NVIC_EnableIRQ)) +

    [Stack]

    +
    [Called By] + +

    RCCEx_PLL2_Config (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    RCCEx_PLL3_Config (Thumb, 364 bytes, Stack size 24 bytes, stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    UART_EndRxTransfer (Thumb, 158 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer)) +

    [Stack]

    +
    [Called By] + +

    UART_DMAAbortOnError (Thumb, 30 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError)) +

    [Stack]

    +
    [Calls] +
    [Address Reference Count : 1] +

    UART_EndTransmit_IT (Thumb, 68 bytes, Stack size 16 bytes, stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT)) +

    [Stack]

    +
    [Calls] +
    [Called By] + +

    UARTEx_SetNbDataToProcess (Thumb, 138 bytes, Stack size 8 bytes, stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess)) +

    [Stack]

    +
    [Called By] +

    +

    +Undefined Global Symbols +


    diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp b/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp new file mode 100644 index 0000000..53e8f48 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.lnp @@ -0,0 +1,199 @@ +--cpu=Cortex-M33 +"autoguidestick\startup_stm32h563xx.o" +"autoguidestick\main.o" +"autoguidestick\tx_initialize_low_level.o" +"autoguidestick\gpio.o" +"autoguidestick\memorymap.o" +"autoguidestick\app_threadx.o" +"autoguidestick\usart.o" +"autoguidestick\stm32h5xx_it.o" +"autoguidestick\stm32h5xx_hal_msp.o" +"autoguidestick\stm32h5xx_hal_timebase_tim.o" +"autoguidestick\app_azure_rtos.o" +"autoguidestick\stm32h5xx_hal_tim.o" +"autoguidestick\stm32h5xx_hal_tim_ex.o" +"autoguidestick\stm32h5xx_hal_cortex.o" +"autoguidestick\stm32h5xx_hal_rcc.o" +"autoguidestick\stm32h5xx_hal_rcc_ex.o" +"autoguidestick\stm32h5xx_hal_flash.o" +"autoguidestick\stm32h5xx_hal_flash_ex.o" +"autoguidestick\stm32h5xx_hal_gpio.o" +"autoguidestick\stm32h5xx_hal_dma.o" +"autoguidestick\stm32h5xx_hal_dma_ex.o" +"autoguidestick\stm32h5xx_hal_pwr.o" +"autoguidestick\stm32h5xx_hal_pwr_ex.o" +"autoguidestick\stm32h5xx_hal.o" +"autoguidestick\stm32h5xx_hal_exti.o" +"autoguidestick\stm32h5xx_hal_uart.o" +"autoguidestick\stm32h5xx_hal_uart_ex.o" +"autoguidestick\system_stm32h5xx.o" +"autoguidestick\tx_initialize_high_level.o" +"autoguidestick\tx_initialize_kernel_enter.o" +"autoguidestick\tx_initialize_kernel_setup.o" +"autoguidestick\tx_thread_context_restore.o" +"autoguidestick\tx_thread_context_save.o" +"autoguidestick\tx_thread_interrupt_control.o" +"autoguidestick\tx_thread_interrupt_disable.o" +"autoguidestick\tx_thread_interrupt_restore.o" +"autoguidestick\tx_thread_schedule.o" +"autoguidestick\tx_thread_stack_build.o" +"autoguidestick\tx_thread_system_return.o" +"autoguidestick\tx_timer_interrupt.o" +"autoguidestick\tx_thread_stack_error_handler.o" +"autoguidestick\tx_thread_stack_error_notify.o" +"autoguidestick\tx_thread_system_resume.o" +"autoguidestick\tx_block_allocate.o" +"autoguidestick\tx_block_pool_cleanup.o" +"autoguidestick\tx_block_pool_create.o" +"autoguidestick\tx_block_pool_delete.o" +"autoguidestick\tx_block_pool_info_get.o" +"autoguidestick\tx_block_pool_initialize.o" +"autoguidestick\tx_block_pool_prioritize.o" +"autoguidestick\tx_block_release.o" +"autoguidestick\tx_byte_allocate.o" +"autoguidestick\tx_byte_pool_cleanup.o" +"autoguidestick\tx_byte_pool_create.o" +"autoguidestick\tx_byte_pool_delete.o" +"autoguidestick\tx_byte_pool_info_get.o" +"autoguidestick\tx_byte_pool_initialize.o" +"autoguidestick\tx_byte_pool_prioritize.o" +"autoguidestick\tx_byte_pool_search.o" +"autoguidestick\tx_byte_release.o" +"autoguidestick\tx_event_flags_cleanup.o" +"autoguidestick\tx_event_flags_create.o" +"autoguidestick\tx_event_flags_delete.o" +"autoguidestick\tx_event_flags_get.o" +"autoguidestick\tx_event_flags_info_get.o" +"autoguidestick\tx_event_flags_initialize.o" +"autoguidestick\tx_event_flags_set.o" +"autoguidestick\tx_event_flags_set_notify.o" +"autoguidestick\tx_mutex_cleanup.o" +"autoguidestick\tx_mutex_create.o" +"autoguidestick\tx_mutex_delete.o" +"autoguidestick\tx_mutex_get.o" +"autoguidestick\tx_mutex_info_get.o" +"autoguidestick\tx_mutex_initialize.o" +"autoguidestick\tx_mutex_prioritize.o" +"autoguidestick\tx_mutex_priority_change.o" +"autoguidestick\tx_mutex_put.o" +"autoguidestick\tx_queue_cleanup.o" +"autoguidestick\tx_queue_create.o" +"autoguidestick\tx_queue_delete.o" +"autoguidestick\tx_queue_flush.o" +"autoguidestick\tx_queue_front_send.o" +"autoguidestick\tx_queue_info_get.o" +"autoguidestick\tx_queue_initialize.o" +"autoguidestick\tx_queue_prioritize.o" +"autoguidestick\tx_queue_receive.o" +"autoguidestick\tx_queue_send.o" +"autoguidestick\tx_queue_send_notify.o" +"autoguidestick\tx_semaphore_ceiling_put.o" +"autoguidestick\tx_semaphore_cleanup.o" +"autoguidestick\tx_semaphore_create.o" +"autoguidestick\tx_semaphore_delete.o" +"autoguidestick\tx_semaphore_get.o" +"autoguidestick\tx_semaphore_info_get.o" +"autoguidestick\tx_semaphore_initialize.o" +"autoguidestick\tx_semaphore_prioritize.o" +"autoguidestick\tx_semaphore_put.o" +"autoguidestick\tx_semaphore_put_notify.o" +"autoguidestick\tx_thread_create.o" +"autoguidestick\tx_thread_delete.o" +"autoguidestick\tx_thread_entry_exit_notify.o" +"autoguidestick\tx_thread_identify.o" +"autoguidestick\tx_thread_info_get.o" +"autoguidestick\tx_thread_initialize.o" +"autoguidestick\tx_thread_preemption_change.o" +"autoguidestick\tx_thread_priority_change.o" +"autoguidestick\tx_thread_relinquish.o" +"autoguidestick\tx_thread_reset.o" +"autoguidestick\tx_thread_resume.o" +"autoguidestick\tx_thread_shell_entry.o" +"autoguidestick\tx_thread_sleep.o" +"autoguidestick\tx_thread_stack_analyze.o" +"autoguidestick\tx_thread_suspend.o" +"autoguidestick\tx_thread_system_preempt_check.o" +"autoguidestick\tx_thread_system_suspend.o" +"autoguidestick\tx_thread_terminate.o" +"autoguidestick\tx_thread_time_slice.o" +"autoguidestick\tx_thread_time_slice_change.o" +"autoguidestick\tx_thread_timeout.o" +"autoguidestick\tx_thread_wait_abort.o" +"autoguidestick\tx_time_get.o" +"autoguidestick\tx_time_set.o" +"autoguidestick\txe_block_allocate.o" +"autoguidestick\txe_block_pool_create.o" +"autoguidestick\txe_block_pool_delete.o" +"autoguidestick\txe_block_pool_info_get.o" +"autoguidestick\txe_block_pool_prioritize.o" +"autoguidestick\txe_block_release.o" +"autoguidestick\txe_byte_allocate.o" +"autoguidestick\txe_byte_pool_create.o" +"autoguidestick\txe_byte_pool_delete.o" +"autoguidestick\txe_byte_pool_info_get.o" +"autoguidestick\txe_byte_pool_prioritize.o" +"autoguidestick\txe_byte_release.o" +"autoguidestick\txe_event_flags_create.o" +"autoguidestick\txe_event_flags_delete.o" +"autoguidestick\txe_event_flags_get.o" +"autoguidestick\txe_event_flags_info_get.o" +"autoguidestick\txe_event_flags_set.o" +"autoguidestick\txe_event_flags_set_notify.o" +"autoguidestick\txe_mutex_create.o" +"autoguidestick\txe_mutex_delete.o" +"autoguidestick\txe_mutex_get.o" +"autoguidestick\txe_mutex_info_get.o" +"autoguidestick\txe_mutex_prioritize.o" +"autoguidestick\txe_mutex_put.o" +"autoguidestick\txe_queue_create.o" +"autoguidestick\txe_queue_delete.o" +"autoguidestick\txe_queue_flush.o" +"autoguidestick\txe_queue_front_send.o" +"autoguidestick\txe_queue_info_get.o" +"autoguidestick\txe_queue_prioritize.o" +"autoguidestick\txe_queue_receive.o" +"autoguidestick\txe_queue_send.o" +"autoguidestick\txe_queue_send_notify.o" +"autoguidestick\txe_semaphore_ceiling_put.o" +"autoguidestick\txe_semaphore_create.o" +"autoguidestick\txe_semaphore_delete.o" +"autoguidestick\txe_semaphore_get.o" +"autoguidestick\txe_semaphore_info_get.o" +"autoguidestick\txe_semaphore_prioritize.o" +"autoguidestick\txe_semaphore_put.o" +"autoguidestick\txe_semaphore_put_notify.o" +"autoguidestick\txe_thread_create.o" +"autoguidestick\txe_thread_delete.o" +"autoguidestick\txe_thread_entry_exit_notify.o" +"autoguidestick\txe_thread_info_get.o" +"autoguidestick\txe_thread_preemption_change.o" +"autoguidestick\txe_thread_priority_change.o" +"autoguidestick\txe_thread_relinquish.o" +"autoguidestick\txe_thread_reset.o" +"autoguidestick\txe_thread_resume.o" +"autoguidestick\txe_thread_suspend.o" +"autoguidestick\txe_thread_terminate.o" +"autoguidestick\txe_thread_time_slice_change.o" +"autoguidestick\txe_thread_wait_abort.o" +"autoguidestick\tx_timer_activate.o" +"autoguidestick\tx_timer_change.o" +"autoguidestick\tx_timer_create.o" +"autoguidestick\tx_timer_deactivate.o" +"autoguidestick\tx_timer_delete.o" +"autoguidestick\tx_timer_expiration_process.o" +"autoguidestick\tx_timer_info_get.o" +"autoguidestick\tx_timer_initialize.o" +"autoguidestick\tx_timer_system_activate.o" +"autoguidestick\tx_timer_system_deactivate.o" +"autoguidestick\tx_timer_thread_entry.o" +"autoguidestick\txe_timer_activate.o" +"autoguidestick\txe_timer_change.o" +"autoguidestick\txe_timer_create.o" +"autoguidestick\txe_timer_deactivate.o" +"autoguidestick\txe_timer_delete.o" +"autoguidestick\txe_timer_info_get.o" +"autoguidestick\hcble.o" +--strict --scatter "AutoGuideStick\AutoGuideStick.sct" +--summary_stderr --info summarysizes --map --load_addr_map_info --xref --callgraph --symbols +--info sizes --info totals --info unused --info veneers +--list "AutoGuideStick.map" -o AutoGuideStick\AutoGuideStick.axf \ No newline at end of file diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.map b/MDK-ARM/AutoGuideStick/AutoGuideStick.map new file mode 100644 index 0000000..1611e97 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.map @@ -0,0 +1,5368 @@ +Component: Arm Compiler for Embedded 6.21 Tool: armlink [5ec1fa00] + +============================================================================== + +Section Cross References + + startup_stm32h563xx.o(STACK) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h563xx.o(HEAP) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h563xx.o(RESET) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h563xx.o(RESET) refers to startup_stm32h563xx.o(STACK) for __initial_sp + startup_stm32h563xx.o(RESET) refers to startup_stm32h563xx.o(.text) for Reset_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.NMI_Handler) for NMI_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.HardFault_Handler) for HardFault_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.MemManage_Handler) for MemManage_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.BusFault_Handler) for BusFault_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.UsageFault_Handler) for UsageFault_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.DebugMon_Handler) for DebugMon_Handler + startup_stm32h563xx.o(RESET) refers to tx_thread_schedule.o(.text) for PendSV_Handler + startup_stm32h563xx.o(RESET) refers to tx_initialize_low_level.o(.text) for SysTick_Handler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) for TIM1_UP_IRQHandler + startup_stm32h563xx.o(RESET) refers to stm32h5xx_it.o(.text.USART1_IRQHandler) for USART1_IRQHandler + startup_stm32h563xx.o(.text) refers (Special) to heapauxi.o(.text) for __use_two_region_memory + startup_stm32h563xx.o(.text) refers to system_stm32h5xx.o(.text.SystemInit) for SystemInit + startup_stm32h563xx.o(.text) refers to __main.o(!!!main) for __main + startup_stm32h563xx.o(.text) refers to startup_stm32h563xx.o(HEAP) for Heap_Mem + startup_stm32h563xx.o(.text) refers to startup_stm32h563xx.o(STACK) for Stack_Mem + main.o(.text.main) refers to stm32h5xx_hal.o(.text.HAL_Init) for HAL_Init + main.o(.text.main) refers to main.o(.text.SystemClock_Config) for SystemClock_Config + main.o(.text.main) refers to gpio.o(.text.MX_GPIO_Init) for MX_GPIO_Init + main.o(.text.main) refers to usart.o(.text.MX_USART1_UART_Init) for MX_USART1_UART_Init + main.o(.text.main) refers to app_threadx.o(.text.MX_ThreadX_Init) for MX_ThreadX_Init + main.o(.ARM.exidx.text.main) refers to main.o(.text.main) for [Anonymous Symbol] + main.o(.text.SystemClock_Config) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + main.o(.text.SystemClock_Config) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for HAL_RCC_OscConfig + main.o(.text.SystemClock_Config) refers to main.o(.text.Error_Handler) for Error_Handler + main.o(.text.SystemClock_Config) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for HAL_RCC_ClockConfig + main.o(.ARM.exidx.text.SystemClock_Config) refers to main.o(.text.SystemClock_Config) for [Anonymous Symbol] + main.o(.ARM.exidx.text.Error_Handler) refers to main.o(.text.Error_Handler) for [Anonymous Symbol] + main.o(.text.HAL_TIM_PeriodElapsedCallback) refers to stm32h5xx_hal.o(.text.HAL_IncTick) for HAL_IncTick + main.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for [Anonymous Symbol] + tx_initialize_low_level.o(.text) refers to tx_timer_interrupt.o(.text) for _tx_timer_interrupt + tx_initialize_low_level.o(.text) refers to startup_stm32h563xx.o(RESET) for __Vectors + tx_initialize_low_level.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_system_stack_ptr) for _tx_thread_system_stack_ptr + gpio.o(.ARM.exidx.text.MX_GPIO_Init) refers to gpio.o(.text.MX_GPIO_Init) for [Anonymous Symbol] + app_threadx.o(.ARM.exidx.text.App_ThreadX_Init) refers to app_threadx.o(.text.App_ThreadX_Init) for [Anonymous Symbol] + app_threadx.o(.text.MX_ThreadX_Init) refers to tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) for _tx_initialize_kernel_enter + app_threadx.o(.ARM.exidx.text.MX_ThreadX_Init) refers to app_threadx.o(.text.MX_ThreadX_Init) for [Anonymous Symbol] + usart.o(.text.MX_USART1_UART_Init) refers to usart.o(.bss.huart1) for huart1 + usart.o(.text.MX_USART1_UART_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Init) for HAL_UART_Init + usart.o(.text.MX_USART1_UART_Init) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.text.MX_USART1_UART_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold) for HAL_UARTEx_SetTxFifoThreshold + usart.o(.text.MX_USART1_UART_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold) for HAL_UARTEx_SetRxFifoThreshold + usart.o(.text.MX_USART1_UART_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode) for HAL_UARTEx_DisableFifoMode + usart.o(.ARM.exidx.text.MX_USART1_UART_Init) refers to usart.o(.text.MX_USART1_UART_Init) for [Anonymous Symbol] + usart.o(.text.HAL_UART_MspInit) refers to rt_memclr_w.o(.text) for __aeabi_memclr8 + usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for HAL_RCCEx_PeriphCLKConfig + usart.o(.text.HAL_UART_MspInit) refers to main.o(.text.Error_Handler) for Error_Handler + usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + usart.o(.text.HAL_UART_MspInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + usart.o(.ARM.exidx.text.HAL_UART_MspInit) refers to usart.o(.text.HAL_UART_MspInit) for [Anonymous Symbol] + usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for HAL_GPIO_DeInit + usart.o(.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for HAL_NVIC_DisableIRQ + usart.o(.ARM.exidx.text.HAL_UART_MspDeInit) refers to usart.o(.text.HAL_UART_MspDeInit) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.NMI_Handler) refers to stm32h5xx_it.o(.text.NMI_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.HardFault_Handler) refers to stm32h5xx_it.o(.text.HardFault_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.MemManage_Handler) refers to stm32h5xx_it.o(.text.MemManage_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.BusFault_Handler) refers to stm32h5xx_it.o(.text.BusFault_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.UsageFault_Handler) refers to stm32h5xx_it.o(.text.UsageFault_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.ARM.exidx.text.DebugMon_Handler) refers to stm32h5xx_it.o(.text.DebugMon_Handler) for [Anonymous Symbol] + stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) refers to stm32h5xx_hal_timebase_tim.o(.bss.htim1) for htim1 + stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for HAL_TIM_IRQHandler + stm32h5xx_it.o(.ARM.exidx.text.TIM1_UP_IRQHandler) refers to stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) for [Anonymous Symbol] + stm32h5xx_it.o(.text.USART1_IRQHandler) refers to usart.o(.bss.huart1) for huart1 + stm32h5xx_it.o(.text.USART1_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) for HAL_UART_IRQHandler + stm32h5xx_it.o(.ARM.exidx.text.USART1_IRQHandler) refers to stm32h5xx_it.o(.text.USART1_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit) refers to stm32h5xx_hal_msp.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for HAL_RCC_GetClockConfig + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for HAL_RCC_GetPCLK2Freq + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_timebase_tim.o(.bss.htim1) for htim1 + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) for HAL_TIM_Base_Init + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) for HAL_TIM_Base_Start_IT + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for HAL_NVIC_EnableIRQ + stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_InitTick) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for [Anonymous Symbol] + stm32h5xx_hal_timebase_tim.o(.text.HAL_SuspendTick) refers to stm32h5xx_hal_timebase_tim.o(.bss.htim1) for htim1 + stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_SuspendTick) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_SuspendTick) for [Anonymous Symbol] + stm32h5xx_hal_timebase_tim.o(.text.HAL_ResumeTick) refers to stm32h5xx_hal_timebase_tim.o(.bss.htim1) for htim1 + stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_ResumeTick) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_ResumeTick) for [Anonymous Symbol] + app_azure_rtos.o(.text.tx_application_define) refers to app_azure_rtos.o(.bss.tx_app_byte_pool) for tx_app_byte_pool + app_azure_rtos.o(.text.tx_application_define) refers to app_azure_rtos.o(.rodata.str1.1) for .L.str + app_azure_rtos.o(.text.tx_application_define) refers to app_azure_rtos.o(.bss.tx_byte_pool_buffer) for tx_byte_pool_buffer + app_azure_rtos.o(.text.tx_application_define) refers to txe_byte_pool_create.o(.text._txe_byte_pool_create) for _txe_byte_pool_create + app_azure_rtos.o(.text.tx_application_define) refers to app_threadx.o(.text.App_ThreadX_Init) for App_ThreadX_Init + app_azure_rtos.o(.ARM.exidx.text.tx_application_define) refers to app_azure_rtos.o(.text.tx_application_define) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for HAL_TIM_Base_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for HAL_TIM_Base_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for HAL_TIM_PeriodElapsedHalfCpltCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMAError) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for HAL_DMAEx_List_Start_IT + stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMA_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for HAL_TIM_OC_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for HAL_TIM_OC_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for HAL_TIM_PWM_PulseFinishedHalfCpltCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for HAL_TIM_PWM_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for HAL_TIM_PWM_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for HAL_TIM_IC_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for HAL_TIM_IC_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for HAL_TIM_IC_CaptureHalfCpltCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for HAL_TIM_OnePulse_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for HAL_TIM_OnePulse_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for HAL_TIM_Encoder_MspInit + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for HAL_TIM_Encoder_MspDeInit + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for HAL_TIM_IC_CaptureCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for HAL_TIM_OC_DelayElapsedCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to main.o(.text.HAL_TIM_PeriodElapsedCallback) for HAL_TIM_PeriodElapsedCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for HAL_TIMEx_BreakCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) for HAL_TIMEx_Break2Callback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback) for HAL_TIMEx_EncoderIndexCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback) for HAL_TIMEx_DirectionChangeCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback) for HAL_TIMEx_IndexErrorCallback + stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback) for HAL_TIMEx_TransitionErrorCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC5_SetConfig) for TIM_OC5_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC6_SetConfig) for TIM_OC6_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC1_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC3_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC4_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC5_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC5_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC6_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_OC6_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig) for TIM_TI3_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig) for TIM_TI4_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC3_SetConfig) for TIM_OC3_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC4_SetConfig) for TIM_OC4_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC5_SetConfig) for TIM_OC5_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC6_SetConfig) for TIM_OC6_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC1_SetConfig) for TIM_OC1_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig) for TIM_TI2_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for HAL_TIM_DMABurst_MultiWriteStart + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt) for TIM_DMADelayPulseCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMATriggerCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) for HAL_TIM_TriggerCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for HAL_TIM_TriggerHalfCpltCallback + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for HAL_TIM_DMABurst_MultiReadStart + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt) for TIM_DMAPeriodElapsedCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt) for TIM_DMAPeriodElapsedHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerCplt) for TIM_DMATriggerCplt + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt) for TIM_DMATriggerHalfCplt + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_GenerateEvent) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) refers to stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for TIM_ITRx_SetConfig + stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) refers to stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage) for TIM_TI1_ConfigInputStage + stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage) for TIM_TI2_ConfigInputStage + stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig) refers to stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig) for TIM_SlaveTimer_SetConfig + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_GetChannelState) for [Anonymous Symbol] + stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurstState) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for HAL_TIMEx_HallSensor_MspInit + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) for TIM_Base_SetConfig + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig) for TIM_TI1_SetConfig + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) refers to stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig) for TIM_OC2_SetConfig + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for HAL_TIMEx_HallSensor_MspDeInit + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt) for TIM_DMACaptureCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt) for TIM_DMACaptureHalfCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) for HAL_TIM_PWM_PulseFinishedCallback + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) refers to stm32h5xx_hal_tim.o(.text.HAL_TIM_ErrorCallback) for HAL_TIM_ErrorCallback + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt) for TIM_DMADelayPulseNCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt) for TIM_DMADelayPulseHalfCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN) for TIM_DMAErrorCCxN + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT) for TIM_DMA_Start_IT + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd) for TIM_CCxNChannelCmd + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd) for TIM_CCxChannelCmd + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for TIMEx_DMACommutationCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for TIMEx_DMACommutationHalfCplt + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h5xx_hal_tim.o(.text.TIM_DMAError) for TIM_DMAError + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for HAL_TIMEx_CommutCallback + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for HAL_TIMEx_CommutHalfCpltCallback + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt) refers to stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakInput) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakInput) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TISelection) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TISelection) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GroupChannel5) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_GroupChannel5) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisarmBreakInput) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisarmBreakInput) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ReArmBreakInput) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DitheringEnable) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DitheringEnable) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DitheringDisable) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DitheringDisable) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OC_ConfigPulseOnCompare) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OC_ConfigPulseOnCompare) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigSlaveModePreload) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigSlaveModePreload) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableSlaveModePreload) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableSlaveModePreload) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableSlaveModePreload) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableSlaveModePreload) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableDeadTimePreload) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableDeadTimePreload) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableDeadTimePreload) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableDeadTimePreload) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigDeadTime) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigDeadTime) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigAsymmetricalDeadTime) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigAsymmetricalDeadTime) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableAsymmetricalDeadTime) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableAsymmetricalDeadTime) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableAsymmetricalDeadTime) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableAsymmetricalDeadTime) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigEncoderIndex) refers to stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig) for TIM_ETR_SetConfig + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigEncoderIndex) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigEncoderIndex) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableEncoderIndex) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableEncoderIndex) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableEncoderIndex) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableEncoderIndex) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableEncoderFirstIndex) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableEncoderFirstIndex) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableEncoderFirstIndex) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableEncoderFirstIndex) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_Break2Callback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EncoderIndexCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DirectionChangeCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_IndexErrorCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TransitionErrorCallback) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState) for [Anonymous Symbol] + stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState) refers to stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for __NVIC_SetPriorityGrouping + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriorityGrouping) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h5xx_hal_cortex.o(.text.NVIC_EncodePriority) for NVIC_EncodePriority + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriority) for __NVIC_SetPriority + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority) refers to stm32h5xx_hal_cortex.o(.text.NVIC_EncodePriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for __NVIC_EnableIRQ + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_EnableIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for __NVIC_DisableIRQ + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_DisableIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SystemReset) for __NVIC_SystemReset + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SystemReset) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SystemReset) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriorityGrouping) for __NVIC_GetPriorityGrouping + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriority) for __NVIC_GetPriority + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) refers to stm32h5xx_hal_cortex.o(.text.NVIC_DecodePriority) for NVIC_DecodePriority + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority) refers to stm32h5xx_hal_cortex.o(.text.NVIC_DecodePriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriority) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for __NVIC_SetPendingIRQ + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for __NVIC_GetPendingIRQ + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for __NVIC_ClearPendingIRQ + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetActive) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetActive) for __NVIC_GetActive + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetActive) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive) refers to stm32h5xx_hal_cortex.o(.text.__NVIC_GetActive) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_GetCLKSourceConfig) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_GetCLKSourceConfig) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for HAL_SYSTICK_Callback + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Callback) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_Enable) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_Disable) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_EnableRegion) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_DisableRegion) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigRegion) for MPU_ConfigRegion + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigRegion) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigRegion) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes) for MPU_ConfigMemoryAttributes + stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigMemoryAttributes) for [Anonymous Symbol] + stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigMemoryAttributes) refers to stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32h5xx.o(.rodata.AHBPrescTable) for AHBPrescTable + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32h5xx.o(.rodata.AHBPrescTable) for AHBPrescTable + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for HAL_GPIO_Init + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_MCOConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) refers to system_stm32h5xx.o(.rodata.APBPrescTable) for APBPrescTable + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) refers to system_stm32h5xx.o(.rodata.APBPrescTable) for APBPrescTable + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq) refers to system_stm32h5xx.o(.rodata.APBPrescTable) for APBPrescTable + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK3Freq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetResetSource) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetResetSource) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_EnableCSS) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for HAL_RCC_CSSCallback + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_CSSCallback) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ConfigAttributes) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_ConfigAttributes) for [Anonymous Symbol] + stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetConfigAttributes) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetConfigAttributes) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) for RCCEx_PLL2_Config + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) for RCCEx_PLL3_Config + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL2_Config) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL2_Config) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL3_Config) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLL3_Config) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL1ClockFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL2ClockFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL3ClockFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq) for HAL_RCCEx_GetPLL1ClockFreq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq) for HAL_RCCEx_GetPLL2ClockFreq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq) for HAL_RCCEx_GetPLL3ClockFreq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) for HAL_RCC_GetPCLK2Freq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) for HAL_RCC_GetPCLK1Freq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq) for HAL_RCC_GetPCLK3Freq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) for HAL_RCC_GetHCLKFreq + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL2) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL2) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLLSource_Enable) for RCCEx_PLLSource_Enable + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLL2) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL2) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLLSource_Enable) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLLSource_Enable) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLLSource_Enable) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL2) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLL2) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL2) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL3) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL3) refers to stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLLSource_Enable) for RCCEx_PLLSource_Enable + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLL3) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL3) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL3) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLL3) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL3) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WakeUpStopCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_WakeUpStopCLKConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_KerWakeUpStopCLKConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_KerWakeUpStopCLKConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSECSS) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSECSS) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback) for HAL_RCCEx_LSECSS_Callback + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_Callback) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSCO) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for HAL_PWR_EnableBkUpAccess + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSCO) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for HAL_PWR_DisableBkUpAccess + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSCO) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSCO) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSCO) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for HAL_PWR_EnableBkUpAccess + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSCO) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for HAL_PWR_DisableBkUpAccess + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSCO) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSCO) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSConfig) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSGetSynchronizationInfo) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSGetSynchronizationInfo) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSWaitSynchronization) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback) for HAL_RCCEx_CRS_SyncOkCallback + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback) for HAL_RCCEx_CRS_SyncWarnCallback + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback) for HAL_RCCEx_CRS_ExpectedSyncCallback + stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback) for HAL_RCCEx_CRS_ErrorCallback + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_IRQHandler) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncOkCallback) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncWarnCallback) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ExpectedSyncCallback) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback) for [Anonymous Symbol] + stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ErrorCallback) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord) for FLASH_Program_QuadWord + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord_OBK) for FLASH_Program_QuadWord_OBK + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_HalfWord) for FLASH_Program_HalfWord + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_Word) for FLASH_Program_Word + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_QuadWord) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord_OBK) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_QuadWord_OBK) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord_OBK) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_HalfWord) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_HalfWord) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Word) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_Word) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord) for FLASH_Program_QuadWord + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord_OBK) for FLASH_Program_QuadWord_OBK + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_HalfWord) for FLASH_Program_HalfWord + stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_Program_Word) for FLASH_Program_Word + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for HAL_FLASH_OperationErrorCallback + stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for HAL_FLASH_EndOfOperationCallback + stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) refers (Weak) to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccCorrectionCallback) for HAL_FLASHEx_EccCorrectionCallback + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_Unlock) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_Lock) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Lock) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Launch) for [Anonymous Symbol] + stm32h5xx_hal_flash.o(.text.HAL_FLASH_GetError) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError) refers to stm32h5xx_hal_flash.o(.text.HAL_FLASH_GetError) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OBKErase) for FLASH_OBKErase + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_MassErase) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OBKErase) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OBKErase) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_MassErase) for FLASH_MassErase + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OBKErase) for FLASH_OBKErase + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_Erase_Sector) for FLASH_Erase_Sector + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for FLASH_OB_EnableWRP + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for FLASH_OB_DisableWRP + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_ProdStateConfig) for FLASH_OB_ProdStateConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for FLASH_OB_UserConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootAddrConfig) for FLASH_OB_BootAddrConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootLockConfig) for FLASH_OB_BootLockConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_LockConfig) for FLASH_OB_OTP_LockConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_HDPConfig) for FLASH_OB_HDPConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EDATAConfig) for FLASH_OB_EDATAConfig + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_ProdStateConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_ProdStateConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootAddrConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootAddrConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootLockConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootLockConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_OTP_LockConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_LockConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_HDPConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_HDPConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EDATAConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EDATAConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetProdState) for FLASH_OB_GetProdState + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for FLASH_OB_GetUser + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for FLASH_OB_GetWRP + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetHDP) for FLASH_OB_GetHDP + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetEDATA) for FLASH_OB_GetEDATA + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetBootConfig) for FLASH_OB_GetBootConfig + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_GetLock) for FLASH_OB_OTP_GetLock + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetProdState) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetProdState) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetUser) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetHDP) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetHDP) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetEDATA) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetEDATA) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBootConfig) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetBootConfig) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_OTP_GetLock) refers to stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_GetLock) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Unlock) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Unlock) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Lock) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Lock) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Swap) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap_IT) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Swap_IT) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap_IT) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetOperation) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetOperation) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigBBAttributes) refers to stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation) for FLASH_WaitForLastOperation + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigBBAttributes) refers to stm32h5xx_hal_flash.o(.data.pFlash) for pFlash + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigBBAttributes) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigBBAttributes) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetConfigBBAttributes) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetConfigBBAttributes) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigPrivMode) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigPrivMode) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetPrivMode) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetPrivMode) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigHDPExtension) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigHDPExtension) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EnableEccCorrectionInterrupt) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EnableEccCorrectionInterrupt) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_DisableEccCorrectionInterrupt) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_DisableEccCorrectionInterrupt) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetEccInfo) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetEccInfo) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ECCD_IRQHandler) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccDetectionCallback) for HAL_FLASHEx_EccDetectionCallback + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ECCD_IRQHandler) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ECCD_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EccDetectionCallback) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccDetectionCallback) for [Anonymous Symbol] + stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EccCorrectionCallback) refers to stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccCorrectionCallback) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_ReadPin) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WriteMultipleStatePin) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WriteMultipleStatePin) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_TogglePin) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_LockPin) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EnableHighSPeedLowVoltage) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EnableHighSPeedLowVoltage) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DisableHighSPeedLowVoltage) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DisableHighSPeedLowVoltage) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Rising_Callback) for HAL_GPIO_EXTI_Rising_Callback + stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Falling_Callback) for HAL_GPIO_EXTI_Falling_Callback + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Rising_Callback) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Rising_Callback) for [Anonymous Symbol] + stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Falling_Callback) refers to stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Falling_Callback) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for DMA_Init + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Init) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init) refers to stm32h5xx_hal_dma.o(.text.DMA_Init) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.DMA_SetConfig) for DMA_SetConfig + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes) for [Anonymous Symbol] + stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for DMA_List_Init + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for DMA_List_BuildNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for DMA_List_GetNodeConfig + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for DMA_List_ResetQueueNodes + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses) for DMA_List_CheckNodesBaseAddresses + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes) for DMA_List_CheckNodesTypes + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue) for DMA_List_CleanQueue + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode) for DMA_List_FindNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for DMA_List_ConvertNodeToDynamic + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for DMA_List_UpdateDynamicQueueNodesCLLR + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToDynamic.update_link + stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode + stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for DMA_List_ClearUnusedFields + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for DMA_List_UpdateStaticQueueNodesCLLR + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode) for DMA_List_FillNode + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for DMA_List_ConvertNodeToStatic + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo) for DMA_List_GetCLLRNodeInfo + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.rodata.cst32) for .L__const.DMA_List_ConvertNodeToStatic.update_link + stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for DMA_List_FormatNode + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode) for [Anonymous Symbol] + stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields) refers to stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnablePVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisablePVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for HAL_PWR_PVDCallback + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVDCallback) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigAttributes) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_ConfigAttributes) for [Anonymous Symbol] + stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_GetConfigAttributes) refers to stm32h5xx_hal_pwr.o(.text.HAL_PWR_GetConfigAttributes) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigSupply) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetSupplyConfig) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetSupplyConfig) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlStopModeVoltageScaling) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlStopModeVoltageScaling) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetStopModeVoltageRange) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetStopModeVoltageRange) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigAVD) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigAVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAVD) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAVD) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAVD) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBVoltageDetector) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBVoltageDetector) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBVoltageDetector) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBVoltageDetector) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableVddUSB) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableVddUSB) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableVddUSB) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableVddUSB) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMonitoring) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMonitoring) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMonitoring) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMonitoring) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUCPDStandbyMode) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUCPDStandbyMode) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUCPDStandbyMode) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUCPDStandbyMode) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUCPDDeadBattery) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUCPDDeadBattery) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUCPDDeadBattery) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUCPDDeadBattery) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBatteryCharging) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBatteryCharging) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBatteryCharging) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBatteryCharging) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAnalogBooster) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAnalogBooster) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAnalogBooster) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAnalogBooster) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Rising_Callback) for HAL_PWREx_PVD_AVD_Rising_Callback + stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Falling_Callback) for HAL_PWREx_PVD_AVD_Falling_Callback + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_IRQHandler) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_Rising_Callback) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Rising_Callback) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_Falling_Callback) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Falling_Callback) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableWakeUpPin) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableWakeUpPin) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableWakeUpPin) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableWakeUpPin) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMemoryShutOff) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMemoryShutOff) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMemoryShutOff) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMemoryShutOff) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkupRAMRetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkupRAMRetention) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkupRAMRetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkupRAMRetention) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableStandbyIORetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableStandbyIORetention) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableStandbyIORetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableStandbyIORetention) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableStandbyJTAGIORetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableStandbyJTAGIORetention) for [Anonymous Symbol] + stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableStandbyJTAGIORetention) refers to stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableStandbyJTAGIORetention) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_Init) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) for HAL_NVIC_SetPriorityGrouping + stm32h5xx_hal.o(.text.HAL_Init) refers to stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) for HAL_RCC_GetSysClockFreq + stm32h5xx_hal.o(.text.HAL_Init) refers to system_stm32h5xx.o(.rodata.AHBPrescTable) for AHBPrescTable + stm32h5xx_hal.o(.text.HAL_Init) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h5xx_hal.o(.text.HAL_Init) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig) for HAL_SYSTICK_CLKSourceConfig + stm32h5xx_hal.o(.text.HAL_Init) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h5xx_hal.o(.text.HAL_Init) refers to stm32h5xx_hal_msp.o(.text.HAL_MspInit) for HAL_MspInit + stm32h5xx_hal.o(.ARM.exidx.text.HAL_Init) refers to stm32h5xx_hal.o(.text.HAL_Init) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_InitTick) refers to stm32h5xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h5xx_hal.o(.text.HAL_InitTick) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + stm32h5xx_hal.o(.text.HAL_InitTick) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_GetCLKSourceConfig) for HAL_SYSTICK_GetCLKSourceConfig + stm32h5xx_hal.o(.text.HAL_InitTick) refers to stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Config) for HAL_SYSTICK_Config + stm32h5xx_hal.o(.text.HAL_InitTick) refers to stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) for HAL_NVIC_SetPriority + stm32h5xx_hal.o(.text.HAL_InitTick) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal.o(.ARM.exidx.text.HAL_InitTick) refers to stm32h5xx_hal.o(.text.HAL_InitTick) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_MspInit) refers to stm32h5xx_hal.o(.text.HAL_MspInit) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_DeInit) refers to stm32h5xx_hal.o(.text.HAL_MspDeInit) for HAL_MspDeInit + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DeInit) refers to stm32h5xx_hal.o(.text.HAL_DeInit) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_MspDeInit) refers to stm32h5xx_hal.o(.text.HAL_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_IncTick) refers to stm32h5xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h5xx_hal.o(.text.HAL_IncTick) refers to stm32h5xx_hal.o(.bss.uwTick) for uwTick + stm32h5xx_hal.o(.ARM.exidx.text.HAL_IncTick) refers to stm32h5xx_hal.o(.text.HAL_IncTick) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_GetTick) refers to stm32h5xx_hal.o(.bss.uwTick) for uwTick + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTick) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_GetTickPrio) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio) refers to stm32h5xx_hal.o(.text.HAL_GetTickPrio) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h5xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h5xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h5xx_hal.o(.data.uwTickPrio) for uwTickPrio + stm32h5xx_hal.o(.text.HAL_SetTickFreq) refers to stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) for HAL_InitTick + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq) refers to stm32h5xx_hal.o(.text.HAL_SetTickFreq) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_GetTickFreq) refers to stm32h5xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq) refers to stm32h5xx_hal.o(.text.HAL_GetTickFreq) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_Delay) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal.o(.text.HAL_Delay) refers to stm32h5xx_hal.o(.data.uwTickFreq) for uwTickFreq + stm32h5xx_hal.o(.ARM.exidx.text.HAL_Delay) refers to stm32h5xx_hal.o(.text.HAL_Delay) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SuspendTick) refers to stm32h5xx_hal.o(.text.HAL_SuspendTick) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_ResumeTick) refers to stm32h5xx_hal.o(.text.HAL_ResumeTick) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion) refers to stm32h5xx_hal.o(.text.HAL_GetHalVersion) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetREVID) refers to stm32h5xx_hal.o(.text.HAL_GetREVID) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetDEVID) refers to stm32h5xx_hal.o(.text.HAL_GetDEVID) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0) refers to stm32h5xx_hal.o(.text.HAL_GetUIDw0) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1) refers to stm32h5xx_hal.o(.text.HAL_GetUIDw1) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2) refers to stm32h5xx_hal.o(.text.HAL_GetUIDw2) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode) refers to stm32h5xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode) refers to stm32h5xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode) refers to stm32h5xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode) refers to stm32h5xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_VoltageScalingConfig) refers to stm32h5xx_hal.o(.text.HAL_VREFBUF_VoltageScalingConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_HighImpedanceConfig) refers to stm32h5xx_hal.o(.text.HAL_VREFBUF_HighImpedanceConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_TrimmingConfig) refers to stm32h5xx_hal.o(.text.HAL_VREFBUF_TrimmingConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.text.HAL_EnableVREFBUF) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal.o(.ARM.exidx.text.HAL_EnableVREFBUF) refers to stm32h5xx_hal.o(.text.HAL_EnableVREFBUF) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_DisableVREFBUF) refers to stm32h5xx_hal.o(.text.HAL_DisableVREFBUF) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ETHInterfaceSelect) refers to stm32h5xx_hal.o(.text.HAL_SBS_ETHInterfaceSelect) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EnableVddIO1CompensationCell) refers to stm32h5xx_hal.o(.text.HAL_SBS_EnableVddIO1CompensationCell) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_DisableVddIO1CompensationCell) refers to stm32h5xx_hal.o(.text.HAL_SBS_DisableVddIO1CompensationCell) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EnableVddIO2CompensationCell) refers to stm32h5xx_hal.o(.text.HAL_SBS_EnableVddIO2CompensationCell) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_DisableVddIO2CompensationCell) refers to stm32h5xx_hal.o(.text.HAL_SBS_DisableVddIO2CompensationCell) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDCompensationCodeSelect) refers to stm32h5xx_hal.o(.text.HAL_SBS_VDDCompensationCodeSelect) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDIOCompensationCodeSelect) refers to stm32h5xx_hal.o(.text.HAL_SBS_VDDIOCompensationCodeSelect) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetVddIO1CompensationCellReadyFlag) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetVddIO1CompensationCellReadyFlag) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetVddIO2CompensationCellReadyFlag) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetVddIO2CompensationCellReadyFlag) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDCompensationCodeConfig) refers to stm32h5xx_hal.o(.text.HAL_SBS_VDDCompensationCodeConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDIOCompensationCodeConfig) refers to stm32h5xx_hal.o(.text.HAL_SBS_VDDIOCompensationCodeConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetNMOSVddCompensationValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetNMOSVddCompensationValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetPMOSVddCompensationValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetPMOSVddCompensationValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetNMOSVddIO2CompensationValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetNMOSVddIO2CompensationValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetPMOSVddIO2CompensationValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetPMOSVddIO2CompensationValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_DisableECCNMI) refers to stm32h5xx_hal.o(.text.HAL_SBS_FLASH_DisableECCNMI) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_EnableECCNMI) refers to stm32h5xx_hal.o(.text.HAL_SBS_FLASH_EnableECCNMI) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_ECCNMI_IsDisabled) refers to stm32h5xx_hal.o(.text.HAL_SBS_FLASH_ECCNMI_IsDisabled) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_IncrementHDPLValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_IncrementHDPLValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetHDPLValue) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetHDPLValue) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EPOCHSelection) refers to stm32h5xx_hal.o(.text.HAL_SBS_EPOCHSelection) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetEPOCHSelection) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetEPOCHSelection) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_SetOBKHDPL) refers to stm32h5xx_hal.o(.text.HAL_SBS_SetOBKHDPL) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetOBKHDPL) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetOBKHDPL) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_OpenAccessPort) refers to stm32h5xx_hal.o(.text.HAL_SBS_OpenAccessPort) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_OpenDebug) refers to stm32h5xx_hal.o(.text.HAL_SBS_OpenDebug) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ConfigDebugLevel) refers to stm32h5xx_hal.o(.text.HAL_SBS_ConfigDebugLevel) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetDebugLevel) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetDebugLevel) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_LockDebugConfig) refers to stm32h5xx_hal.o(.text.HAL_SBS_LockDebugConfig) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ConfigDebugSecurity) refers to stm32h5xx_hal.o(.text.HAL_SBS_ConfigDebugSecurity) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetDebugSecurity) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetDebugSecurity) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_Lock) refers to stm32h5xx_hal.o(.text.HAL_SBS_Lock) for [Anonymous Symbol] + stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetLock) refers to stm32h5xx_hal.o(.text.HAL_SBS_GetLock) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetHandle) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetPending) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_ClearPending) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ConfigLineAttributes) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_ConfigLineAttributes) for [Anonymous Symbol] + stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLineAttributes) refers to stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetConfigLineAttributes) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32h5xx_hal_uart.o(.text.HAL_UART_Init) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for UART_AdvFeatureConfig + stm32h5xx_hal_uart.o(.text.HAL_UART_Init) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32h5xx_hal_uart.o(.text.HAL_UART_Init) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Init) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspInit) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_MspInit) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_AdvFeatureConfig) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_SetConfig) refers to stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) for HAL_RCCEx_GetPeriphCLKFreq + stm32h5xx_hal_uart.o(.text.UART_SetConfig) refers to stm32h5xx_hal_uart.o(.rodata.UARTPrescTable) for UARTPrescTable + stm32h5xx_hal_uart.o(.text.UART_SetConfig) refers to lludivv7m.o(.text) for __aeabi_uldivmod + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_SetConfig) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) refers to stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_CheckIdleState) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for UART_AdvFeatureConfig + stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_LIN_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32h5xx_hal_uart.o(.text.HAL_LIN_Init) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for UART_AdvFeatureConfig + stm32h5xx_hal_uart.o(.text.HAL_LIN_Init) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32h5xx_hal_uart.o(.text.HAL_LIN_Init) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_LIN_Init) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for UART_AdvFeatureConfig + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_Init) refers to stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_DeInit) refers to usart.o(.text.HAL_UART_MspDeInit) for HAL_UART_MspDeInit + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DeInit) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_DeInit) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspDeInit) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_MspDeInit) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit) refers to stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) refers to stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_WaitOnFlagUntilTimeout) refers to stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Receive) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart.o(.text.HAL_UART_Receive) refers to stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Receive) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT_FIFOEN) for UART_TxISR_16BIT_FIFOEN + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT_FIFOEN) for UART_TxISR_8BIT_FIFOEN + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT) for UART_TxISR_16BIT + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT) for UART_TxISR_8BIT + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_16BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT_FIFOEN) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_8BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT_FIFOEN) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_16BIT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_8BIT) refers to stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) for UART_Start_Receive_IT + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) for UART_RxISR_16BIT_FIFOEN + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) for UART_RxISR_8BIT_FIFOEN + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT) for UART_RxISR_16BIT + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT) for UART_RxISR_8BIT + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMATransmitCplt) for UART_DMATransmitCplt + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxHalfCplt) for UART_DMATxHalfCplt + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMAError) for UART_DMAError + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for HAL_DMAEx_List_Start_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_DMA) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMATransmitCplt) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback) for HAL_UART_TxCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATransmitCplt) refers to stm32h5xx_hal_uart.o(.text.UART_DMATransmitCplt) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMATxHalfCplt) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_TxHalfCpltCallback) for HAL_UART_TxHalfCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxHalfCplt) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMAError) refers to stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer) for UART_EndTxTransfer + stm32h5xx_hal_uart.o(.text.UART_DMAError) refers to stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32h5xx_hal_uart.o(.text.UART_DMAError) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAError) refers to stm32h5xx_hal_uart.o(.text.UART_DMAError) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) for UART_Start_Receive_DMA + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt) for UART_DMAReceiveCplt + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt) for UART_DMARxHalfCplt + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_DMAError) for UART_DMAError + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT) for HAL_DMAEx_List_Start_IT + stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT) for HAL_DMA_Start_IT + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAPause) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend) for HAL_DMAEx_Suspend + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAPause) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAPause) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_DMAPause) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAResume) refers to stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume) for HAL_DMAEx_Resume + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAResume) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_DMAResume) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer) for UART_EndTxTransfer + stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop) refers to stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAStop) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndTxTransfer) refers to stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndRxTransfer) refers to stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Abort) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError) for HAL_DMA_GetError + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxAbortCallback) for UART_DMATxAbortCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxAbortCallback) for UART_DMARxAbortCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMATxAbortCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxAbortCallback) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxAbortCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMARxAbortCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback) for HAL_UART_AbortCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxAbortCallback) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxAbortCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) for UART_DMATxOnlyAbortCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for HAL_UART_AbortTransmitCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for HAL_UART_AbortTransmitCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxOnlyAbortCallback) refers to stm32h5xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) for UART_DMARxOnlyAbortCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for HAL_UART_AbortReceiveCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for HAL_UART_AbortReceiveCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxOnlyAbortCallback) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.UART_EndRxTransfer) for UART_EndRxTransfer + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError) for UART_DMAAbortOnError + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) for HAL_DMA_Abort_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) for HAL_DMA_Abort + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback) for HAL_UARTEx_WakeupCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT) for UART_EndTransmit_IT + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback) for HAL_UARTEx_TxFifoEmptyCallback + stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback) for HAL_UARTEx_RxFifoFullCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_IRQHandler) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAAbortOnError) refers to stm32h5xx_hal_uart.o(.text.UART_DMAAbortOnError) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_RxEventCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback) for HAL_UART_TxCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndTransmit_IT) refers to stm32h5xx_hal_uart.o(.text.UART_EndTransmit_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_TxHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_RxCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ReceiverTimeout_Config) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ReceiverTimeout_Config) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_EnableReceiverTimeout) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_EnableReceiverTimeout) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DisableReceiverTimeout) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_DisableReceiverTimeout) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_EnableMuteMode) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnableMuteMode) refers to stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_EnableMuteMode) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_DisableMuteMode) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_DisableMuteMode) refers to stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_DisableMuteMode) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnterMuteMode) refers to stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_EnterMuteMode) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableTransmitter) refers to stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_EnableTransmitter) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableReceiver) refers to stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_EnableReceiver) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_SendBreak) refers to stm32h5xx_hal_uart.o(.text.HAL_LIN_SendBreak) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetState) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_GetState) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetError) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_GetError) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT) for UART_RxISR_16BIT + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_16BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) for HAL_UART_ErrorCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT) for UART_RxISR_8BIT + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_8BIT_FIFOEN) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_16BIT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_8BIT) refers to stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for HAL_UART_RxCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAReceiveCplt) refers to stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt) for [Anonymous Symbol] + stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt) refers to stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) for HAL_UARTEx_RxEventCallback + stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback) for HAL_UART_RxHalfCpltCallback + stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxHalfCplt) refers to stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init) refers to usart.o(.text.HAL_UART_MspInit) for HAL_UART_MspInit + stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) for UART_AdvFeatureConfig + stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_SetConfig) for UART_SetConfig + stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_RS485Ex_Init) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_WakeupCallback) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_RxFifoFullCallback) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_TxFifoEmptyCallback) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_MultiProcessorEx_AddressLength_Set) refers to stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) for UART_CheckIdleState + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_MultiProcessorEx_AddressLength_Set) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_MultiProcessorEx_AddressLength_Set) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_StopModeWakeUpSourceConfig) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_Wakeup_AddressConfig) for UARTEx_Wakeup_AddressConfig + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_StopModeWakeUpSourceConfig) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_StopModeWakeUpSourceConfig) refers to stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) for UART_WaitOnFlagUntilTimeout + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_StopModeWakeUpSourceConfig) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_StopModeWakeUpSourceConfig) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.UARTEx_Wakeup_AddressConfig) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_Wakeup_AddressConfig) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_EnableStopMode) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_EnableStopMode) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_DisableStopMode) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableStopMode) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_EnableFifoMode) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) for UARTEx_SetNbDataToProcess + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_EnableFifoMode) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_EnableFifoMode) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) refers to stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.numerator) for UARTEx_SetNbDataToProcess.numerator + stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) refers to stm32h5xx_hal_uart_ex.o(.rodata.UARTEx_SetNbDataToProcess.denominator) for UARTEx_SetNbDataToProcess.denominator + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.UARTEx_SetNbDataToProcess) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_DisableFifoMode) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) for UARTEx_SetNbDataToProcess + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_SetTxFifoThreshold) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold) refers to stm32h5xx_hal_uart_ex.o(.text.UARTEx_SetNbDataToProcess) for UARTEx_SetNbDataToProcess + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_SetRxFifoThreshold) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle) refers to stm32h5xx_hal.o(.text.HAL_GetTick) for HAL_GetTick + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_IT) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT) for UART_Start_Receive_IT + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_IT) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_IT) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA) refers to stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA) for UART_Start_Receive_DMA + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_DMA) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA) for [Anonymous Symbol] + stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_GetRxEventType) refers to stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_GetRxEventType) for [Anonymous Symbol] + system_stm32h5xx.o(.ARM.exidx.text.SystemInit) refers to system_stm32h5xx.o(.text.SystemInit) for [Anonymous Symbol] + system_stm32h5xx.o(.text.SystemCoreClockUpdate) refers to system_stm32h5xx.o(.data.SystemCoreClock) for SystemCoreClock + system_stm32h5xx.o(.text.SystemCoreClockUpdate) refers to system_stm32h5xx.o(.rodata.AHBPrescTable) for AHBPrescTable + system_stm32h5xx.o(.ARM.exidx.text.SystemCoreClockUpdate) refers to system_stm32h5xx.o(.text.SystemCoreClockUpdate) for [Anonymous Symbol] + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_thread_initialize.o(.text._tx_thread_initialize) for _tx_thread_initialize + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_timer_initialize.o(.text._tx_timer_initialize) for _tx_timer_initialize + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_ptr) for _tx_semaphore_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_count) for _tx_semaphore_created_count + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_queue_created_ptr) for _tx_queue_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_queue_created_count) for _tx_queue_created_count + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_ptr) for _tx_event_flags_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_count) for _tx_event_flags_created_count + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_ptr) for _tx_block_pool_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_count) for _tx_block_pool_created_count + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_ptr) for _tx_byte_pool_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_count) for _tx_byte_pool_created_count + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_ptr) for _tx_mutex_created_ptr + tx_initialize_high_level.o(.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_count) for _tx_mutex_created_count + tx_initialize_high_level.o(.ARM.exidx.text._tx_initialize_high_level) refers to tx_initialize_high_level.o(.text._tx_initialize_high_level) for [Anonymous Symbol] + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_initialize_low_level.o(.text) for _tx_initialize_low_level + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_initialize_high_level.o(.text._tx_initialize_high_level) for _tx_initialize_high_level + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_initialize_high_level.o(.bss._tx_initialize_unused_memory) for _tx_initialize_unused_memory + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to app_azure_rtos.o(.text.tx_application_define) for tx_application_define + tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) refers to tx_thread_schedule.o(.text) for _tx_thread_schedule + tx_initialize_kernel_enter.o(.ARM.exidx.text._tx_initialize_kernel_enter) refers to tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) for [Anonymous Symbol] + tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup) refers to tx_initialize_low_level.o(.text) for _tx_initialize_low_level + tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup) refers to tx_initialize_high_level.o(.text._tx_initialize_high_level) for _tx_initialize_high_level + tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_initialize_kernel_setup.o(.ARM.exidx.text._tx_initialize_kernel_setup) refers to tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup) for [Anonymous Symbol] + tx_thread_schedule.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_schedule.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_schedule.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_schedule.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_timer_interrupt.o(.text) refers to tx_timer_expiration_process.o(.text._tx_timer_expiration_process) for _tx_timer_expiration_process + tx_timer_interrupt.o(.text) refers to tx_thread_time_slice.o(.text._tx_thread_time_slice) for _tx_thread_time_slice + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_system_clock) for _tx_timer_system_clock + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_expired_time_slice) for _tx_timer_expired_time_slice + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_expired) for _tx_timer_expired + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_interrupt.o(.text) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_interrupt.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_timer_interrupt.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_timer_interrupt.o(.text) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_stack_error_handler.o(.text._tx_thread_stack_error_handler) refers to tx_thread_initialize.o(.bss._tx_thread_application_stack_error_handler) for _tx_thread_application_stack_error_handler + tx_thread_stack_error_handler.o(.ARM.exidx.text._tx_thread_stack_error_handler) refers to tx_thread_stack_error_handler.o(.text._tx_thread_stack_error_handler) for [Anonymous Symbol] + tx_thread_stack_error_notify.o(.text._tx_thread_stack_error_notify) refers to tx_thread_initialize.o(.bss._tx_thread_application_stack_error_handler) for _tx_thread_application_stack_error_handler + tx_thread_stack_error_notify.o(.ARM.exidx.text._tx_thread_stack_error_notify) refers to tx_thread_stack_error_notify.o(.text._tx_thread_stack_error_notify) for [Anonymous Symbol] + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate) for _tx_timer_system_deactivate + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_priority_maps) for _tx_thread_priority_maps + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_system_resume.o(.text._tx_thread_system_resume) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_system_resume.o(.ARM.exidx.text._tx_thread_system_resume) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for [Anonymous Symbol] + tx_block_allocate.o(.text._tx_block_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_block_allocate.o(.text._tx_block_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_block_allocate.o(.text._tx_block_allocate) refers to tx_block_pool_cleanup.o(.text._tx_block_pool_cleanup) for _tx_block_pool_cleanup + tx_block_allocate.o(.text._tx_block_allocate) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_block_allocate.o(.ARM.exidx.text._tx_block_allocate) refers to tx_block_allocate.o(.text._tx_block_allocate) for [Anonymous Symbol] + tx_block_pool_cleanup.o(.text._tx_block_pool_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_block_pool_cleanup.o(.text._tx_block_pool_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_block_pool_cleanup.o(.ARM.exidx.text._tx_block_pool_cleanup) refers to tx_block_pool_cleanup.o(.text._tx_block_pool_cleanup) for [Anonymous Symbol] + tx_block_pool_create.o(.text._tx_block_pool_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_block_pool_create.o(.text._tx_block_pool_create) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_count) for _tx_block_pool_created_count + tx_block_pool_create.o(.text._tx_block_pool_create) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_ptr) for _tx_block_pool_created_ptr + tx_block_pool_create.o(.ARM.exidx.text._tx_block_pool_create) refers to tx_block_pool_create.o(.text._tx_block_pool_create) for [Anonymous Symbol] + tx_block_pool_delete.o(.text._tx_block_pool_delete) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_count) for _tx_block_pool_created_count + tx_block_pool_delete.o(.text._tx_block_pool_delete) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_ptr) for _tx_block_pool_created_ptr + tx_block_pool_delete.o(.text._tx_block_pool_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_block_pool_delete.o(.text._tx_block_pool_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_block_pool_delete.o(.text._tx_block_pool_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_block_pool_delete.o(.ARM.exidx.text._tx_block_pool_delete) refers to tx_block_pool_delete.o(.text._tx_block_pool_delete) for [Anonymous Symbol] + tx_block_pool_info_get.o(.ARM.exidx.text._tx_block_pool_info_get) refers to tx_block_pool_info_get.o(.text._tx_block_pool_info_get) for [Anonymous Symbol] + tx_block_pool_prioritize.o(.text._tx_block_pool_prioritize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_block_pool_prioritize.o(.text._tx_block_pool_prioritize) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_block_pool_prioritize.o(.ARM.exidx.text._tx_block_pool_prioritize) refers to tx_block_pool_prioritize.o(.text._tx_block_pool_prioritize) for [Anonymous Symbol] + tx_block_release.o(.text._tx_block_release) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_block_release.o(.text._tx_block_release) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_block_release.o(.ARM.exidx.text._tx_block_release) refers to tx_block_release.o(.text._tx_block_release) for [Anonymous Symbol] + tx_byte_allocate.o(.text._tx_byte_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_byte_allocate.o(.text._tx_byte_allocate) refers to tx_byte_pool_search.o(.text._tx_byte_pool_search) for _tx_byte_pool_search + tx_byte_allocate.o(.text._tx_byte_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_byte_allocate.o(.text._tx_byte_allocate) refers to tx_byte_pool_cleanup.o(.text._tx_byte_pool_cleanup) for _tx_byte_pool_cleanup + tx_byte_allocate.o(.text._tx_byte_allocate) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_byte_allocate.o(.ARM.exidx.text._tx_byte_allocate) refers to tx_byte_allocate.o(.text._tx_byte_allocate) for [Anonymous Symbol] + tx_byte_pool_cleanup.o(.text._tx_byte_pool_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_byte_pool_cleanup.o(.text._tx_byte_pool_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_byte_pool_cleanup.o(.ARM.exidx.text._tx_byte_pool_cleanup) refers to tx_byte_pool_cleanup.o(.text._tx_byte_pool_cleanup) for [Anonymous Symbol] + tx_byte_pool_create.o(.text._tx_byte_pool_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_byte_pool_create.o(.text._tx_byte_pool_create) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_count) for _tx_byte_pool_created_count + tx_byte_pool_create.o(.text._tx_byte_pool_create) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_ptr) for _tx_byte_pool_created_ptr + tx_byte_pool_create.o(.ARM.exidx.text._tx_byte_pool_create) refers to tx_byte_pool_create.o(.text._tx_byte_pool_create) for [Anonymous Symbol] + tx_byte_pool_delete.o(.text._tx_byte_pool_delete) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_count) for _tx_byte_pool_created_count + tx_byte_pool_delete.o(.text._tx_byte_pool_delete) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_ptr) for _tx_byte_pool_created_ptr + tx_byte_pool_delete.o(.text._tx_byte_pool_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_byte_pool_delete.o(.text._tx_byte_pool_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_byte_pool_delete.o(.text._tx_byte_pool_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_byte_pool_delete.o(.ARM.exidx.text._tx_byte_pool_delete) refers to tx_byte_pool_delete.o(.text._tx_byte_pool_delete) for [Anonymous Symbol] + tx_byte_pool_info_get.o(.ARM.exidx.text._tx_byte_pool_info_get) refers to tx_byte_pool_info_get.o(.text._tx_byte_pool_info_get) for [Anonymous Symbol] + tx_byte_pool_prioritize.o(.text._tx_byte_pool_prioritize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_byte_pool_prioritize.o(.text._tx_byte_pool_prioritize) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_byte_pool_prioritize.o(.ARM.exidx.text._tx_byte_pool_prioritize) refers to tx_byte_pool_prioritize.o(.text._tx_byte_pool_prioritize) for [Anonymous Symbol] + tx_byte_pool_search.o(.text._tx_byte_pool_search) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_byte_pool_search.o(.ARM.exidx.text._tx_byte_pool_search) refers to tx_byte_pool_search.o(.text._tx_byte_pool_search) for [Anonymous Symbol] + tx_byte_release.o(.text._tx_byte_release) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_byte_release.o(.text._tx_byte_release) refers to tx_byte_pool_search.o(.text._tx_byte_pool_search) for _tx_byte_pool_search + tx_byte_release.o(.text._tx_byte_release) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_byte_release.o(.text._tx_byte_release) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_byte_release.o(.text._tx_byte_release) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_byte_release.o(.ARM.exidx.text._tx_byte_release) refers to tx_byte_release.o(.text._tx_byte_release) for [Anonymous Symbol] + tx_event_flags_cleanup.o(.text._tx_event_flags_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_event_flags_cleanup.o(.text._tx_event_flags_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_event_flags_cleanup.o(.ARM.exidx.text._tx_event_flags_cleanup) refers to tx_event_flags_cleanup.o(.text._tx_event_flags_cleanup) for [Anonymous Symbol] + tx_event_flags_create.o(.text._tx_event_flags_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_event_flags_create.o(.text._tx_event_flags_create) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_count) for _tx_event_flags_created_count + tx_event_flags_create.o(.text._tx_event_flags_create) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_ptr) for _tx_event_flags_created_ptr + tx_event_flags_create.o(.ARM.exidx.text._tx_event_flags_create) refers to tx_event_flags_create.o(.text._tx_event_flags_create) for [Anonymous Symbol] + tx_event_flags_delete.o(.text._tx_event_flags_delete) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_count) for _tx_event_flags_created_count + tx_event_flags_delete.o(.text._tx_event_flags_delete) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_ptr) for _tx_event_flags_created_ptr + tx_event_flags_delete.o(.text._tx_event_flags_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_event_flags_delete.o(.text._tx_event_flags_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_event_flags_delete.o(.text._tx_event_flags_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_event_flags_delete.o(.ARM.exidx.text._tx_event_flags_delete) refers to tx_event_flags_delete.o(.text._tx_event_flags_delete) for [Anonymous Symbol] + tx_event_flags_get.o(.text._tx_event_flags_get) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_event_flags_get.o(.text._tx_event_flags_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_event_flags_get.o(.text._tx_event_flags_get) refers to tx_event_flags_cleanup.o(.text._tx_event_flags_cleanup) for _tx_event_flags_cleanup + tx_event_flags_get.o(.text._tx_event_flags_get) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_event_flags_get.o(.ARM.exidx.text._tx_event_flags_get) refers to tx_event_flags_get.o(.text._tx_event_flags_get) for [Anonymous Symbol] + tx_event_flags_info_get.o(.ARM.exidx.text._tx_event_flags_info_get) refers to tx_event_flags_info_get.o(.text._tx_event_flags_info_get) for [Anonymous Symbol] + tx_event_flags_set.o(.text._tx_event_flags_set) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_event_flags_set.o(.text._tx_event_flags_set) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_event_flags_set.o(.text._tx_event_flags_set) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_event_flags_set.o(.ARM.exidx.text._tx_event_flags_set) refers to tx_event_flags_set.o(.text._tx_event_flags_set) for [Anonymous Symbol] + tx_event_flags_set_notify.o(.ARM.exidx.text._tx_event_flags_set_notify) refers to tx_event_flags_set_notify.o(.text._tx_event_flags_set_notify) for [Anonymous Symbol] + tx_mutex_cleanup.o(.text._tx_mutex_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_cleanup.o(.text._tx_mutex_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_mutex_cleanup.o(.ARM.exidx.text._tx_mutex_cleanup) refers to tx_mutex_cleanup.o(.text._tx_mutex_cleanup) for [Anonymous Symbol] + tx_mutex_cleanup.o(.text._tx_mutex_thread_release) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_cleanup.o(.text._tx_mutex_thread_release) refers to tx_mutex_put.o(.text._tx_mutex_put) for _tx_mutex_put + tx_mutex_cleanup.o(.ARM.exidx.text._tx_mutex_thread_release) refers to tx_mutex_cleanup.o(.text._tx_mutex_thread_release) for [Anonymous Symbol] + tx_mutex_create.o(.text._tx_mutex_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_mutex_create.o(.text._tx_mutex_create) refers to tx_thread_initialize.o(.bss._tx_thread_mutex_release) for _tx_thread_mutex_release + tx_mutex_create.o(.text._tx_mutex_create) refers to tx_mutex_cleanup.o(.text._tx_mutex_thread_release) for _tx_mutex_thread_release + tx_mutex_create.o(.text._tx_mutex_create) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_count) for _tx_mutex_created_count + tx_mutex_create.o(.text._tx_mutex_create) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_ptr) for _tx_mutex_created_ptr + tx_mutex_create.o(.ARM.exidx.text._tx_mutex_create) refers to tx_mutex_create.o(.text._tx_mutex_create) for [Anonymous Symbol] + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_count) for _tx_mutex_created_count + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_ptr) for _tx_mutex_created_ptr + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_mutex_put.o(.text._tx_mutex_put) for _tx_mutex_put + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_mutex_delete.o(.text._tx_mutex_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_mutex_delete.o(.ARM.exidx.text._tx_mutex_delete) refers to tx_mutex_delete.o(.text._tx_mutex_delete) for [Anonymous Symbol] + tx_mutex_get.o(.text._tx_mutex_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_mutex_get.o(.text._tx_mutex_get) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_get.o(.text._tx_mutex_get) refers to tx_mutex_cleanup.o(.text._tx_mutex_cleanup) for _tx_mutex_cleanup + tx_mutex_get.o(.text._tx_mutex_get) refers to tx_mutex_priority_change.o(.text._tx_mutex_priority_change) for _tx_mutex_priority_change + tx_mutex_get.o(.text._tx_mutex_get) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_mutex_get.o(.ARM.exidx.text._tx_mutex_get) refers to tx_mutex_get.o(.text._tx_mutex_get) for [Anonymous Symbol] + tx_mutex_info_get.o(.ARM.exidx.text._tx_mutex_info_get) refers to tx_mutex_info_get.o(.text._tx_mutex_info_get) for [Anonymous Symbol] + tx_mutex_prioritize.o(.text._tx_mutex_prioritize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_prioritize.o(.text._tx_mutex_prioritize) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_mutex_prioritize.o(.ARM.exidx.text._tx_mutex_prioritize) refers to tx_mutex_prioritize.o(.text._tx_mutex_prioritize) for [Anonymous Symbol] + tx_mutex_priority_change.o(.text._tx_mutex_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_mutex_priority_change.o(.text._tx_mutex_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_priority_change.o(.text._tx_mutex_priority_change) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_mutex_priority_change.o(.text._tx_mutex_priority_change) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_mutex_priority_change.o(.text._tx_mutex_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_mutex_priority_change.o(.ARM.exidx.text._tx_mutex_priority_change) refers to tx_mutex_priority_change.o(.text._tx_mutex_priority_change) for [Anonymous Symbol] + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_mutex_prioritize.o(.text._tx_mutex_prioritize) for _tx_mutex_prioritize + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_mutex_priority_change.o(.text._tx_mutex_priority_change) for _tx_mutex_priority_change + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_mutex_put.o(.text._tx_mutex_put) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_mutex_put.o(.ARM.exidx.text._tx_mutex_put) refers to tx_mutex_put.o(.text._tx_mutex_put) for [Anonymous Symbol] + tx_queue_cleanup.o(.text._tx_queue_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_cleanup.o(.text._tx_queue_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_cleanup.o(.ARM.exidx.text._tx_queue_cleanup) refers to tx_queue_cleanup.o(.text._tx_queue_cleanup) for [Anonymous Symbol] + tx_queue_create.o(.text._tx_queue_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_queue_create.o(.text._tx_queue_create) refers to tx_initialize_high_level.o(.bss._tx_queue_created_count) for _tx_queue_created_count + tx_queue_create.o(.text._tx_queue_create) refers to tx_initialize_high_level.o(.bss._tx_queue_created_ptr) for _tx_queue_created_ptr + tx_queue_create.o(.ARM.exidx.text._tx_queue_create) refers to tx_queue_create.o(.text._tx_queue_create) for [Anonymous Symbol] + tx_queue_delete.o(.text._tx_queue_delete) refers to tx_initialize_high_level.o(.bss._tx_queue_created_count) for _tx_queue_created_count + tx_queue_delete.o(.text._tx_queue_delete) refers to tx_initialize_high_level.o(.bss._tx_queue_created_ptr) for _tx_queue_created_ptr + tx_queue_delete.o(.text._tx_queue_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_delete.o(.text._tx_queue_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_delete.o(.text._tx_queue_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_queue_delete.o(.ARM.exidx.text._tx_queue_delete) refers to tx_queue_delete.o(.text._tx_queue_delete) for [Anonymous Symbol] + tx_queue_flush.o(.text._tx_queue_flush) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_flush.o(.text._tx_queue_flush) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_flush.o(.text._tx_queue_flush) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_queue_flush.o(.ARM.exidx.text._tx_queue_flush) refers to tx_queue_flush.o(.text._tx_queue_flush) for [Anonymous Symbol] + tx_queue_front_send.o(.text._tx_queue_front_send) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_front_send.o(.text._tx_queue_front_send) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_front_send.o(.text._tx_queue_front_send) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_queue_front_send.o(.text._tx_queue_front_send) refers to tx_queue_cleanup.o(.text._tx_queue_cleanup) for _tx_queue_cleanup + tx_queue_front_send.o(.text._tx_queue_front_send) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_queue_front_send.o(.ARM.exidx.text._tx_queue_front_send) refers to tx_queue_front_send.o(.text._tx_queue_front_send) for [Anonymous Symbol] + tx_queue_info_get.o(.ARM.exidx.text._tx_queue_info_get) refers to tx_queue_info_get.o(.text._tx_queue_info_get) for [Anonymous Symbol] + tx_queue_prioritize.o(.text._tx_queue_prioritize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_prioritize.o(.text._tx_queue_prioritize) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_queue_prioritize.o(.ARM.exidx.text._tx_queue_prioritize) refers to tx_queue_prioritize.o(.text._tx_queue_prioritize) for [Anonymous Symbol] + tx_queue_receive.o(.text._tx_queue_receive) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_receive.o(.text._tx_queue_receive) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_receive.o(.text._tx_queue_receive) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_queue_receive.o(.text._tx_queue_receive) refers to tx_queue_cleanup.o(.text._tx_queue_cleanup) for _tx_queue_cleanup + tx_queue_receive.o(.text._tx_queue_receive) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_queue_receive.o(.ARM.exidx.text._tx_queue_receive) refers to tx_queue_receive.o(.text._tx_queue_receive) for [Anonymous Symbol] + tx_queue_send.o(.text._tx_queue_send) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_queue_send.o(.text._tx_queue_send) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_queue_send.o(.text._tx_queue_send) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_queue_send.o(.text._tx_queue_send) refers to tx_queue_cleanup.o(.text._tx_queue_cleanup) for _tx_queue_cleanup + tx_queue_send.o(.text._tx_queue_send) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_queue_send.o(.ARM.exidx.text._tx_queue_send) refers to tx_queue_send.o(.text._tx_queue_send) for [Anonymous Symbol] + tx_queue_send_notify.o(.ARM.exidx.text._tx_queue_send_notify) refers to tx_queue_send_notify.o(.text._tx_queue_send_notify) for [Anonymous Symbol] + tx_semaphore_ceiling_put.o(.text._tx_semaphore_ceiling_put) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_ceiling_put.o(.text._tx_semaphore_ceiling_put) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_semaphore_ceiling_put.o(.ARM.exidx.text._tx_semaphore_ceiling_put) refers to tx_semaphore_ceiling_put.o(.text._tx_semaphore_ceiling_put) for [Anonymous Symbol] + tx_semaphore_cleanup.o(.text._tx_semaphore_cleanup) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_cleanup.o(.text._tx_semaphore_cleanup) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_semaphore_cleanup.o(.ARM.exidx.text._tx_semaphore_cleanup) refers to tx_semaphore_cleanup.o(.text._tx_semaphore_cleanup) for [Anonymous Symbol] + tx_semaphore_create.o(.text._tx_semaphore_create) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_count) for _tx_semaphore_created_count + tx_semaphore_create.o(.text._tx_semaphore_create) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_ptr) for _tx_semaphore_created_ptr + tx_semaphore_create.o(.ARM.exidx.text._tx_semaphore_create) refers to tx_semaphore_create.o(.text._tx_semaphore_create) for [Anonymous Symbol] + tx_semaphore_delete.o(.text._tx_semaphore_delete) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_count) for _tx_semaphore_created_count + tx_semaphore_delete.o(.text._tx_semaphore_delete) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_ptr) for _tx_semaphore_created_ptr + tx_semaphore_delete.o(.text._tx_semaphore_delete) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_delete.o(.text._tx_semaphore_delete) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_semaphore_delete.o(.text._tx_semaphore_delete) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_semaphore_delete.o(.ARM.exidx.text._tx_semaphore_delete) refers to tx_semaphore_delete.o(.text._tx_semaphore_delete) for [Anonymous Symbol] + tx_semaphore_get.o(.text._tx_semaphore_get) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_get.o(.text._tx_semaphore_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_semaphore_get.o(.text._tx_semaphore_get) refers to tx_semaphore_cleanup.o(.text._tx_semaphore_cleanup) for _tx_semaphore_cleanup + tx_semaphore_get.o(.text._tx_semaphore_get) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_semaphore_get.o(.ARM.exidx.text._tx_semaphore_get) refers to tx_semaphore_get.o(.text._tx_semaphore_get) for [Anonymous Symbol] + tx_semaphore_info_get.o(.ARM.exidx.text._tx_semaphore_info_get) refers to tx_semaphore_info_get.o(.text._tx_semaphore_info_get) for [Anonymous Symbol] + tx_semaphore_prioritize.o(.text._tx_semaphore_prioritize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_prioritize.o(.text._tx_semaphore_prioritize) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_semaphore_prioritize.o(.ARM.exidx.text._tx_semaphore_prioritize) refers to tx_semaphore_prioritize.o(.text._tx_semaphore_prioritize) for [Anonymous Symbol] + tx_semaphore_put.o(.text._tx_semaphore_put) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_semaphore_put.o(.text._tx_semaphore_put) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_semaphore_put.o(.ARM.exidx.text._tx_semaphore_put) refers to tx_semaphore_put.o(.text._tx_semaphore_put) for [Anonymous Symbol] + tx_semaphore_put_notify.o(.ARM.exidx.text._tx_semaphore_put_notify) refers to tx_semaphore_put_notify.o(.text._tx_semaphore_put_notify) for [Anonymous Symbol] + tx_thread_create.o(.text._tx_thread_create) refers to aeabi_memset.o(.text) for __aeabi_memset + tx_thread_create.o(.text._tx_thread_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_timeout.o(.text._tx_thread_timeout) for _tx_thread_timeout + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_shell_entry.o(.text._tx_thread_shell_entry) for _tx_thread_shell_entry + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_stack_build.o(.text) for _tx_thread_stack_build + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_created_count) for _tx_thread_created_count + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_created_ptr) for _tx_thread_created_ptr + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_thread_create.o(.text._tx_thread_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_thread_create.o(.ARM.exidx.text._tx_thread_create) refers to tx_thread_create.o(.text._tx_thread_create) for [Anonymous Symbol] + tx_thread_delete.o(.text._tx_thread_delete) refers to tx_thread_initialize.o(.bss._tx_thread_created_count) for _tx_thread_created_count + tx_thread_delete.o(.text._tx_thread_delete) refers to tx_thread_initialize.o(.bss._tx_thread_created_ptr) for _tx_thread_created_ptr + tx_thread_delete.o(.ARM.exidx.text._tx_thread_delete) refers to tx_thread_delete.o(.text._tx_thread_delete) for [Anonymous Symbol] + tx_thread_entry_exit_notify.o(.ARM.exidx.text._tx_thread_entry_exit_notify) refers to tx_thread_entry_exit_notify.o(.text._tx_thread_entry_exit_notify) for [Anonymous Symbol] + tx_thread_identify.o(.text._tx_thread_identify) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_identify.o(.ARM.exidx.text._tx_thread_identify) refers to tx_thread_identify.o(.text._tx_thread_identify) for [Anonymous Symbol] + tx_thread_info_get.o(.ARM.exidx.text._tx_thread_info_get) refers to tx_thread_info_get.o(.text._tx_thread_info_get) for [Anonymous Symbol] + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_priority_maps) for _tx_thread_priority_maps + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_initialize.o(.text._tx_thread_initialize) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_created_ptr) for _tx_thread_created_ptr + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_created_count) for _tx_thread_created_count + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_thread_mutex_release) for _tx_thread_mutex_release + tx_thread_initialize.o(.text._tx_thread_initialize) refers to tx_thread_initialize.o(.bss._tx_build_options) for _tx_build_options + tx_thread_initialize.o(.ARM.exidx.text._tx_thread_initialize) refers to tx_thread_initialize.o(.text._tx_thread_initialize) for [Anonymous Symbol] + tx_thread_preemption_change.o(.text._tx_thread_preemption_change) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_preemption_change.o(.text._tx_thread_preemption_change) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_preemption_change.o(.text._tx_thread_preemption_change) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_preemption_change.o(.text._tx_thread_preemption_change) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_thread_preemption_change.o(.ARM.exidx.text._tx_thread_preemption_change) refers to tx_thread_preemption_change.o(.text._tx_thread_preemption_change) for [Anonymous Symbol] + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_priority_change.o(.text._tx_thread_priority_change) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_thread_priority_change.o(.ARM.exidx.text._tx_thread_priority_change) refers to tx_thread_priority_change.o(.text._tx_thread_priority_change) for [Anonymous Symbol] + tx_thread_relinquish.o(.text._tx_thread_relinquish) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_relinquish.o(.text._tx_thread_relinquish) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_thread_relinquish.o(.text._tx_thread_relinquish) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_relinquish.o(.text._tx_thread_relinquish) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_relinquish.o(.text._tx_thread_relinquish) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_relinquish.o(.ARM.exidx.text._tx_thread_relinquish) refers to tx_thread_relinquish.o(.text._tx_thread_relinquish) for [Anonymous Symbol] + tx_thread_reset.o(.text._tx_thread_reset) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_reset.o(.text._tx_thread_reset) refers to aeabi_memset.o(.text) for __aeabi_memset + tx_thread_reset.o(.text._tx_thread_reset) refers to tx_thread_shell_entry.o(.text._tx_thread_shell_entry) for _tx_thread_shell_entry + tx_thread_reset.o(.text._tx_thread_reset) refers to tx_thread_stack_build.o(.text) for _tx_thread_stack_build + tx_thread_reset.o(.ARM.exidx.text._tx_thread_reset) refers to tx_thread_reset.o(.text._tx_thread_reset) for [Anonymous Symbol] + tx_thread_resume.o(.text._tx_thread_resume) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_thread_resume.o(.text._tx_thread_resume) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_resume.o(.text._tx_thread_resume) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_resume.o(.text._tx_thread_resume) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_thread_resume.o(.ARM.exidx.text._tx_thread_resume) refers to tx_thread_resume.o(.text._tx_thread_resume) for [Anonymous Symbol] + tx_thread_shell_entry.o(.text._tx_thread_shell_entry) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_shell_entry.o(.text._tx_thread_shell_entry) refers to tx_thread_initialize.o(.bss._tx_thread_mutex_release) for _tx_thread_mutex_release + tx_thread_shell_entry.o(.text._tx_thread_shell_entry) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_shell_entry.o(.text._tx_thread_shell_entry) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_thread_shell_entry.o(.ARM.exidx.text._tx_thread_shell_entry) refers to tx_thread_shell_entry.o(.text._tx_thread_shell_entry) for [Anonymous Symbol] + tx_thread_sleep.o(.text._tx_thread_sleep) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_sleep.o(.text._tx_thread_sleep) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_thread_sleep.o(.text._tx_thread_sleep) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + tx_thread_sleep.o(.text._tx_thread_sleep) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_sleep.o(.text._tx_thread_sleep) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_thread_sleep.o(.ARM.exidx.text._tx_thread_sleep) refers to tx_thread_sleep.o(.text._tx_thread_sleep) for [Anonymous Symbol] + tx_thread_stack_analyze.o(.ARM.exidx.text._tx_thread_stack_analyze) refers to tx_thread_stack_analyze.o(.text._tx_thread_stack_analyze) for [Anonymous Symbol] + tx_thread_suspend.o(.text._tx_thread_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_suspend.o(.text._tx_thread_suspend) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_thread_suspend.o(.text._tx_thread_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_suspend.o(.text._tx_thread_suspend) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_thread_suspend.o(.ARM.exidx.text._tx_thread_suspend) refers to tx_thread_suspend.o(.text._tx_thread_suspend) for [Anonymous Symbol] + tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_system_preempt_check.o(.ARM.exidx.text._tx_thread_system_preempt_check) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for [Anonymous Symbol] + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_timer_system_activate.o(.text._tx_timer_system_activate) for _tx_timer_system_activate + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_priority_maps) for _tx_thread_priority_maps + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_system_suspend.o(.text._tx_thread_system_suspend) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_system_suspend.o(.ARM.exidx.text._tx_thread_system_suspend) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for [Anonymous Symbol] + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate) for _tx_timer_system_deactivate + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_initialize.o(.bss._tx_thread_mutex_release) for _tx_thread_mutex_release + tx_thread_terminate.o(.text._tx_thread_terminate) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + tx_thread_terminate.o(.ARM.exidx.text._tx_thread_terminate) refers to tx_thread_terminate.o(.text._tx_thread_terminate) for [Anonymous Symbol] + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_timer_initialize.o(.bss._tx_timer_expired_time_slice) for _tx_timer_expired_time_slice + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_thread_initialize.o(.bss._tx_thread_priority_list) for _tx_thread_priority_list + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_thread_initialize.o(.bss._tx_thread_highest_priority) for _tx_thread_highest_priority + tx_thread_time_slice.o(.text._tx_thread_time_slice) refers to tx_thread_initialize.o(.bss._tx_thread_execute_ptr) for _tx_thread_execute_ptr + tx_thread_time_slice.o(.ARM.exidx.text._tx_thread_time_slice) refers to tx_thread_time_slice.o(.text._tx_thread_time_slice) for [Anonymous Symbol] + tx_thread_time_slice_change.o(.text._tx_thread_time_slice_change) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + tx_thread_time_slice_change.o(.text._tx_thread_time_slice_change) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_thread_time_slice_change.o(.ARM.exidx.text._tx_thread_time_slice_change) refers to tx_thread_time_slice_change.o(.text._tx_thread_time_slice_change) for [Anonymous Symbol] + tx_thread_timeout.o(.text._tx_thread_timeout) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_timeout.o(.text._tx_thread_timeout) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_thread_timeout.o(.ARM.exidx.text._tx_thread_timeout) refers to tx_thread_timeout.o(.text._tx_thread_timeout) for [Anonymous Symbol] + tx_thread_wait_abort.o(.text._tx_thread_wait_abort) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_thread_wait_abort.o(.text._tx_thread_wait_abort) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_thread_wait_abort.o(.ARM.exidx.text._tx_thread_wait_abort) refers to tx_thread_wait_abort.o(.text._tx_thread_wait_abort) for [Anonymous Symbol] + tx_time_get.o(.text._tx_time_get) refers to tx_timer_initialize.o(.bss._tx_timer_system_clock) for _tx_timer_system_clock + tx_time_get.o(.ARM.exidx.text._tx_time_get) refers to tx_time_get.o(.text._tx_time_get) for [Anonymous Symbol] + tx_time_set.o(.text._tx_time_set) refers to tx_timer_initialize.o(.bss._tx_timer_system_clock) for _tx_timer_system_clock + tx_time_set.o(.ARM.exidx.text._tx_time_set) refers to tx_time_set.o(.text._tx_time_set) for [Anonymous Symbol] + txe_block_allocate.o(.text._txe_block_allocate) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_block_allocate.o(.text._txe_block_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_block_allocate.o(.text._txe_block_allocate) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_block_allocate.o(.text._txe_block_allocate) refers to tx_block_allocate.o(.text._tx_block_allocate) for _tx_block_allocate + txe_block_allocate.o(.ARM.exidx.text._txe_block_allocate) refers to txe_block_allocate.o(.text._txe_block_allocate) for [Anonymous Symbol] + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_ptr) for _tx_block_pool_created_ptr + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_initialize_high_level.o(.bss._tx_block_pool_created_count) for _tx_block_pool_created_count + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_block_pool_create.o(.text._txe_block_pool_create) refers to tx_block_pool_create.o(.text._tx_block_pool_create) for _tx_block_pool_create + txe_block_pool_create.o(.ARM.exidx.text._txe_block_pool_create) refers to txe_block_pool_create.o(.text._txe_block_pool_create) for [Anonymous Symbol] + txe_block_pool_delete.o(.text._txe_block_pool_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_block_pool_delete.o(.text._txe_block_pool_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_block_pool_delete.o(.text._txe_block_pool_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_block_pool_delete.o(.text._txe_block_pool_delete) refers to tx_block_pool_delete.o(.text._tx_block_pool_delete) for _tx_block_pool_delete + txe_block_pool_delete.o(.ARM.exidx.text._txe_block_pool_delete) refers to txe_block_pool_delete.o(.text._txe_block_pool_delete) for [Anonymous Symbol] + txe_block_pool_info_get.o(.text._txe_block_pool_info_get) refers to tx_block_pool_info_get.o(.text._tx_block_pool_info_get) for _tx_block_pool_info_get + txe_block_pool_info_get.o(.ARM.exidx.text._txe_block_pool_info_get) refers to txe_block_pool_info_get.o(.text._txe_block_pool_info_get) for [Anonymous Symbol] + txe_block_pool_prioritize.o(.text._txe_block_pool_prioritize) refers to tx_block_pool_prioritize.o(.text._tx_block_pool_prioritize) for _tx_block_pool_prioritize + txe_block_pool_prioritize.o(.ARM.exidx.text._txe_block_pool_prioritize) refers to txe_block_pool_prioritize.o(.text._txe_block_pool_prioritize) for [Anonymous Symbol] + txe_block_release.o(.text._txe_block_release) refers to tx_block_release.o(.text._tx_block_release) for _tx_block_release + txe_block_release.o(.ARM.exidx.text._txe_block_release) refers to txe_block_release.o(.text._txe_block_release) for [Anonymous Symbol] + txe_byte_allocate.o(.text._txe_byte_allocate) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_byte_allocate.o(.text._txe_byte_allocate) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_byte_allocate.o(.text._txe_byte_allocate) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_byte_allocate.o(.text._txe_byte_allocate) refers to tx_byte_allocate.o(.text._tx_byte_allocate) for _tx_byte_allocate + txe_byte_allocate.o(.ARM.exidx.text._txe_byte_allocate) refers to txe_byte_allocate.o(.text._txe_byte_allocate) for [Anonymous Symbol] + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_ptr) for _tx_byte_pool_created_ptr + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_initialize_high_level.o(.bss._tx_byte_pool_created_count) for _tx_byte_pool_created_count + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_byte_pool_create.o(.text._txe_byte_pool_create) refers to tx_byte_pool_create.o(.text._tx_byte_pool_create) for _tx_byte_pool_create + txe_byte_pool_create.o(.ARM.exidx.text._txe_byte_pool_create) refers to txe_byte_pool_create.o(.text._txe_byte_pool_create) for [Anonymous Symbol] + txe_byte_pool_delete.o(.text._txe_byte_pool_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_byte_pool_delete.o(.text._txe_byte_pool_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_byte_pool_delete.o(.text._txe_byte_pool_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_byte_pool_delete.o(.text._txe_byte_pool_delete) refers to tx_byte_pool_delete.o(.text._tx_byte_pool_delete) for _tx_byte_pool_delete + txe_byte_pool_delete.o(.ARM.exidx.text._txe_byte_pool_delete) refers to txe_byte_pool_delete.o(.text._txe_byte_pool_delete) for [Anonymous Symbol] + txe_byte_pool_info_get.o(.text._txe_byte_pool_info_get) refers to tx_byte_pool_info_get.o(.text._tx_byte_pool_info_get) for _tx_byte_pool_info_get + txe_byte_pool_info_get.o(.ARM.exidx.text._txe_byte_pool_info_get) refers to txe_byte_pool_info_get.o(.text._txe_byte_pool_info_get) for [Anonymous Symbol] + txe_byte_pool_prioritize.o(.text._txe_byte_pool_prioritize) refers to tx_byte_pool_prioritize.o(.text._tx_byte_pool_prioritize) for _tx_byte_pool_prioritize + txe_byte_pool_prioritize.o(.ARM.exidx.text._txe_byte_pool_prioritize) refers to txe_byte_pool_prioritize.o(.text._txe_byte_pool_prioritize) for [Anonymous Symbol] + txe_byte_release.o(.text._txe_byte_release) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_byte_release.o(.text._txe_byte_release) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_byte_release.o(.text._txe_byte_release) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_byte_release.o(.text._txe_byte_release) refers to tx_byte_release.o(.text._tx_byte_release) for _tx_byte_release + txe_byte_release.o(.ARM.exidx.text._txe_byte_release) refers to txe_byte_release.o(.text._txe_byte_release) for [Anonymous Symbol] + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_ptr) for _tx_event_flags_created_ptr + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_initialize_high_level.o(.bss._tx_event_flags_created_count) for _tx_event_flags_created_count + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_event_flags_create.o(.text._txe_event_flags_create) refers to tx_event_flags_create.o(.text._tx_event_flags_create) for _tx_event_flags_create + txe_event_flags_create.o(.ARM.exidx.text._txe_event_flags_create) refers to txe_event_flags_create.o(.text._txe_event_flags_create) for [Anonymous Symbol] + txe_event_flags_delete.o(.text._txe_event_flags_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_event_flags_delete.o(.text._txe_event_flags_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_event_flags_delete.o(.text._txe_event_flags_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_event_flags_delete.o(.text._txe_event_flags_delete) refers to tx_event_flags_delete.o(.text._tx_event_flags_delete) for _tx_event_flags_delete + txe_event_flags_delete.o(.ARM.exidx.text._txe_event_flags_delete) refers to txe_event_flags_delete.o(.text._txe_event_flags_delete) for [Anonymous Symbol] + txe_event_flags_get.o(.text._txe_event_flags_get) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_event_flags_get.o(.text._txe_event_flags_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_event_flags_get.o(.text._txe_event_flags_get) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_event_flags_get.o(.text._txe_event_flags_get) refers to tx_event_flags_get.o(.text._tx_event_flags_get) for _tx_event_flags_get + txe_event_flags_get.o(.ARM.exidx.text._txe_event_flags_get) refers to txe_event_flags_get.o(.text._txe_event_flags_get) for [Anonymous Symbol] + txe_event_flags_info_get.o(.text._txe_event_flags_info_get) refers to tx_event_flags_info_get.o(.text._tx_event_flags_info_get) for _tx_event_flags_info_get + txe_event_flags_info_get.o(.ARM.exidx.text._txe_event_flags_info_get) refers to txe_event_flags_info_get.o(.text._txe_event_flags_info_get) for [Anonymous Symbol] + txe_event_flags_set.o(.text._txe_event_flags_set) refers to tx_event_flags_set.o(.text._tx_event_flags_set) for _tx_event_flags_set + txe_event_flags_set.o(.ARM.exidx.text._txe_event_flags_set) refers to txe_event_flags_set.o(.text._txe_event_flags_set) for [Anonymous Symbol] + txe_event_flags_set_notify.o(.text._txe_event_flags_set_notify) refers to tx_event_flags_set_notify.o(.text._tx_event_flags_set_notify) for _tx_event_flags_set_notify + txe_event_flags_set_notify.o(.ARM.exidx.text._txe_event_flags_set_notify) refers to txe_event_flags_set_notify.o(.text._txe_event_flags_set_notify) for [Anonymous Symbol] + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_ptr) for _tx_mutex_created_ptr + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_initialize_high_level.o(.bss._tx_mutex_created_count) for _tx_mutex_created_count + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_mutex_create.o(.text._txe_mutex_create) refers to tx_mutex_create.o(.text._tx_mutex_create) for _tx_mutex_create + txe_mutex_create.o(.ARM.exidx.text._txe_mutex_create) refers to txe_mutex_create.o(.text._txe_mutex_create) for [Anonymous Symbol] + txe_mutex_delete.o(.text._txe_mutex_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_mutex_delete.o(.text._txe_mutex_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_mutex_delete.o(.text._txe_mutex_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_mutex_delete.o(.text._txe_mutex_delete) refers to tx_mutex_delete.o(.text._tx_mutex_delete) for _tx_mutex_delete + txe_mutex_delete.o(.ARM.exidx.text._txe_mutex_delete) refers to txe_mutex_delete.o(.text._txe_mutex_delete) for [Anonymous Symbol] + txe_mutex_get.o(.text._txe_mutex_get) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_mutex_get.o(.text._txe_mutex_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_mutex_get.o(.text._txe_mutex_get) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_mutex_get.o(.text._txe_mutex_get) refers to tx_mutex_get.o(.text._tx_mutex_get) for _tx_mutex_get + txe_mutex_get.o(.ARM.exidx.text._txe_mutex_get) refers to txe_mutex_get.o(.text._txe_mutex_get) for [Anonymous Symbol] + txe_mutex_info_get.o(.text._txe_mutex_info_get) refers to tx_mutex_info_get.o(.text._tx_mutex_info_get) for _tx_mutex_info_get + txe_mutex_info_get.o(.ARM.exidx.text._txe_mutex_info_get) refers to txe_mutex_info_get.o(.text._txe_mutex_info_get) for [Anonymous Symbol] + txe_mutex_prioritize.o(.text._txe_mutex_prioritize) refers to tx_mutex_prioritize.o(.text._tx_mutex_prioritize) for _tx_mutex_prioritize + txe_mutex_prioritize.o(.ARM.exidx.text._txe_mutex_prioritize) refers to txe_mutex_prioritize.o(.text._txe_mutex_prioritize) for [Anonymous Symbol] + txe_mutex_put.o(.text._txe_mutex_put) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_mutex_put.o(.text._txe_mutex_put) refers to tx_mutex_put.o(.text._tx_mutex_put) for _tx_mutex_put + txe_mutex_put.o(.ARM.exidx.text._txe_mutex_put) refers to txe_mutex_put.o(.text._txe_mutex_put) for [Anonymous Symbol] + txe_queue_create.o(.text._txe_queue_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_queue_create.o(.text._txe_queue_create) refers to tx_initialize_high_level.o(.bss._tx_queue_created_ptr) for _tx_queue_created_ptr + txe_queue_create.o(.text._txe_queue_create) refers to tx_initialize_high_level.o(.bss._tx_queue_created_count) for _tx_queue_created_count + txe_queue_create.o(.text._txe_queue_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_queue_create.o(.text._txe_queue_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_queue_create.o(.text._txe_queue_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_queue_create.o(.text._txe_queue_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_queue_create.o(.text._txe_queue_create) refers to tx_queue_create.o(.text._tx_queue_create) for _tx_queue_create + txe_queue_create.o(.ARM.exidx.text._txe_queue_create) refers to txe_queue_create.o(.text._txe_queue_create) for [Anonymous Symbol] + txe_queue_delete.o(.text._txe_queue_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_queue_delete.o(.text._txe_queue_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_queue_delete.o(.text._txe_queue_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_queue_delete.o(.text._txe_queue_delete) refers to tx_queue_delete.o(.text._tx_queue_delete) for _tx_queue_delete + txe_queue_delete.o(.ARM.exidx.text._txe_queue_delete) refers to txe_queue_delete.o(.text._txe_queue_delete) for [Anonymous Symbol] + txe_queue_flush.o(.text._txe_queue_flush) refers to tx_queue_flush.o(.text._tx_queue_flush) for _tx_queue_flush + txe_queue_flush.o(.ARM.exidx.text._txe_queue_flush) refers to txe_queue_flush.o(.text._txe_queue_flush) for [Anonymous Symbol] + txe_queue_front_send.o(.text._txe_queue_front_send) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_queue_front_send.o(.text._txe_queue_front_send) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_queue_front_send.o(.text._txe_queue_front_send) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_queue_front_send.o(.text._txe_queue_front_send) refers to tx_queue_front_send.o(.text._tx_queue_front_send) for _tx_queue_front_send + txe_queue_front_send.o(.ARM.exidx.text._txe_queue_front_send) refers to txe_queue_front_send.o(.text._txe_queue_front_send) for [Anonymous Symbol] + txe_queue_info_get.o(.text._txe_queue_info_get) refers to tx_queue_info_get.o(.text._tx_queue_info_get) for _tx_queue_info_get + txe_queue_info_get.o(.ARM.exidx.text._txe_queue_info_get) refers to txe_queue_info_get.o(.text._txe_queue_info_get) for [Anonymous Symbol] + txe_queue_prioritize.o(.text._txe_queue_prioritize) refers to tx_queue_prioritize.o(.text._tx_queue_prioritize) for _tx_queue_prioritize + txe_queue_prioritize.o(.ARM.exidx.text._txe_queue_prioritize) refers to txe_queue_prioritize.o(.text._txe_queue_prioritize) for [Anonymous Symbol] + txe_queue_receive.o(.text._txe_queue_receive) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_queue_receive.o(.text._txe_queue_receive) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_queue_receive.o(.text._txe_queue_receive) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_queue_receive.o(.text._txe_queue_receive) refers to tx_queue_receive.o(.text._tx_queue_receive) for _tx_queue_receive + txe_queue_receive.o(.ARM.exidx.text._txe_queue_receive) refers to txe_queue_receive.o(.text._txe_queue_receive) for [Anonymous Symbol] + txe_queue_send.o(.text._txe_queue_send) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_queue_send.o(.text._txe_queue_send) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_queue_send.o(.text._txe_queue_send) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_queue_send.o(.text._txe_queue_send) refers to tx_queue_send.o(.text._tx_queue_send) for _tx_queue_send + txe_queue_send.o(.ARM.exidx.text._txe_queue_send) refers to txe_queue_send.o(.text._txe_queue_send) for [Anonymous Symbol] + txe_queue_send_notify.o(.text._txe_queue_send_notify) refers to tx_queue_send_notify.o(.text._tx_queue_send_notify) for _tx_queue_send_notify + txe_queue_send_notify.o(.ARM.exidx.text._txe_queue_send_notify) refers to txe_queue_send_notify.o(.text._txe_queue_send_notify) for [Anonymous Symbol] + txe_semaphore_ceiling_put.o(.text._txe_semaphore_ceiling_put) refers to tx_semaphore_ceiling_put.o(.text._tx_semaphore_ceiling_put) for _tx_semaphore_ceiling_put + txe_semaphore_ceiling_put.o(.ARM.exidx.text._txe_semaphore_ceiling_put) refers to txe_semaphore_ceiling_put.o(.text._txe_semaphore_ceiling_put) for [Anonymous Symbol] + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_ptr) for _tx_semaphore_created_ptr + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_initialize_high_level.o(.bss._tx_semaphore_created_count) for _tx_semaphore_created_count + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_semaphore_create.o(.text._txe_semaphore_create) refers to tx_semaphore_create.o(.text._tx_semaphore_create) for _tx_semaphore_create + txe_semaphore_create.o(.ARM.exidx.text._txe_semaphore_create) refers to txe_semaphore_create.o(.text._txe_semaphore_create) for [Anonymous Symbol] + txe_semaphore_delete.o(.text._txe_semaphore_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_semaphore_delete.o(.text._txe_semaphore_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_semaphore_delete.o(.text._txe_semaphore_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_semaphore_delete.o(.text._txe_semaphore_delete) refers to tx_semaphore_delete.o(.text._tx_semaphore_delete) for _tx_semaphore_delete + txe_semaphore_delete.o(.ARM.exidx.text._txe_semaphore_delete) refers to txe_semaphore_delete.o(.text._txe_semaphore_delete) for [Anonymous Symbol] + txe_semaphore_get.o(.text._txe_semaphore_get) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_semaphore_get.o(.text._txe_semaphore_get) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_semaphore_get.o(.text._txe_semaphore_get) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_semaphore_get.o(.text._txe_semaphore_get) refers to tx_semaphore_get.o(.text._tx_semaphore_get) for _tx_semaphore_get + txe_semaphore_get.o(.ARM.exidx.text._txe_semaphore_get) refers to txe_semaphore_get.o(.text._txe_semaphore_get) for [Anonymous Symbol] + txe_semaphore_info_get.o(.text._txe_semaphore_info_get) refers to tx_semaphore_info_get.o(.text._tx_semaphore_info_get) for _tx_semaphore_info_get + txe_semaphore_info_get.o(.ARM.exidx.text._txe_semaphore_info_get) refers to txe_semaphore_info_get.o(.text._txe_semaphore_info_get) for [Anonymous Symbol] + txe_semaphore_prioritize.o(.text._txe_semaphore_prioritize) refers to tx_semaphore_prioritize.o(.text._tx_semaphore_prioritize) for _tx_semaphore_prioritize + txe_semaphore_prioritize.o(.ARM.exidx.text._txe_semaphore_prioritize) refers to txe_semaphore_prioritize.o(.text._txe_semaphore_prioritize) for [Anonymous Symbol] + txe_semaphore_put.o(.text._txe_semaphore_put) refers to tx_semaphore_put.o(.text._tx_semaphore_put) for _tx_semaphore_put + txe_semaphore_put.o(.ARM.exidx.text._txe_semaphore_put) refers to txe_semaphore_put.o(.text._txe_semaphore_put) for [Anonymous Symbol] + txe_semaphore_put_notify.o(.text._txe_semaphore_put_notify) refers to tx_semaphore_put_notify.o(.text._tx_semaphore_put_notify) for _tx_semaphore_put_notify + txe_semaphore_put_notify.o(.ARM.exidx.text._txe_semaphore_put_notify) refers to txe_semaphore_put_notify.o(.text._txe_semaphore_put_notify) for [Anonymous Symbol] + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_created_ptr) for _tx_thread_created_ptr + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_created_count) for _tx_thread_created_count + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_thread_create.o(.text._txe_thread_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_create.o(.text._txe_thread_create) refers to tx_thread_create.o(.text._tx_thread_create) for _tx_thread_create + txe_thread_create.o(.ARM.exidx.text._txe_thread_create) refers to txe_thread_create.o(.text._txe_thread_create) for [Anonymous Symbol] + txe_thread_delete.o(.text._txe_thread_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_delete.o(.text._txe_thread_delete) refers to tx_thread_delete.o(.text._tx_thread_delete) for _tx_thread_delete + txe_thread_delete.o(.ARM.exidx.text._txe_thread_delete) refers to txe_thread_delete.o(.text._txe_thread_delete) for [Anonymous Symbol] + txe_thread_entry_exit_notify.o(.text._txe_thread_entry_exit_notify) refers to tx_thread_entry_exit_notify.o(.text._tx_thread_entry_exit_notify) for _tx_thread_entry_exit_notify + txe_thread_entry_exit_notify.o(.ARM.exidx.text._txe_thread_entry_exit_notify) refers to txe_thread_entry_exit_notify.o(.text._txe_thread_entry_exit_notify) for [Anonymous Symbol] + txe_thread_info_get.o(.text._txe_thread_info_get) refers to tx_thread_info_get.o(.text._tx_thread_info_get) for _tx_thread_info_get + txe_thread_info_get.o(.ARM.exidx.text._txe_thread_info_get) refers to txe_thread_info_get.o(.text._txe_thread_info_get) for [Anonymous Symbol] + txe_thread_preemption_change.o(.text._txe_thread_preemption_change) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_preemption_change.o(.text._txe_thread_preemption_change) refers to tx_thread_preemption_change.o(.text._tx_thread_preemption_change) for _tx_thread_preemption_change + txe_thread_preemption_change.o(.ARM.exidx.text._txe_thread_preemption_change) refers to txe_thread_preemption_change.o(.text._txe_thread_preemption_change) for [Anonymous Symbol] + txe_thread_priority_change.o(.text._txe_thread_priority_change) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_priority_change.o(.text._txe_thread_priority_change) refers to tx_thread_priority_change.o(.text._tx_thread_priority_change) for _tx_thread_priority_change + txe_thread_priority_change.o(.ARM.exidx.text._txe_thread_priority_change) refers to txe_thread_priority_change.o(.text._txe_thread_priority_change) for [Anonymous Symbol] + txe_thread_relinquish.o(.text._txe_thread_relinquish) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_thread_relinquish.o(.text._txe_thread_relinquish) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_relinquish.o(.text._txe_thread_relinquish) refers to tx_thread_relinquish.o(.text._tx_thread_relinquish) for _tx_thread_relinquish + txe_thread_relinquish.o(.ARM.exidx.text._txe_thread_relinquish) refers to txe_thread_relinquish.o(.text._txe_thread_relinquish) for [Anonymous Symbol] + txe_thread_reset.o(.text._txe_thread_reset) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_thread_reset.o(.text._txe_thread_reset) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_thread_reset.o(.text._txe_thread_reset) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_reset.o(.text._txe_thread_reset) refers to tx_thread_reset.o(.text._tx_thread_reset) for _tx_thread_reset + txe_thread_reset.o(.ARM.exidx.text._txe_thread_reset) refers to txe_thread_reset.o(.text._txe_thread_reset) for [Anonymous Symbol] + txe_thread_resume.o(.text._txe_thread_resume) refers to tx_thread_resume.o(.text._tx_thread_resume) for _tx_thread_resume + txe_thread_resume.o(.ARM.exidx.text._txe_thread_resume) refers to txe_thread_resume.o(.text._txe_thread_resume) for [Anonymous Symbol] + txe_thread_suspend.o(.text._txe_thread_suspend) refers to tx_thread_suspend.o(.text._tx_thread_suspend) for _tx_thread_suspend + txe_thread_suspend.o(.ARM.exidx.text._txe_thread_suspend) refers to txe_thread_suspend.o(.text._txe_thread_suspend) for [Anonymous Symbol] + txe_thread_terminate.o(.text._txe_thread_terminate) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_terminate.o(.text._txe_thread_terminate) refers to tx_thread_terminate.o(.text._tx_thread_terminate) for _tx_thread_terminate + txe_thread_terminate.o(.ARM.exidx.text._txe_thread_terminate) refers to txe_thread_terminate.o(.text._txe_thread_terminate) for [Anonymous Symbol] + txe_thread_time_slice_change.o(.text._txe_thread_time_slice_change) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_thread_time_slice_change.o(.text._txe_thread_time_slice_change) refers to tx_thread_time_slice_change.o(.text._tx_thread_time_slice_change) for _tx_thread_time_slice_change + txe_thread_time_slice_change.o(.ARM.exidx.text._txe_thread_time_slice_change) refers to txe_thread_time_slice_change.o(.text._txe_thread_time_slice_change) for [Anonymous Symbol] + txe_thread_wait_abort.o(.text._txe_thread_wait_abort) refers to tx_thread_wait_abort.o(.text._tx_thread_wait_abort) for _tx_thread_wait_abort + txe_thread_wait_abort.o(.ARM.exidx.text._txe_thread_wait_abort) refers to txe_thread_wait_abort.o(.text._txe_thread_wait_abort) for [Anonymous Symbol] + tx_timer_activate.o(.text._tx_timer_activate) refers to tx_timer_system_activate.o(.text._tx_timer_system_activate) for _tx_timer_system_activate + tx_timer_activate.o(.ARM.exidx.text._tx_timer_activate) refers to tx_timer_activate.o(.text._tx_timer_activate) for [Anonymous Symbol] + tx_timer_change.o(.ARM.exidx.text._tx_timer_change) refers to tx_timer_change.o(.text._tx_timer_change) for [Anonymous Symbol] + tx_timer_create.o(.text._tx_timer_create) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_timer_create.o(.text._tx_timer_create) refers to tx_timer_initialize.o(.bss._tx_timer_created_count) for _tx_timer_created_count + tx_timer_create.o(.text._tx_timer_create) refers to tx_timer_initialize.o(.bss._tx_timer_created_ptr) for _tx_timer_created_ptr + tx_timer_create.o(.text._tx_timer_create) refers to tx_timer_system_activate.o(.text._tx_timer_system_activate) for _tx_timer_system_activate + tx_timer_create.o(.ARM.exidx.text._tx_timer_create) refers to tx_timer_create.o(.text._tx_timer_create) for [Anonymous Symbol] + tx_timer_deactivate.o(.text._tx_timer_deactivate) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_deactivate.o(.text._tx_timer_deactivate) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_deactivate.o(.text._tx_timer_deactivate) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_deactivate.o(.text._tx_timer_deactivate) refers to tx_timer_initialize.o(.bss._tx_timer_expired_timer_ptr) for _tx_timer_expired_timer_ptr + tx_timer_deactivate.o(.ARM.exidx.text._tx_timer_deactivate) refers to tx_timer_deactivate.o(.text._tx_timer_deactivate) for [Anonymous Symbol] + tx_timer_delete.o(.text._tx_timer_delete) refers to tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate) for _tx_timer_system_deactivate + tx_timer_delete.o(.text._tx_timer_delete) refers to tx_timer_initialize.o(.bss._tx_timer_created_count) for _tx_timer_created_count + tx_timer_delete.o(.text._tx_timer_delete) refers to tx_timer_initialize.o(.bss._tx_timer_created_ptr) for _tx_timer_created_ptr + tx_timer_delete.o(.ARM.exidx.text._tx_timer_delete) refers to tx_timer_delete.o(.text._tx_timer_delete) for [Anonymous Symbol] + tx_timer_expiration_process.o(.text._tx_timer_expiration_process) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_timer_expiration_process.o(.text._tx_timer_expiration_process) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + tx_timer_expiration_process.o(.text._tx_timer_expiration_process) refers to tx_thread_system_resume.o(.text._tx_thread_system_resume) for _tx_thread_system_resume + tx_timer_expiration_process.o(.ARM.exidx.text._tx_timer_expiration_process) refers to tx_timer_expiration_process.o(.text._tx_timer_expiration_process) for [Anonymous Symbol] + tx_timer_info_get.o(.text._tx_timer_info_get) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_info_get.o(.text._tx_timer_info_get) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_info_get.o(.text._tx_timer_info_get) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_info_get.o(.text._tx_timer_info_get) refers to tx_timer_initialize.o(.bss._tx_timer_expired_timer_ptr) for _tx_timer_expired_timer_ptr + tx_timer_info_get.o(.ARM.exidx.text._tx_timer_info_get) refers to tx_timer_info_get.o(.text._tx_timer_info_get) for [Anonymous Symbol] + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_system_clock) for _tx_timer_system_clock + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_time_slice) for _tx_timer_time_slice + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_expired_time_slice) for _tx_timer_expired_time_slice + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_expired) for _tx_timer_expired + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_expired_timer_ptr) for _tx_timer_expired_timer_ptr + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_list) for _tx_timer_list + tx_timer_initialize.o(.text._tx_timer_initialize) refers to rt_memclr_w.o(.text) for __aeabi_memclr4 + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_stack_start) for _tx_timer_stack_start + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_thread_stack_area) for _tx_timer_thread_stack_area + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_stack_size) for _tx_timer_stack_size + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_priority) for _tx_timer_priority + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.rodata.str1.1) for .L.str + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_thread_entry.o(.text._tx_timer_thread_entry) for _tx_timer_thread_entry + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_thread_create.o(.text._tx_thread_create) for _tx_thread_create + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_created_ptr) for _tx_timer_created_ptr + tx_timer_initialize.o(.text._tx_timer_initialize) refers to tx_timer_initialize.o(.bss._tx_timer_created_count) for _tx_timer_created_count + tx_timer_initialize.o(.ARM.exidx.text._tx_timer_initialize) refers to tx_timer_initialize.o(.text._tx_timer_initialize) for [Anonymous Symbol] + tx_timer_system_activate.o(.text._tx_timer_system_activate) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_system_activate.o(.text._tx_timer_system_activate) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_system_activate.o(.text._tx_timer_system_activate) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_system_activate.o(.ARM.exidx.text._tx_timer_system_activate) refers to tx_timer_system_activate.o(.text._tx_timer_system_activate) for [Anonymous Symbol] + tx_timer_system_deactivate.o(.ARM.exidx.text._tx_timer_system_deactivate) refers to tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate) for [Anonymous Symbol] + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_current_ptr) for _tx_timer_current_ptr + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_list_end) for _tx_timer_list_end + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_list_start) for _tx_timer_list_start + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_expired) for _tx_timer_expired + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_expired_timer_ptr) for _tx_timer_expired_timer_ptr + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_system_activate.o(.text._tx_timer_system_activate) for _tx_timer_system_activate + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + tx_timer_thread_entry.o(.text._tx_timer_thread_entry) refers to tx_thread_system_suspend.o(.text._tx_thread_system_suspend) for _tx_thread_system_suspend + tx_timer_thread_entry.o(.ARM.exidx.text._tx_timer_thread_entry) refers to tx_timer_thread_entry.o(.text._tx_timer_thread_entry) for [Anonymous Symbol] + txe_timer_activate.o(.text._txe_timer_activate) refers to tx_timer_activate.o(.text._tx_timer_activate) for _tx_timer_activate + txe_timer_activate.o(.ARM.exidx.text._txe_timer_activate) refers to txe_timer_activate.o(.text._txe_timer_activate) for [Anonymous Symbol] + txe_timer_change.o(.text._txe_timer_change) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_timer_change.o(.text._txe_timer_change) refers to tx_timer_change.o(.text._tx_timer_change) for _tx_timer_change + txe_timer_change.o(.ARM.exidx.text._txe_timer_change) refers to txe_timer_change.o(.text._txe_timer_change) for [Anonymous Symbol] + txe_timer_create.o(.text._txe_timer_create) refers to tx_thread_initialize.o(.bss._tx_thread_preempt_disable) for _tx_thread_preempt_disable + txe_timer_create.o(.text._txe_timer_create) refers to tx_timer_initialize.o(.bss._tx_timer_created_ptr) for _tx_timer_created_ptr + txe_timer_create.o(.text._txe_timer_create) refers to tx_timer_initialize.o(.bss._tx_timer_created_count) for _tx_timer_created_count + txe_timer_create.o(.text._txe_timer_create) refers to tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) for _tx_thread_system_preempt_check + txe_timer_create.o(.text._txe_timer_create) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_timer_create.o(.text._txe_timer_create) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_timer_create.o(.text._txe_timer_create) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_timer_create.o(.text._txe_timer_create) refers to tx_timer_create.o(.text._tx_timer_create) for _tx_timer_create + txe_timer_create.o(.ARM.exidx.text._txe_timer_create) refers to txe_timer_create.o(.text._txe_timer_create) for [Anonymous Symbol] + txe_timer_deactivate.o(.text._txe_timer_deactivate) refers to tx_timer_deactivate.o(.text._tx_timer_deactivate) for _tx_timer_deactivate + txe_timer_deactivate.o(.ARM.exidx.text._txe_timer_deactivate) refers to txe_timer_deactivate.o(.text._txe_timer_deactivate) for [Anonymous Symbol] + txe_timer_delete.o(.text._txe_timer_delete) refers to tx_thread_initialize.o(.data._tx_thread_system_state) for _tx_thread_system_state + txe_timer_delete.o(.text._txe_timer_delete) refers to tx_thread_initialize.o(.bss._tx_thread_current_ptr) for _tx_thread_current_ptr + txe_timer_delete.o(.text._txe_timer_delete) refers to tx_timer_initialize.o(.bss._tx_timer_thread) for _tx_timer_thread + txe_timer_delete.o(.text._txe_timer_delete) refers to tx_timer_delete.o(.text._tx_timer_delete) for _tx_timer_delete + txe_timer_delete.o(.ARM.exidx.text._txe_timer_delete) refers to txe_timer_delete.o(.text._txe_timer_delete) for [Anonymous Symbol] + txe_timer_info_get.o(.text._txe_timer_info_get) refers to tx_timer_info_get.o(.text._tx_timer_info_get) for _tx_timer_info_get + txe_timer_info_get.o(.ARM.exidx.text._txe_timer_info_get) refers to txe_timer_info_get.o(.text._txe_timer_info_get) for [Anonymous Symbol] + hcble.o(.text.HCBle_SendData) refers to hcble.o(.bss.HC_Send_Data) for HC_Send_Data + hcble.o(.text.HCBle_SendData) refers to vsprintf.o(.text) for vsprintf + hcble.o(.text.HCBle_SendData) refers to strlen.o(.text) for strlen + hcble.o(.text.HCBle_SendData) refers to usart.o(.bss.huart1) for huart1 + hcble.o(.text.HCBle_SendData) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit) for HAL_UART_Transmit + hcble.o(.ARM.exidx.text.HCBle_SendData) refers to hcble.o(.text.HCBle_SendData) for [Anonymous Symbol] + hcble.o(.text.HAL_UART_RxCpltCallback) refers to hcble.o(.bss.rx_data) for rx_data + hcble.o(.text.HAL_UART_RxCpltCallback) refers to hcble.o(.bss.rx_index) for rx_index + hcble.o(.text.HAL_UART_RxCpltCallback) refers to hcble.o(.bss.HC_Recevie) for HC_Recevie + hcble.o(.text.HAL_UART_RxCpltCallback) refers to hcble.o(.bss.data_received) for data_received + hcble.o(.text.HAL_UART_RxCpltCallback) refers to rt_memclr.o(.text) for __aeabi_memclr + hcble.o(.text.HAL_UART_RxCpltCallback) refers to stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT) for HAL_UART_Receive_IT + hcble.o(.ARM.exidx.text.HAL_UART_RxCpltCallback) refers to hcble.o(.text.HAL_UART_RxCpltCallback) for [Anonymous Symbol] + vsprintf.o(.text) refers (Special) to _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) for _printf_a + vsprintf.o(.text) refers (Special) to _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) for _printf_c + vsprintf.o(.text) refers (Special) to _printf_charcount.o(.text) for _printf_charcount + vsprintf.o(.text) refers (Special) to _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) for _printf_d + vsprintf.o(.text) refers (Special) to _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) for _printf_e + vsprintf.o(.text) refers (Special) to _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) for _printf_f + vsprintf.o(.text) refers (Special) to printf1.o(x$fpl$printf1) for _printf_fp_dec + vsprintf.o(.text) refers (Special) to printf2.o(x$fpl$printf2) for _printf_fp_hex + vsprintf.o(.text) refers (Special) to _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) for _printf_g + vsprintf.o(.text) refers (Special) to _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) for _printf_i + vsprintf.o(.text) refers (Special) to _printf_dec.o(.text) for _printf_int_dec + vsprintf.o(.text) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + vsprintf.o(.text) refers (Special) to _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) for _printf_lc + vsprintf.o(.text) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + vsprintf.o(.text) refers (Special) to _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) for _printf_lld + vsprintf.o(.text) refers (Special) to _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) for _printf_lli + vsprintf.o(.text) refers (Special) to _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) for _printf_llo + vsprintf.o(.text) refers (Special) to _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) for _printf_llu + vsprintf.o(.text) refers (Special) to _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) for _printf_llx + vsprintf.o(.text) refers (Special) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + vsprintf.o(.text) refers (Special) to _printf_hex_int_ll_ptr.o(.text) for _printf_longlong_hex + vsprintf.o(.text) refers (Special) to _printf_oct_int_ll.o(.text) for _printf_longlong_oct + vsprintf.o(.text) refers (Special) to _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) for _printf_ls + vsprintf.o(.text) refers (Special) to _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) for _printf_n + vsprintf.o(.text) refers (Special) to _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) for _printf_o + vsprintf.o(.text) refers (Special) to _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) for _printf_p + vsprintf.o(.text) refers (Special) to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + vsprintf.o(.text) refers (Special) to _printf_pad.o(.text) for _printf_post_padding + vsprintf.o(.text) refers (Special) to _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) for _printf_s + vsprintf.o(.text) refers (Special) to _printf_str.o(.text) for _printf_str + vsprintf.o(.text) refers (Special) to _printf_truncate.o(.text) for _printf_truncate_signed + vsprintf.o(.text) refers (Special) to _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) for _printf_u + vsprintf.o(.text) refers (Special) to _printf_wctomb.o(.text) for _printf_wctomb + vsprintf.o(.text) refers (Special) to _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) for _printf_x + vsprintf.o(.text) refers to _printf_char_common.o(.text) for _printf_char_common + vsprintf.o(.text) refers to _sputc.o(.text) for _sputc + aeabi_memset.o(.text) refers to rt_memclr.o(.text) for _memset + rt_memclr.o(.text) refers to rt_memclr_w.o(.text) for _memset_w + __main.o(!!!main) refers to __rtentry.o(.ARM.Collect$$rtentry$$00000000) for __rt_entry + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for __rt_entry_li + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for __rt_entry_main + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) for __rt_entry_postli_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000009) for __rt_entry_postsh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry2.o(.ARM.Collect$$rtentry$$00000002) for __rt_entry_presh_1 + __rtentry.o(.ARM.Collect$$rtentry$$00000000) refers (Special) to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for __rt_entry_sh + aeabi_ldiv0_sigfpe.o(.text) refers to rt_div0.o(.text) for __rt_div0 + __printf.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + _printf_str.o(.text) refers (Special) to _printf_char.o(.text) for _printf_cs_common + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_str.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_signed + _printf_dec.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_char_common.o(.text) refers to __printf_flags_ss_wp.o(.text) for __printf + _printf_wctomb.o(.text) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_wctomb.o(.text) refers to _c16rtomb.o(.text) for _wcrtomb + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_wctomb.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_wctomb.o(.text) refers to _printf_wctomb.o(.constdata) for .constdata + _printf_wctomb.o(.constdata) refers (Special) to _printf_wchar.o(.text) for _printf_lcs_common + _printf_longlong_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_longlong_dec.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_oct_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_oct_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll.o(.text) refers to _printf_hex_ll.o(.constdata) for .constdata + _printf_hex_int.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int.o(.text) refers to _printf_hex_int.o(.constdata) for .constdata + _printf_hex_int_ll.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll.o(.text) refers to _printf_hex_int_ll.o(.constdata) for .constdata + _printf_hex_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ptr.o(.text) refers to _printf_hex_ptr.o(.constdata) for .constdata + _printf_hex_int_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ptr.o(.text) refers to _printf_hex_int_ptr.o(.constdata) for .constdata + _printf_hex_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_ll_ptr.o(.text) refers to _printf_hex_ll_ptr.o(.constdata) for .constdata + _printf_hex_int_ll_ptr.o(.text) refers to _printf_intcommon.o(.text) for _printf_int_common + _printf_hex_int_ll_ptr.o(.text) refers (Weak) to _printf_truncate.o(.text) for _printf_truncate_unsigned + _printf_hex_int_ll_ptr.o(.text) refers to _printf_hex_int_ll_ptr.o(.constdata) for .constdata + __printf_flags.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags.o(.text) refers to __printf_flags.o(.constdata) for .constdata + __printf_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss.o(.text) refers to __printf_flags_ss.o(.constdata) for .constdata + __printf_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_wp.o(.text) refers to __printf_flags_wp.o(.constdata) for .constdata + __printf_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_wp.o(i._is_digit) for _is_digit + __printf_flags_ss_wp.o(.text) refers to _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) for _printf_percent + __printf_flags_ss_wp.o(.text) refers to __printf_flags_ss_wp.o(.constdata) for .constdata + _printf_c.o(.ARM.Collect$$_printf_percent$$00000013) refers (Weak) to _printf_char.o(.text) for _printf_char + _printf_s.o(.ARM.Collect$$_printf_percent$$00000014) refers (Weak) to _printf_char.o(.text) for _printf_string + _printf_n.o(.ARM.Collect$$_printf_percent$$00000001) refers (Weak) to _printf_charcount.o(.text) for _printf_charcount + _printf_x.o(.ARM.Collect$$_printf_percent$$0000000C) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_int_hex + _printf_p.o(.ARM.Collect$$_printf_percent$$00000002) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_hex_ptr + _printf_o.o(.ARM.Collect$$_printf_percent$$0000000B) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_int_oct + _printf_i.o(.ARM.Collect$$_printf_percent$$00000008) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_d.o(.ARM.Collect$$_printf_percent$$00000009) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_u.o(.ARM.Collect$$_printf_percent$$0000000A) refers (Weak) to _printf_dec.o(.text) for _printf_int_dec + _printf_f.o(.ARM.Collect$$_printf_percent$$00000003) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_e.o(.ARM.Collect$$_printf_percent$$00000004) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_g.o(.ARM.Collect$$_printf_percent$$00000005) refers (Weak) to printf1.o(x$fpl$printf1) for _printf_fp_dec + _printf_a.o(.ARM.Collect$$_printf_percent$$00000006) refers (Weak) to printf2.o(x$fpl$printf2) for _printf_fp_hex + _printf_percent.o(.ARM.Collect$$_printf_percent$$00000000) refers (Special) to _printf_percent_end.o(.ARM.Collect$$_printf_percent$$00000017) for _printf_percent_end + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lli.o(.ARM.Collect$$_printf_percent$$0000000D) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_lld.o(.ARM.Collect$$_printf_percent$$0000000E) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llu.o(.ARM.Collect$$_printf_percent$$0000000F) refers (Weak) to _printf_longlong_dec.o(.text) for _printf_longlong_dec + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_lc.o(.ARM.Collect$$_printf_percent$$00000015) refers (Weak) to _printf_wchar.o(.text) for _printf_wchar + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Special) to _printf_l.o(.ARM.Collect$$_printf_percent$$00000012) for _printf_l + _printf_ls.o(.ARM.Collect$$_printf_percent$$00000016) refers (Weak) to _printf_wchar.o(.text) for _printf_wstring + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llo.o(.ARM.Collect$$_printf_percent$$00000010) refers (Weak) to _printf_oct_int_ll.o(.text) for _printf_ll_oct + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Special) to _printf_ll.o(.ARM.Collect$$_printf_percent$$00000007) for _printf_ll + _printf_llx.o(.ARM.Collect$$_printf_percent$$00000011) refers (Weak) to _printf_hex_int_ll_ptr.o(.text) for _printf_ll_hex + printf1.o(x$fpl$printf1) refers to _printf_fp_dec.o(.text) for _printf_fp_dec_real + printf2.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + printf2b.o(x$fpl$printf2) refers to _printf_fp_hex.o(.text) for _printf_fp_hex_real + __rtentry2.o(.ARM.Collect$$rtentry$$00000008) refers to boardinit2.o(.text) for _platform_post_stackheap_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) refers to libinit.o(.ARM.Collect$$libinit$$00000000) for __rt_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) refers to boardinit3.o(.text) for _platform_post_lib_init + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to main.o(.text.main) for main + __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) refers to exit.o(.text) for exit + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000001) for .ARM.Collect$$rtentry$$00000001 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$00000008) for .ARM.Collect$$rtentry$$00000008 + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) for .ARM.Collect$$rtentry$$0000000A + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000B) for .ARM.Collect$$rtentry$$0000000B + __rtentry2.o(.ARM.exidx) refers to __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) for .ARM.Collect$$rtentry$$0000000D + __rtentry4.o(.ARM.Collect$$rtentry$$00000004) refers to sys_stackheap_outer.o(.text) for __user_setup_stackheap + __rtentry4.o(.ARM.exidx) refers to __rtentry4.o(.ARM.Collect$$rtentry$$00000004) for .ARM.Collect$$rtentry$$00000004 + rt_div0.o(.text) refers to defsig_fpe_outer.o(.text) for __rt_SIGFPE + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_intcommon.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_dec.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_dec.o(.text) refers (Special) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + _printf_fp_dec.o(.text) refers to bigflt0.o(.text) for _btod_etento + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_d2e) for _btod_d2e + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv + _printf_fp_dec.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul + _printf_fp_dec.o(.text) refers to lludiv10.o(.text) for _ll_udiv10 + _printf_fp_dec.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_dec.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + _printf_fp_dec.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_dec_accurate.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_dec_accurate.o(.text) refers (Special) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + _printf_fp_dec_accurate.o(.text) refers to btod_accurate.o(.text) for _btod_main + _printf_fp_dec_accurate.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_dec_accurate.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_dec_accurate.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec_accurate.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_dec_accurate.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + _printf_fp_dec_accurate.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_fp_hex.o(.text) refers to fpclassify.o(i.__ARM_fpclassify) for __ARM_fpclassify + _printf_fp_hex.o(.text) refers to _printf_fp_infnan.o(.text) for _printf_fp_infnan + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_hex.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + _printf_fp_hex.o(.text) refers to _printf_fp_hex.o(.constdata) for .constdata + _printf_fp_hex.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + _printf_char.o(.text) refers (Weak) to _printf_str.o(.text) for _printf_str + _printf_wchar.o(.text) refers (Weak) to _printf_wctomb.o(.text) for _printf_wctomb + _c16rtomb.o(.text) refers to rt_ctype_table.o(.text) for __rt_ctype_table + sys_stackheap_outer.o(.text) refers to libspace.o(.text) for __user_perproc_libspace + sys_stackheap_outer.o(.text) refers to startup_stm32h563xx.o(.text) for __user_initial_stackheap + rt_ctype_table.o(.text) refers to rt_locale_intlibspace.o(.text) for __rt_locale + rt_ctype_table.o(.text) refers to lc_ctype_c.o(locale$$code) for _get_lc_ctype + rt_locale.o(.text) refers to rt_locale.o(.bss) for __rt_locale_data + rt_locale_intlibspace.o(.text) refers to libspace.o(.bss) for __libspace_start + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_pre_padding + _printf_fp_infnan.o(.text) refers (Weak) to _printf_pad.o(.text) for _printf_post_padding + bigflt0.o(.text) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + bigflt0.o(.text) refers to btod.o(CL$$btod_emul) for _btod_emul + bigflt0.o(.text) refers to btod.o(CL$$btod_ediv) for _btod_ediv + bigflt0.o(.text) refers to bigflt0.o(.constdata) for .constdata + bigflt0.o(.constdata) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e) refers to btod.o(CL$$btod_d2e_norm_op1) for _d2e_norm_op1 + btod.o(CL$$btod_d2e_norm_op1) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_d2e_norm_op1) refers to btod.o(CL$$btod_d2e_denorm_low) for _d2e_denorm_low + btod.o(CL$$btod_d2e_denorm_low) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emul) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common + btod.o(CL$$btod_emul) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_ediv) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_div_common) for __btod_div_common + btod.o(CL$$btod_ediv) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_emuld) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_mult_common) for __btod_mult_common + btod.o(CL$$btod_emuld) refers to btod.o(CL$$btod_e2d) for _e2d + btod.o(CL$$btod_edivd) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_div_common) for __btod_div_common + btod.o(CL$$btod_edivd) refers to btod.o(CL$$btod_e2d) for _e2d + btod.o(CL$$btod_e2e) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_e2d) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_e2d) refers to btod.o(CL$$btod_e2e) for _e2e + btod.o(CL$$btod_mult_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod.o(CL$$btod_div_common) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + btod_accurate.o(.text) refers to btod_accurate_common.o(.text) for _btod_common + lc_numeric_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000018) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000018) for __rt_lib_init_lc_numeric_2 + lc_numeric_c.o(locale$$code) refers to strcmpv8m_maindsp.o(.text) for strcmp + lc_numeric_c.o(locale$$code) refers to lc_numeric_c.o(locale$$data) for __lcnum_c_name + exit.o(.text) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for __rt_exit + defsig_fpe_outer.o(.text) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig_fpe_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_fpe_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000030) for __rt_lib_init_alloca_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000002E) for __rt_lib_init_argv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001D) for __rt_lib_init_atexit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000023) for __rt_lib_init_clock_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000034) for __rt_lib_init_cpp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000032) for __rt_lib_init_exceptions_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000001) for __rt_lib_init_fp_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000021) for __rt_lib_init_fp_trap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000025) for __rt_lib_init_getenv_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000C) for __rt_lib_init_heap_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000013) for __rt_lib_init_lc_collate_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000015) for __rt_lib_init_lc_ctype_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000017) for __rt_lib_init_lc_monetary_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000019) for __rt_lib_init_lc_numeric_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001B) for __rt_lib_init_lc_time_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000006) for __rt_lib_init_preinit_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000010) for __rt_lib_init_rand_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000004) for __rt_lib_init_relocate_pie_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000035) for __rt_lib_init_return + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000001F) for __rt_lib_init_signal_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000027) for __rt_lib_init_stdio_1 + libinit.o(.ARM.Collect$$libinit$$00000000) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$0000000E) for __rt_lib_init_user_alloc_1 + istatus.o(x$fpl$ieeestatus) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + fpclassify.o(i.__ARM_fpclassify) refers (Special) to usenofp.o(x$fpl$usenofp) for __I$use$fp + libspace.o(.text) refers to libspace.o(.bss) for __libspace_start + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.Collect$$rtexit$$00000000) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for __rt_exit_exit + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for __rt_exit_ls + rtexit.o(.ARM.exidx) refers (Special) to rtexit2.o(.ARM.Collect$$rtexit$$00000002) for __rt_exit_prels_1 + rtexit.o(.ARM.exidx) refers to rtexit.o(.ARM.Collect$$rtexit$$00000000) for .ARM.Collect$$rtexit$$00000000 + rt_raise.o(.text) refers to __raise.o(.text) for __raise + rt_raise.o(.text) refers to sys_exit.o(.text) for _sys_exit + btod_accurate_common.o(.text) refers to llushr.o(.text) for __aeabi_llsr + lc_ctype_c.o(locale$$data) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000014) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers (Special) to libinit2.o(.ARM.Collect$$libinit$$00000014) for __rt_lib_init_lc_ctype_2 + lc_ctype_c.o(locale$$code) refers to strcmpv8m_maindsp.o(.text) for strcmp + lc_ctype_c.o(locale$$code) refers to lc_ctype_c.o(locale$$data) for __lcctype_c_name + defsig_exit.o(.text) refers to sys_exit.o(.text) for _sys_exit + defsig_fpe_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + libinit2.o(.ARM.Collect$$libinit$$00000001) refers to fpinit.o(x$fpl$fpinit) for _fp_init + libinit2.o(.ARM.Collect$$libinit$$00000011) refers (Weak) to rt_locale_intlibspace.o(.text) for __rt_locale + libinit2.o(.ARM.Collect$$libinit$$00000012) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000014) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000014) refers (Weak) to lc_ctype_c.o(locale$$code) for _get_lc_ctype + libinit2.o(.ARM.Collect$$libinit$$00000016) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000018) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000018) refers (Weak) to lc_numeric_c.o(locale$$code) for _get_lc_numeric + libinit2.o(.ARM.Collect$$libinit$$0000001A) refers to libinit2.o(.ARM.Collect$$libinit$$00000011) for .ARM.Collect$$libinit$$00000011 + libinit2.o(.ARM.Collect$$libinit$$00000028) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + libinit2.o(.ARM.Collect$$libinit$$00000029) refers to argv_veneer.o(.emb_text) for __ARM_argv_veneer + sys_exit.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_exit_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_exit_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + rtexit2.o(.ARM.Collect$$rtexit$$00000003) refers to libshutdown.o(.ARM.Collect$$libshutdown$$00000000) for __rt_lib_shutdown + rtexit2.o(.ARM.Collect$$rtexit$$00000004) refers to sys_exit.o(.text) for _sys_exit + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000001) for .ARM.Collect$$rtexit$$00000001 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000003) for .ARM.Collect$$rtexit$$00000003 + rtexit2.o(.ARM.exidx) refers to rtexit2.o(.ARM.Collect$$rtexit$$00000004) for .ARM.Collect$$rtexit$$00000004 + __raise.o(.text) refers to defsig.o(CL$$defsig) for __default_signal_handler + defsig_general.o(.text) refers to sys_wrch.o(.text) for _ttywrch + argv_veneer.o(.emb_text) refers to no_argv.o(.text) for __ARM_get_argv + sys_wrch.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_wrch_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_wrch_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig.o(CL$$defsig) refers to defsig_fpe_inner.o(.text) for __rt_SIGFPE_inner + defsig.o(CL$$defsig) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + _get_argv_nomalloc.o(.text) refers (Special) to hrguard.o(.text) for __heap_region$guard + _get_argv_nomalloc.o(.text) refers to defsig_rtmem_outer.o(.text) for __rt_SIGRTMEM + _get_argv_nomalloc.o(.text) refers to sys_command.o(.text) for _sys_command_string + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) for __rt_lib_shutdown_cpp_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) for __rt_lib_shutdown_fp_trap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) for __rt_lib_shutdown_heap_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) for __rt_lib_shutdown_return + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) for __rt_lib_shutdown_signal_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) for __rt_lib_shutdown_stdio_1 + libshutdown.o(.ARM.Collect$$libshutdown$$00000000) refers (Special) to libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) for __rt_lib_shutdown_user_alloc_1 + sys_command.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + sys_command_hlt.o(.text) refers (Special) to use_no_semi.o(.text) for __I$use$semihosting + sys_command_hlt.o(.text) refers (Special) to indicate_semi.o(.text) for __semihosting_library_function + defsig_abrt_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtred_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_rtmem_outer.o(.text) refers to defsig_rtmem_inner.o(.text) for __rt_SIGRTMEM_inner + defsig_rtmem_outer.o(.text) refers to defsig_exit.o(.text) for __sig_exit + defsig_rtmem_formal.o(.text) refers to rt_raise.o(.text) for __rt_raise + defsig_stak_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_pvfn_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_cppl_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_segv_inner.o(.text) refers to defsig_general.o(.text) for __default_signal_display + defsig_other.o(.text) refers to defsig_general.o(.text) for __default_signal_display + + +============================================================================== + +Removing Unused input sections from the image. + + Removing main.o(.text), (0 bytes). + Removing main.o(.ARM.exidx.text.main), (8 bytes). + Removing main.o(.ARM.exidx.text.SystemClock_Config), (8 bytes). + Removing main.o(.ARM.exidx.text.Error_Handler), (8 bytes). + Removing main.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing main.o(.ARM.use_no_argv), (4 bytes). + Removing gpio.o(.text), (0 bytes). + Removing gpio.o(.ARM.exidx.text.MX_GPIO_Init), (8 bytes). + Removing memorymap.o(.text), (0 bytes). + Removing app_threadx.o(.text), (0 bytes). + Removing app_threadx.o(.ARM.exidx.text.App_ThreadX_Init), (8 bytes). + Removing app_threadx.o(.ARM.exidx.text.MX_ThreadX_Init), (8 bytes). + Removing usart.o(.text), (0 bytes). + Removing usart.o(.ARM.exidx.text.MX_USART1_UART_Init), (8 bytes). + Removing usart.o(.ARM.exidx.text.HAL_UART_MspInit), (8 bytes). + Removing usart.o(.text.HAL_UART_MspDeInit), (68 bytes). + Removing usart.o(.ARM.exidx.text.HAL_UART_MspDeInit), (8 bytes). + Removing stm32h5xx_it.o(.text), (0 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.NMI_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.HardFault_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.MemManage_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.BusFault_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.UsageFault_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.DebugMon_Handler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.TIM1_UP_IRQHandler), (8 bytes). + Removing stm32h5xx_it.o(.ARM.exidx.text.USART1_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_msp.o(.text), (0 bytes). + Removing stm32h5xx_hal_msp.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.text), (0 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_InitTick), (8 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.text.HAL_SuspendTick), (20 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_SuspendTick), (8 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.text.HAL_ResumeTick), (20 bytes). + Removing stm32h5xx_hal_timebase_tim.o(.ARM.exidx.text.HAL_ResumeTick), (8 bytes). + Removing app_azure_rtos.o(.text), (0 bytes). + Removing app_azure_rtos.o(.ARM.exidx.text.tx_application_define), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text), (0 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_Base_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_DeInit), (178 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start), (390 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop), (70 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop_IT), (82 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_DMA), (530 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedCplt), (22 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMAPeriodElapsedHalfCplt), (22 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAPeriodElapsedHalfCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMAError), (154 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMAError), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMA_Start_IT), (122 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMA_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Stop_DMA), (92 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Init), (168 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DeInit), (178 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start), (892 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_CCxChannelCmd), (54 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_CCxChannelCmd), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop), (492 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_IT), (1006 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_IT), (606 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Start_DMA), (1468 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseCplt), (116 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMADelayPulseHalfCplt), (116 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMADelayPulseHalfCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_Stop_DMA), (638 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Init), (168 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_DeInit), (178 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start), (892 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop), (492 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_IT), (1006 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_IT), (606 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Start_DMA), (1468 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_Stop_DMA), (638 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Init), (168 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_DeInit), (178 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start), (822 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop), (286 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_IT), (936 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_IT), (400 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Start_DMA), (1274 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMACaptureCplt), (116 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMACaptureHalfCplt), (116 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMACaptureHalfCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_Stop_DMA), (430 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Init), (144 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_DeInit), (128 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start), (408 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop), (402 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Start_IT), (432 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_Stop_IT), (426 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Init), (308 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Init), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_DeInit), (128 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start), (334 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop), (390 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_IT), (382 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_IT), (438 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Start_DMA), (896 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_Stop_DMA), (470 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_DelayElapsedCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_ConfigChannel), (196 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_ConfigChannel), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC1_SetConfig), (500 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC1_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC2_SetConfig), (528 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC2_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC3_SetConfig), (526 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC3_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC4_SetConfig), (528 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC4_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC5_SetConfig), (290 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC5_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_OC6_SetConfig), (292 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_OC6_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_ConfigChannel), (304 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_ConfigChannel), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI1_SetConfig), (440 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI2_SetConfig), (108 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI3_SetConfig), (106 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI3_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI4_SetConfig), (108 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI4_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_ConfigChannel), (432 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_ConfigChannel), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_ConfigChannel), (418 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_ConfigChannel), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStart), (350 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStart), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiWriteStart), (802 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiWriteStart), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMATriggerCplt), (22 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_DMATriggerHalfCplt), (22 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_DMATriggerHalfCplt), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_WriteStop), (202 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_WriteStop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStart), (350 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStart), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_MultiReadStart), (802 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_MultiReadStart), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurst_ReadStop), (202 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurst_ReadStop), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_GenerateEvent), (92 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GenerateEvent), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigOCrefClear), (500 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigOCrefClear), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_ETR_SetConfig), (52 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ETR_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigClockSource), (520 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigClockSource), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI1_ConfigInputStage), (80 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI1_ConfigInputStage), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_ITRx_SetConfig), (48 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_ITRx_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_TI2_ConfigInputStage), (82 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_TI2_ConfigInputStage), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ConfigTI1Input), (44 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ConfigTI1Input), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro), (150 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.TIM_SlaveTimer_SetConfig), (442 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.TIM_SlaveTimer_SetConfig), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_SlaveConfigSynchro_IT), (150 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_SlaveConfigSynchro_IT), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ReadCapturedValue), (86 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ReadCapturedValue), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PeriodElapsedHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_CaptureHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_TriggerHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_ErrorCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_ErrorCallback), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Base_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OC_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_PWM_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_IC_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_OnePulse_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_OnePulse_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_Encoder_GetState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_Encoder_GetState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_GetActiveChannel), (12 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetActiveChannel), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_GetChannelState), (142 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_GetChannelState), (8 bytes). + Removing stm32h5xx_hal_tim.o(.text.HAL_TIM_DMABurstState), (14 bytes). + Removing stm32h5xx_hal_tim.o(.ARM.exidx.text.HAL_TIM_DMABurstState), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Init), (298 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Init), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspInit), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_DeInit), (128 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_DeInit), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start), (490 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop), (102 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_IT), (502 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_IT), (114 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Start_DMA), (584 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_Stop_DMA), (110 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start), (558 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.TIM_CCxNChannelCmd), (54 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_CCxNChannelCmd), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop), (208 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_IT), (684 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_IT), (356 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Start_DMA), (1086 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.TIM_DMADelayPulseNCplt), (116 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMADelayPulseNCplt), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.TIM_DMAErrorCCxN), (146 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIM_DMAErrorCCxN), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OCN_Stop_DMA), (352 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OCN_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start), (558 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop), (208 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_IT), (684 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_IT), (356 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Start_DMA), (1086 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Start_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_PWMN_Stop_DMA), (352 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_PWMN_Stop_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start), (186 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop), (182 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Start_IT), (210 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Start_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OnePulseN_Stop_IT), (206 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OnePulseN_Stop_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent), (170 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_IT), (170 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_IT), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigCommutEvent_DMA), (212 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigCommutEvent_DMA), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationCplt), (30 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationCplt), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.TIMEx_DMACommutationHalfCplt), (30 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.TIMEx_DMACommutationHalfCplt), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_MasterConfigSynchronization), (530 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_MasterConfigSynchronization), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakDeadTime), (340 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakDeadTime), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigBreakInput), (286 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigBreakInput), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_RemapConfig), (88 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_RemapConfig), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TISelection), (248 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TISelection), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_GroupChannel5), (108 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GroupChannel5), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisarmBreakInput), (142 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisarmBreakInput), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ReArmBreakInput), (218 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ReArmBreakInput), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DitheringEnable), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DitheringEnable), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DitheringDisable), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DitheringDisable), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_OC_ConfigPulseOnCompare), (130 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_OC_ConfigPulseOnCompare), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigSlaveModePreload), (32 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigSlaveModePreload), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableSlaveModePreload), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableSlaveModePreload), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableSlaveModePreload), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableSlaveModePreload), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableDeadTimePreload), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableDeadTimePreload), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableDeadTimePreload), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableDeadTimePreload), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigDeadTime), (32 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigDeadTime), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigAsymmetricalDeadTime), (32 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigAsymmetricalDeadTime), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableAsymmetricalDeadTime), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableAsymmetricalDeadTime), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableAsymmetricalDeadTime), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableAsymmetricalDeadTime), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_ConfigEncoderIndex), (136 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_ConfigEncoderIndex), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableEncoderIndex), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableEncoderIndex), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableEncoderIndex), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableEncoderIndex), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EnableEncoderFirstIndex), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EnableEncoderFirstIndex), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DisableEncoderFirstIndex), (22 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DisableEncoderFirstIndex), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_CommutHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_BreakCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_Break2Callback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_EncoderIndexCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_DirectionChangeCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_IndexErrorCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_TransitionErrorCallback), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_HallSensor_GetState), (14 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_HallSensor_GetState), (8 bytes). + Removing stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_GetChannelNState), (94 bytes). + Removing stm32h5xx_hal_tim_ex.o(.ARM.exidx.text.HAL_TIMEx_GetChannelNState), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text), (0 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriorityGrouping), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.NVIC_EncodePriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_EnableIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_EnableIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_DisableIRQ), (20 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_DisableIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_DisableIRQ), (56 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_DisableIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SystemReset), (4 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SystemReset), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_SystemReset), (38 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SystemReset), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriorityGrouping), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPriority), (36 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.NVIC_DecodePriority), (118 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.NVIC_DecodePriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_GetPriority), (66 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPriority), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPendingIRQ), (20 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_SetPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_SetPendingIRQ), (48 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_SetPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetPendingIRQ), (20 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_GetPendingIRQ), (64 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_ClearPendingIRQ), (20 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_ClearPendingIRQ), (48 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_ClearPendingIRQ), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_NVIC_GetActive), (20 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_NVIC_GetActive), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.__NVIC_GetActive), (64 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.__NVIC_GetActive), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Config), (74 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Config), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_CLKSourceConfig), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_GetCLKSourceConfig), (98 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_GetCLKSourceConfig), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_Callback), (2 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_SYSTICK_Callback), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_Enable), (52 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Enable), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_Disable), (46 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_Disable), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_EnableRegion), (36 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_EnableRegion), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_DisableRegion), (36 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_DisableRegion), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigRegion), (24 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigRegion), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.MPU_ConfigRegion), (82 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigRegion), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.HAL_MPU_ConfigMemoryAttributes), (24 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.HAL_MPU_ConfigMemoryAttributes), (8 bytes). + Removing stm32h5xx_hal_cortex.o(.text.MPU_ConfigMemoryAttributes), (94 bytes). + Removing stm32h5xx_hal_cortex.o(.ARM.exidx.text.MPU_ConfigMemoryAttributes), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text), (0 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_DeInit), (754 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_DeInit), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_OscConfig), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetHCLKFreq), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ClockConfig), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetSysClockFreq), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_MCOConfig), (200 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_MCOConfig), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK1Freq), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK2Freq), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetPCLK3Freq), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetOscConfig), (292 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetOscConfig), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetClockConfig), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetResetSource), (32 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetResetSource), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_EnableCSS), (18 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_EnableCSS), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_NMI_IRQHandler), (42 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_NMI_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_CSSCallback), (2 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_CSSCallback), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_ConfigAttributes), (66 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_ConfigAttributes), (8 bytes). + Removing stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetConfigAttributes), (64 bytes). + Removing stm32h5xx_hal_rcc.o(.ARM.exidx.text.HAL_RCC_GetConfigAttributes), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_PeriphCLKConfig), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL2_Config), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLL3_Config), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKConfig), (1282 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKConfig), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL1ClockFreq), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL2ClockFreq), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPLL3ClockFreq), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_GetPeriphCLKFreq), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL2), (390 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLL2), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.RCCEx_PLLSource_Enable), (318 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.RCCEx_PLLSource_Enable), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL2), (106 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLL2), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnablePLL3), (390 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnablePLL3), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisablePLL3), (106 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisablePLL3), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_WakeUpStopCLKConfig), (28 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_WakeUpStopCLKConfig), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_KerWakeUpStopCLKConfig), (28 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_KerWakeUpStopCLKConfig), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSECSS), (18 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSECSS), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSECSS), (18 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSECSS), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_IRQHandler), (28 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_LSECSS_Callback), (2 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_LSECSS_Callback), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_EnableLSCO), (84 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_EnableLSCO), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_DisableLSCO), (74 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_DisableLSCO), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSConfig), (112 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSConfig), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate), (18 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSSoftwareSynchronizationGenerate), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSGetSynchronizationInfo), (68 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSGetSynchronizationInfo), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRSWaitSynchronization), (328 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRSWaitSynchronization), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_IRQHandler), (272 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncOkCallback), (2 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncOkCallback), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_SyncWarnCallback), (2 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_SyncWarnCallback), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ExpectedSyncCallback), (2 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ExpectedSyncCallback), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_CRS_ErrorCallback), (8 bytes). + Removing stm32h5xx_hal_rcc_ex.o(.ARM.exidx.text.HAL_RCCEx_CRS_ErrorCallback), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text), (0 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program), (276 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.FLASH_WaitForLastOperation), (176 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_WaitForLastOperation), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord), (110 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_QuadWord), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.FLASH_Program_QuadWord_OBK), (142 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_QuadWord_OBK), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.FLASH_Program_HalfWord), (38 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_HalfWord), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.FLASH_Program_Word), (38 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.FLASH_Program_Word), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_Program_IT), (246 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Program_IT), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_IRQHandler), (432 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_OperationErrorCallback), (8 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OperationErrorCallback), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_EndOfOperationCallback), (8 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_EndOfOperationCallback), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_Unlock), (86 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Unlock), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_Lock), (48 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_Lock), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Unlock), (88 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Unlock), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Lock), (50 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Lock), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_OB_Launch), (40 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_OB_Launch), (8 bytes). + Removing stm32h5xx_hal_flash.o(.text.HAL_FLASH_GetError), (12 bytes). + Removing stm32h5xx_hal_flash.o(.ARM.exidx.text.HAL_FLASH_GetError), (8 bytes). + Removing stm32h5xx_hal_flash.o(.data.pFlash), (28 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase), (322 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_MassErase), (106 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_MassErase), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OBKErase), (26 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OBKErase), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_Erase_Sector), (96 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_Erase_Sector), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_Erase_IT), (192 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_Erase_IT), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBProgram), (338 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBProgram), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EnableWRP), (68 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EnableWRP), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_DisableWRP), (68 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_DisableWRP), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_ProdStateConfig), (28 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_ProdStateConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_UserConfig), (726 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_UserConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootAddrConfig), (40 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootAddrConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_BootLockConfig), (42 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_BootLockConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_LockConfig), (24 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_OTP_LockConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_HDPConfig), (74 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_HDPConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_EDATAConfig), (132 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_EDATAConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBGetConfig), (180 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBGetConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetProdState), (16 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetProdState), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetUser), (42 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetUser), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetWRP), (92 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetWRP), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetHDP), (80 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetHDP), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetEDATA), (92 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetEDATA), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_GetBootConfig), (50 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_GetBootConfig), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.FLASH_OB_OTP_GetLock), (12 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.FLASH_OB_OTP_GetLock), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Unlock), (86 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Unlock), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Lock), (48 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Lock), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap), (86 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Swap), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_OBK_Swap_IT), (84 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_OBK_Swap_IT), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetOperation), (50 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetOperation), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigBBAttributes), (176 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigBBAttributes), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetConfigBBAttributes), (96 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetConfigBBAttributes), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigPrivMode), (28 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigPrivMode), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetPrivMode), (16 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetPrivMode), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ConfigHDPExtension), (102 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ConfigHDPExtension), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EnableEccCorrectionInterrupt), (22 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EnableEccCorrectionInterrupt), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_DisableEccCorrectionInterrupt), (22 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_DisableEccCorrectionInterrupt), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_GetEccInfo), (536 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_GetEccInfo), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_ECCD_IRQHandler), (42 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_ECCD_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccDetectionCallback), (2 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EccDetectionCallback), (8 bytes). + Removing stm32h5xx_hal_flash_ex.o(.text.HAL_FLASHEx_EccCorrectionCallback), (2 bytes). + Removing stm32h5xx_hal_flash_ex.o(.ARM.exidx.text.HAL_FLASHEx_EccCorrectionCallback), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text), (0 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_Init), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DeInit), (334 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DeInit), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_ReadPin), (46 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_ReadPin), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WritePin), (44 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WritePin), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_WriteMultipleStatePin), (36 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_WriteMultipleStatePin), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_TogglePin), (38 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_TogglePin), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_LockPin), (90 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_LockPin), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EnableHighSPeedLowVoltage), (24 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EnableHighSPeedLowVoltage), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_DisableHighSPeedLowVoltage), (24 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_DisableHighSPeedLowVoltage), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_IRQHandler), (100 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Rising_Callback), (10 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Rising_Callback), (8 bytes). + Removing stm32h5xx_hal_gpio.o(.text.HAL_GPIO_EXTI_Falling_Callback), (10 bytes). + Removing stm32h5xx_hal_gpio.o(.ARM.exidx.text.HAL_GPIO_EXTI_Falling_Callback), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text), (0 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_Init), (960 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Init), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.DMA_Init), (1930 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_Init), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_DeInit), (476 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_DeInit), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_Start), (170 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.DMA_SetConfig), (64 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.DMA_SetConfig), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_Start_IT), (226 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Start_IT), (8 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort), (8 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_Abort_IT), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_PollForTransfer), (526 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_PollForTransfer), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_IRQHandler), (724 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_RegisterCallback), (142 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_RegisterCallback), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_UnRegisterCallback), (164 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_UnRegisterCallback), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetState), (14 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetState), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetError), (12 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetError), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_ConfigChannelAttributes), (114 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_ConfigChannelAttributes), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetConfigChannelAttributes), (156 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetConfigChannelAttributes), (8 bytes). + Removing stm32h5xx_hal_dma.o(.text.HAL_DMA_GetLockChannelAttributes), (88 bytes). + Removing stm32h5xx_hal_dma.o(.ARM.exidx.text.HAL_DMA_GetLockChannelAttributes), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Init), (898 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Init), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_Init), (1040 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_Init), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_DeInit), (502 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_DeInit), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start), (268 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetCLLRNodeInfo), (94 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetCLLRNodeInfo), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_Start_IT), (326 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_Start_IT), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_BuildNode), (90 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_BuildNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_BuildNode), (728 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_BuildNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_GetNodeConfig), (52 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_GetNodeConfig), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_GetNodeConfig), (532 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_GetNodeConfig), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode), (410 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesBaseAddresses), (104 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesBaseAddresses), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_CheckNodesTypes), (134 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CheckNodesTypes), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FindNode), (326 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FindNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Head), (214 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Head), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertNode_Tail), (240 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertNode_Tail), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode), (368 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_CleanQueue), (34 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_CleanQueue), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Head), (262 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Head), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_RemoveNode_Tail), (214 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_RemoveNode_Tail), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode), (534 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Head), (268 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Head), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ReplaceNode_Tail), (260 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ReplaceNode_Tail), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ResetQ), (148 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ResetQ), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ResetQueueNodes), (126 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ResetQueueNodes), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ), (618 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Head), (376 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Head), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_InsertQ_Tail), (364 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_InsertQ_Tail), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularModeConfig), (234 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularModeConfig), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_SetCircularMode), (202 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_SetCircularMode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ClearCircularMode), (158 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ClearCircularMode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToDynamic), (296 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToDynamic), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FillNode), (56 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FillNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToDynamic), (282 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToDynamic), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateDynamicQueueNodesCLLR), (222 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateDynamicQueueNodesCLLR), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_ConvertQToStatic), (202 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_ConvertQToStatic), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_UpdateStaticQueueNodesCLLR), (174 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_UpdateStaticQueueNodesCLLR), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ConvertNodeToStatic), (196 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ConvertNodeToStatic), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_LinkQ), (418 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_LinkQ), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_List_UnLinkQ), (112 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_List_UnLinkQ), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigDataHandling), (130 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigDataHandling), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigTrigger), (136 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigTrigger), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_ConfigRepeatBlock), (322 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_ConfigRepeatBlock), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend), (172 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Suspend_IT), (88 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Suspend_IT), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_Resume), (106 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_Resume), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.HAL_DMAEx_GetFifoLevel), (18 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.HAL_DMAEx_GetFifoLevel), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_FormatNode), (112 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_FormatNode), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.text.DMA_List_ClearUnusedFields), (44 bytes). + Removing stm32h5xx_hal_dma_ex.o(.ARM.exidx.text.DMA_List_ClearUnusedFields), (8 bytes). + Removing stm32h5xx_hal_dma_ex.o(.rodata.cst32), (64 bytes). + Removing stm32h5xx_hal_pwr.o(.text), (0 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DeInit), (2 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DeInit), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableBkUpAccess), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableBkUpAccess), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableBkUpAccess), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableBkUpAccess), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_ConfigPVD), (214 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigPVD), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnablePVD), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnablePVD), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisablePVD), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisablePVD), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableWakeUpPin), (34 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableWakeUpPin), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableWakeUpPin), (32 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableWakeUpPin), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSLEEPMode), (50 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSLEEPMode), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSTOPMode), (82 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTOPMode), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnterSTANDBYMode), (44 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnterSTANDBYMode), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableSleepOnExit), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSleepOnExit), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableSleepOnExit), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSleepOnExit), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_EnableSEVOnPend), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_EnableSEVOnPend), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_DisableSEVOnPend), (18 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_DisableSEVOnPend), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVD_IRQHandler), (76 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVD_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_PVDCallback), (2 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_PVDCallback), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_ConfigAttributes), (72 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_ConfigAttributes), (8 bytes). + Removing stm32h5xx_hal_pwr.o(.text.HAL_PWR_GetConfigAttributes), (64 bytes). + Removing stm32h5xx_hal_pwr.o(.ARM.exidx.text.HAL_PWR_GetConfigAttributes), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigSupply), (118 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigSupply), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetSupplyConfig), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetSupplyConfig), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlVoltageScaling), (130 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlVoltageScaling), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetVoltageRange), (16 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetVoltageRange), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ControlStopModeVoltageScaling), (30 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ControlStopModeVoltageScaling), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_GetStopModeVoltageRange), (16 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_GetStopModeVoltageRange), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_ConfigAVD), (210 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_ConfigAVD), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAVD), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAVD), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAVD), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAVD), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUSBVoltageDetector), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUSBVoltageDetector), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUSBVoltageDetector), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUSBVoltageDetector), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableVddUSB), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableVddUSB), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableVddUSB), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableVddUSB), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMonitoring), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMonitoring), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMonitoring), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMonitoring), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUCPDStandbyMode), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUCPDStandbyMode), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUCPDStandbyMode), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUCPDStandbyMode), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableUCPDDeadBattery), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableUCPDDeadBattery), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableUCPDDeadBattery), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableUCPDDeadBattery), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBatteryCharging), (36 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBatteryCharging), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBatteryCharging), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBatteryCharging), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableAnalogBooster), (26 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableAnalogBooster), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableAnalogBooster), (26 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableAnalogBooster), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_IRQHandler), (92 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Rising_Callback), (2 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_Rising_Callback), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_PVD_AVD_Falling_Callback), (2 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_PVD_AVD_Falling_Callback), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableWakeUpPin), (276 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableWakeUpPin), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableWakeUpPin), (32 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableWakeUpPin), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableFlashPowerDown), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableFlashPowerDown), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableFlashPowerDown), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableFlashPowerDown), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableMemoryShutOff), (24 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableMemoryShutOff), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableMemoryShutOff), (24 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableMemoryShutOff), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableBkupRAMRetention), (20 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableBkupRAMRetention), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableBkupRAMRetention), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableBkupRAMRetention), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableStandbyIORetention), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableStandbyIORetention), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableStandbyIORetention), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableStandbyIORetention), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_EnableStandbyJTAGIORetention), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_EnableStandbyJTAGIORetention), (8 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.text.HAL_PWREx_DisableStandbyJTAGIORetention), (18 bytes). + Removing stm32h5xx_hal_pwr_ex.o(.ARM.exidx.text.HAL_PWREx_DisableStandbyJTAGIORetention), (8 bytes). + Removing stm32h5xx_hal.o(.text), (0 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_Init), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_InitTick), (276 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_InitTick), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_MspInit), (2 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_MspInit), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DeInit), (184 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DeInit), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_MspDeInit), (2 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_MspDeInit), (8 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_IncTick), (8 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTick), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetTickPrio), (12 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTickPrio), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SetTickFreq), (106 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SetTickFreq), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetTickFreq), (12 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetTickFreq), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_Delay), (66 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_Delay), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SuspendTick), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SuspendTick), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_ResumeTick), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_ResumeTick), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetHalVersion), (8 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetHalVersion), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetREVID), (14 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetREVID), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetDEVID), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetDEVID), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetUIDw0), (12 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw0), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetUIDw1), (12 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw1), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_GetUIDw2), (12 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_GetUIDw2), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DBGMCU_EnableDBGStopMode), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStopMode), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DBGMCU_DisableDBGStopMode), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStopMode), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DBGMCU_EnableDBGStandbyMode), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_EnableDBGStandbyMode), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DBGMCU_DisableDBGStandbyMode), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DBGMCU_DisableDBGStandbyMode), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_VREFBUF_VoltageScalingConfig), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_VoltageScalingConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_VREFBUF_HighImpedanceConfig), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_HighImpedanceConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_VREFBUF_TrimmingConfig), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_VREFBUF_TrimmingConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_EnableVREFBUF), (86 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_EnableVREFBUF), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_DisableVREFBUF), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_DisableVREFBUF), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_ETHInterfaceSelect), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ETHInterfaceSelect), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_EnableVddIO1CompensationCell), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EnableVddIO1CompensationCell), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_DisableVddIO1CompensationCell), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_DisableVddIO1CompensationCell), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_EnableVddIO2CompensationCell), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EnableVddIO2CompensationCell), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_DisableVddIO2CompensationCell), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_DisableVddIO2CompensationCell), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_VDDCompensationCodeSelect), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDCompensationCodeSelect), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_VDDIOCompensationCodeSelect), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDIOCompensationCodeSelect), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetVddIO1CompensationCellReadyFlag), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetVddIO1CompensationCellReadyFlag), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetVddIO2CompensationCellReadyFlag), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetVddIO2CompensationCellReadyFlag), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_VDDCompensationCodeConfig), (36 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDCompensationCodeConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_VDDIOCompensationCodeConfig), (38 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_VDDIOCompensationCodeConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetNMOSVddCompensationValue), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetNMOSVddCompensationValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetPMOSVddCompensationValue), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetPMOSVddCompensationValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetNMOSVddIO2CompensationValue), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetNMOSVddIO2CompensationValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetPMOSVddIO2CompensationValue), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetPMOSVddIO2CompensationValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_FLASH_DisableECCNMI), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_DisableECCNMI), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_FLASH_EnableECCNMI), (18 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_EnableECCNMI), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_FLASH_ECCNMI_IsDisabled), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_FLASH_ECCNMI_IsDisabled), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_IncrementHDPLValue), (20 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_IncrementHDPLValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetHDPLValue), (14 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetHDPLValue), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_EPOCHSelection), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_EPOCHSelection), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetEPOCHSelection), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetEPOCHSelection), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_SetOBKHDPL), (28 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_SetOBKHDPL), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetOBKHDPL), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetOBKHDPL), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_OpenAccessPort), (20 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_OpenAccessPort), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_OpenDebug), (20 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_OpenDebug), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_ConfigDebugLevel), (58 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ConfigDebugLevel), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetDebugLevel), (16 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetDebugLevel), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_LockDebugConfig), (20 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_LockDebugConfig), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_ConfigDebugSecurity), (30 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_ConfigDebugSecurity), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetDebugSecurity), (14 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetDebugSecurity), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_Lock), (22 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_Lock), (8 bytes). + Removing stm32h5xx_hal.o(.text.HAL_SBS_GetLock), (52 bytes). + Removing stm32h5xx_hal.o(.ARM.exidx.text.HAL_SBS_GetLock), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text), (0 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_SetConfigLine), (416 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_SetConfigLine), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetConfigLine), (334 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLine), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_ClearConfigLine), (270 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearConfigLine), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_RegisterCallback), (90 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_RegisterCallback), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetHandle), (42 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetHandle), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_IRQHandler), (146 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetPending), (98 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetPending), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_ClearPending), (84 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ClearPending), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_GenerateSWI), (54 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GenerateSWI), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_ConfigLineAttributes), (112 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_ConfigLineAttributes), (8 bytes). + Removing stm32h5xx_hal_exti.o(.text.HAL_EXTI_GetConfigLineAttributes), (110 bytes). + Removing stm32h5xx_hal_exti.o(.ARM.exidx.text.HAL_EXTI_GetConfigLineAttributes), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text), (0 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Init), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_MspInit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspInit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_AdvFeatureConfig), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_SetConfig), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_CheckIdleState), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_Init), (170 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_Init), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_LIN_Init), (228 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_Init), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_Init), (220 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_Init), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_DeInit), (124 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DeInit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_MspDeInit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit), (340 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_WaitOnFlagUntilTimeout), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Receive), (466 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_IT), (332 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT_FIFOEN), (206 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_16BIT_FIFOEN), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT_FIFOEN), (196 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_8BIT_FIFOEN), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_TxISR_16BIT), (152 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_16BIT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_TxISR_8BIT), (142 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_TxISR_8BIT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_IT), (206 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_Start_Receive_IT), (546 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Transmit_DMA), (420 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Transmit_DMA), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMATransmitCplt), (82 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATransmitCplt), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMATxHalfCplt), (22 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxHalfCplt), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMAError), (128 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAError), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Receive_DMA), (178 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Receive_DMA), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_Start_Receive_DMA), (472 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_Start_Receive_DMA), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_DMAPause), (296 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAPause), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_DMAResume), (224 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAResume), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_DMAStop), (288 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DMAStop), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_EndTxTransfer), (92 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndTxTransfer), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndRxTransfer), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Abort), (402 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit), (218 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive), (278 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_Abort_IT), (482 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_Abort_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMATxAbortCallback), (132 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxAbortCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMARxAbortCallback), (114 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxAbortCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmit_IT), (232 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmit_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMATxOnlyAbortCallback), (64 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMATxOnlyAbortCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortTransmitCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortTransmitCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceive_IT), (306 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceive_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMARxOnlyAbortCallback), (62 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxOnlyAbortCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_AbortReceiveCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_AbortReceiveCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_IRQHandler), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAAbortOnError), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ErrorCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UARTEx_RxEventCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_EndTransmit_IT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_TxHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_TxHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_RxCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_RxHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_RxHalfCpltCallback), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_ReceiverTimeout_Config), (68 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_ReceiverTimeout_Config), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_EnableReceiverTimeout), (158 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_EnableReceiverTimeout), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_DisableReceiverTimeout), (158 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_DisableReceiverTimeout), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_EnableMuteMode), (114 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnableMuteMode), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_DisableMuteMode), (114 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_DisableMuteMode), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_MultiProcessor_EnterMuteMode), (20 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_MultiProcessor_EnterMuteMode), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_EnableTransmitter), (158 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableTransmitter), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_HalfDuplex_EnableReceiver), (158 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_HalfDuplex_EnableReceiver), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_LIN_SendBreak), (94 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_LIN_SendBreak), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_GetState), (30 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetState), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.HAL_UART_GetError), (14 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.HAL_UART_GetError), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT_FIFOEN), (794 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_16BIT_FIFOEN), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT_FIFOEN), (790 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_8BIT_FIFOEN), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_RxISR_16BIT), (406 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_16BIT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_RxISR_8BIT), (402 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_RxISR_8BIT), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMAReceiveCplt), (260 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMAReceiveCplt), (8 bytes). + Removing stm32h5xx_hal_uart.o(.text.UART_DMARxHalfCplt), (110 bytes). + Removing stm32h5xx_hal_uart.o(.ARM.exidx.text.UART_DMARxHalfCplt), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text), (0 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_RS485Ex_Init), (208 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_RS485Ex_Init), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_WakeupCallback), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_RxFifoFullCallback), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_TxFifoEmptyCallback), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_MultiProcessorEx_AddressLength_Set), (94 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_MultiProcessorEx_AddressLength_Set), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_StopModeWakeUpSourceConfig), (200 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_StopModeWakeUpSourceConfig), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.UARTEx_Wakeup_AddressConfig), (58 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.UARTEx_Wakeup_AddressConfig), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_EnableStopMode), (104 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_EnableStopMode), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableStopMode), (104 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_DisableStopMode), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_EnableFifoMode), (134 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_EnableFifoMode), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.UARTEx_SetNbDataToProcess), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_DisableFifoMode), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_SetTxFifoThreshold), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_SetRxFifoThreshold), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle), (588 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_IT), (196 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_IT), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_ReceiveToIdle_DMA), (176 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_ReceiveToIdle_DMA), (8 bytes). + Removing stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_GetRxEventType), (12 bytes). + Removing stm32h5xx_hal_uart_ex.o(.ARM.exidx.text.HAL_UARTEx_GetRxEventType), (8 bytes). + Removing system_stm32h5xx.o(.text), (0 bytes). + Removing system_stm32h5xx.o(.ARM.exidx.text.SystemInit), (8 bytes). + Removing system_stm32h5xx.o(.text.SystemCoreClockUpdate), (632 bytes). + Removing system_stm32h5xx.o(.ARM.exidx.text.SystemCoreClockUpdate), (8 bytes). + Removing tx_initialize_high_level.o(.text), (0 bytes). + Removing tx_initialize_high_level.o(.ARM.exidx.text._tx_initialize_high_level), (8 bytes). + Removing tx_initialize_kernel_enter.o(.text), (0 bytes). + Removing tx_initialize_kernel_enter.o(.ARM.exidx.text._tx_initialize_kernel_enter), (8 bytes). + Removing tx_initialize_kernel_setup.o(.text), (0 bytes). + Removing tx_initialize_kernel_setup.o(.text._tx_initialize_kernel_setup), (58 bytes). + Removing tx_initialize_kernel_setup.o(.ARM.exidx.text._tx_initialize_kernel_setup), (8 bytes). + Removing tx_thread_context_restore.o(.text), (2 bytes). + Removing tx_thread_context_save.o(.text), (2 bytes). + Removing tx_thread_interrupt_control.o(.text), (12 bytes). + Removing tx_thread_interrupt_disable.o(.text), (8 bytes). + Removing tx_thread_interrupt_restore.o(.text), (6 bytes). + Removing tx_thread_system_return.o(.text), (32 bytes). + Removing tx_thread_stack_error_handler.o(.text), (0 bytes). + Removing tx_thread_stack_error_handler.o(.text._tx_thread_stack_error_handler), (66 bytes). + Removing tx_thread_stack_error_handler.o(.ARM.exidx.text._tx_thread_stack_error_handler), (8 bytes). + Removing tx_thread_stack_error_notify.o(.text), (0 bytes). + Removing tx_thread_stack_error_notify.o(.text._tx_thread_stack_error_notify), (48 bytes). + Removing tx_thread_stack_error_notify.o(.ARM.exidx.text._tx_thread_stack_error_notify), (8 bytes). + Removing tx_thread_system_resume.o(.text), (0 bytes). + Removing tx_thread_system_resume.o(.ARM.exidx.text._tx_thread_system_resume), (8 bytes). + Removing tx_block_allocate.o(.text), (0 bytes). + Removing tx_block_allocate.o(.text._tx_block_allocate), (356 bytes). + Removing tx_block_allocate.o(.ARM.exidx.text._tx_block_allocate), (8 bytes). + Removing tx_block_pool_cleanup.o(.text), (0 bytes). + Removing tx_block_pool_cleanup.o(.text._tx_block_pool_cleanup), (268 bytes). + Removing tx_block_pool_cleanup.o(.ARM.exidx.text._tx_block_pool_cleanup), (8 bytes). + Removing tx_block_pool_create.o(.text), (0 bytes). + Removing tx_block_pool_create.o(.text._tx_block_pool_create), (336 bytes). + Removing tx_block_pool_create.o(.ARM.exidx.text._tx_block_pool_create), (8 bytes). + Removing tx_block_pool_delete.o(.text), (0 bytes). + Removing tx_block_pool_delete.o(.text._tx_block_pool_delete), (302 bytes). + Removing tx_block_pool_delete.o(.ARM.exidx.text._tx_block_pool_delete), (8 bytes). + Removing tx_block_pool_info_get.o(.text), (0 bytes). + Removing tx_block_pool_info_get.o(.text._tx_block_pool_info_get), (150 bytes). + Removing tx_block_pool_info_get.o(.ARM.exidx.text._tx_block_pool_info_get), (8 bytes). + Removing tx_block_pool_initialize.o(.text), (0 bytes). + Removing tx_block_pool_prioritize.o(.text), (0 bytes). + Removing tx_block_pool_prioritize.o(.text._tx_block_pool_prioritize), (386 bytes). + Removing tx_block_pool_prioritize.o(.ARM.exidx.text._tx_block_pool_prioritize), (8 bytes). + Removing tx_block_release.o(.text), (0 bytes). + Removing tx_block_release.o(.text._tx_block_release), (214 bytes). + Removing tx_block_release.o(.ARM.exidx.text._tx_block_release), (8 bytes). + Removing tx_byte_allocate.o(.text), (0 bytes). + Removing tx_byte_allocate.o(.text._tx_byte_allocate), (406 bytes). + Removing tx_byte_allocate.o(.ARM.exidx.text._tx_byte_allocate), (8 bytes). + Removing tx_byte_pool_cleanup.o(.text), (0 bytes). + Removing tx_byte_pool_cleanup.o(.text._tx_byte_pool_cleanup), (268 bytes). + Removing tx_byte_pool_cleanup.o(.ARM.exidx.text._tx_byte_pool_cleanup), (8 bytes). + Removing tx_byte_pool_create.o(.text), (0 bytes). + Removing tx_byte_pool_create.o(.ARM.exidx.text._tx_byte_pool_create), (8 bytes). + Removing tx_byte_pool_delete.o(.text), (0 bytes). + Removing tx_byte_pool_delete.o(.text._tx_byte_pool_delete), (302 bytes). + Removing tx_byte_pool_delete.o(.ARM.exidx.text._tx_byte_pool_delete), (8 bytes). + Removing tx_byte_pool_info_get.o(.text), (0 bytes). + Removing tx_byte_pool_info_get.o(.text._tx_byte_pool_info_get), (150 bytes). + Removing tx_byte_pool_info_get.o(.ARM.exidx.text._tx_byte_pool_info_get), (8 bytes). + Removing tx_byte_pool_initialize.o(.text), (0 bytes). + Removing tx_byte_pool_prioritize.o(.text), (0 bytes). + Removing tx_byte_pool_prioritize.o(.text._tx_byte_pool_prioritize), (386 bytes). + Removing tx_byte_pool_prioritize.o(.ARM.exidx.text._tx_byte_pool_prioritize), (8 bytes). + Removing tx_byte_pool_search.o(.text), (0 bytes). + Removing tx_byte_pool_search.o(.text._tx_byte_pool_search), (572 bytes). + Removing tx_byte_pool_search.o(.ARM.exidx.text._tx_byte_pool_search), (8 bytes). + Removing tx_byte_release.o(.text), (0 bytes). + Removing tx_byte_release.o(.text._tx_byte_release), (614 bytes). + Removing tx_byte_release.o(.ARM.exidx.text._tx_byte_release), (8 bytes). + Removing tx_event_flags_cleanup.o(.text), (0 bytes). + Removing tx_event_flags_cleanup.o(.text._tx_event_flags_cleanup), (292 bytes). + Removing tx_event_flags_cleanup.o(.ARM.exidx.text._tx_event_flags_cleanup), (8 bytes). + Removing tx_event_flags_create.o(.text), (0 bytes). + Removing tx_event_flags_create.o(.text._tx_event_flags_create), (160 bytes). + Removing tx_event_flags_create.o(.ARM.exidx.text._tx_event_flags_create), (8 bytes). + Removing tx_event_flags_delete.o(.text), (0 bytes). + Removing tx_event_flags_delete.o(.text._tx_event_flags_delete), (302 bytes). + Removing tx_event_flags_delete.o(.ARM.exidx.text._tx_event_flags_delete), (8 bytes). + Removing tx_event_flags_get.o(.text), (0 bytes). + Removing tx_event_flags_get.o(.text._tx_event_flags_get), (484 bytes). + Removing tx_event_flags_get.o(.ARM.exidx.text._tx_event_flags_get), (8 bytes). + Removing tx_event_flags_info_get.o(.text), (0 bytes). + Removing tx_event_flags_info_get.o(.text._tx_event_flags_info_get), (134 bytes). + Removing tx_event_flags_info_get.o(.ARM.exidx.text._tx_event_flags_info_get), (8 bytes). + Removing tx_event_flags_initialize.o(.text), (0 bytes). + Removing tx_event_flags_set.o(.text), (0 bytes). + Removing tx_event_flags_set.o(.text._tx_event_flags_set), (962 bytes). + Removing tx_event_flags_set.o(.ARM.exidx.text._tx_event_flags_set), (8 bytes). + Removing tx_event_flags_set_notify.o(.text), (0 bytes). + Removing tx_event_flags_set_notify.o(.text._tx_event_flags_set_notify), (12 bytes). + Removing tx_event_flags_set_notify.o(.ARM.exidx.text._tx_event_flags_set_notify), (8 bytes). + Removing tx_mutex_cleanup.o(.text), (0 bytes). + Removing tx_mutex_cleanup.o(.text._tx_mutex_cleanup), (268 bytes). + Removing tx_mutex_cleanup.o(.ARM.exidx.text._tx_mutex_cleanup), (8 bytes). + Removing tx_mutex_cleanup.o(.text._tx_mutex_thread_release), (138 bytes). + Removing tx_mutex_cleanup.o(.ARM.exidx.text._tx_mutex_thread_release), (8 bytes). + Removing tx_mutex_create.o(.text), (0 bytes). + Removing tx_mutex_create.o(.text._tx_mutex_create), (186 bytes). + Removing tx_mutex_create.o(.ARM.exidx.text._tx_mutex_create), (8 bytes). + Removing tx_mutex_delete.o(.text), (0 bytes). + Removing tx_mutex_delete.o(.text._tx_mutex_delete), (354 bytes). + Removing tx_mutex_delete.o(.ARM.exidx.text._tx_mutex_delete), (8 bytes). + Removing tx_mutex_get.o(.text), (0 bytes). + Removing tx_mutex_get.o(.text._tx_mutex_get), (542 bytes). + Removing tx_mutex_get.o(.ARM.exidx.text._tx_mutex_get), (8 bytes). + Removing tx_mutex_info_get.o(.text), (0 bytes). + Removing tx_mutex_info_get.o(.text._tx_mutex_info_get), (150 bytes). + Removing tx_mutex_info_get.o(.ARM.exidx.text._tx_mutex_info_get), (8 bytes). + Removing tx_mutex_initialize.o(.text), (0 bytes). + Removing tx_mutex_prioritize.o(.text), (0 bytes). + Removing tx_mutex_prioritize.o(.text._tx_mutex_prioritize), (386 bytes). + Removing tx_mutex_prioritize.o(.ARM.exidx.text._tx_mutex_prioritize), (8 bytes). + Removing tx_mutex_priority_change.o(.text), (0 bytes). + Removing tx_mutex_priority_change.o(.text._tx_mutex_priority_change), (426 bytes). + Removing tx_mutex_priority_change.o(.ARM.exidx.text._tx_mutex_priority_change), (8 bytes). + Removing tx_mutex_put.o(.text), (0 bytes). + Removing tx_mutex_put.o(.text._tx_mutex_put), (1050 bytes). + Removing tx_mutex_put.o(.ARM.exidx.text._tx_mutex_put), (8 bytes). + Removing tx_queue_cleanup.o(.text), (0 bytes). + Removing tx_queue_cleanup.o(.text._tx_queue_cleanup), (288 bytes). + Removing tx_queue_cleanup.o(.ARM.exidx.text._tx_queue_cleanup), (8 bytes). + Removing tx_queue_create.o(.text), (0 bytes). + Removing tx_queue_create.o(.text._tx_queue_create), (238 bytes). + Removing tx_queue_create.o(.ARM.exidx.text._tx_queue_create), (8 bytes). + Removing tx_queue_delete.o(.text), (0 bytes). + Removing tx_queue_delete.o(.text._tx_queue_delete), (302 bytes). + Removing tx_queue_delete.o(.ARM.exidx.text._tx_queue_delete), (8 bytes). + Removing tx_queue_flush.o(.text), (0 bytes). + Removing tx_queue_flush.o(.text._tx_queue_flush), (272 bytes). + Removing tx_queue_flush.o(.ARM.exidx.text._tx_queue_flush), (8 bytes). + Removing tx_queue_front_send.o(.text), (0 bytes). + Removing tx_queue_front_send.o(.text._tx_queue_front_send), (640 bytes). + Removing tx_queue_front_send.o(.ARM.exidx.text._tx_queue_front_send), (8 bytes). + Removing tx_queue_info_get.o(.text), (0 bytes). + Removing tx_queue_info_get.o(.text._tx_queue_info_get), (150 bytes). + Removing tx_queue_info_get.o(.ARM.exidx.text._tx_queue_info_get), (8 bytes). + Removing tx_queue_initialize.o(.text), (0 bytes). + Removing tx_queue_prioritize.o(.text), (0 bytes). + Removing tx_queue_prioritize.o(.text._tx_queue_prioritize), (386 bytes). + Removing tx_queue_prioritize.o(.ARM.exidx.text._tx_queue_prioritize), (8 bytes). + Removing tx_queue_receive.o(.text), (0 bytes). + Removing tx_queue_receive.o(.text._tx_queue_receive), (950 bytes). + Removing tx_queue_receive.o(.ARM.exidx.text._tx_queue_receive), (8 bytes). + Removing tx_queue_send.o(.text), (0 bytes). + Removing tx_queue_send.o(.text._tx_queue_send), (620 bytes). + Removing tx_queue_send.o(.ARM.exidx.text._tx_queue_send), (8 bytes). + Removing tx_queue_send_notify.o(.text), (0 bytes). + Removing tx_queue_send_notify.o(.text._tx_queue_send_notify), (12 bytes). + Removing tx_queue_send_notify.o(.ARM.exidx.text._tx_queue_send_notify), (8 bytes). + Removing tx_semaphore_ceiling_put.o(.text), (0 bytes). + Removing tx_semaphore_ceiling_put.o(.text._tx_semaphore_ceiling_put), (208 bytes). + Removing tx_semaphore_ceiling_put.o(.ARM.exidx.text._tx_semaphore_ceiling_put), (8 bytes). + Removing tx_semaphore_cleanup.o(.text), (0 bytes). + Removing tx_semaphore_cleanup.o(.text._tx_semaphore_cleanup), (268 bytes). + Removing tx_semaphore_cleanup.o(.ARM.exidx.text._tx_semaphore_cleanup), (8 bytes). + Removing tx_semaphore_create.o(.text), (0 bytes). + Removing tx_semaphore_create.o(.text._tx_semaphore_create), (176 bytes). + Removing tx_semaphore_create.o(.ARM.exidx.text._tx_semaphore_create), (8 bytes). + Removing tx_semaphore_delete.o(.text), (0 bytes). + Removing tx_semaphore_delete.o(.text._tx_semaphore_delete), (302 bytes). + Removing tx_semaphore_delete.o(.ARM.exidx.text._tx_semaphore_delete), (8 bytes). + Removing tx_semaphore_get.o(.text), (0 bytes). + Removing tx_semaphore_get.o(.text._tx_semaphore_get), (290 bytes). + Removing tx_semaphore_get.o(.ARM.exidx.text._tx_semaphore_get), (8 bytes). + Removing tx_semaphore_info_get.o(.text), (0 bytes). + Removing tx_semaphore_info_get.o(.text._tx_semaphore_info_get), (130 bytes). + Removing tx_semaphore_info_get.o(.ARM.exidx.text._tx_semaphore_info_get), (8 bytes). + Removing tx_semaphore_initialize.o(.text), (0 bytes). + Removing tx_semaphore_prioritize.o(.text), (0 bytes). + Removing tx_semaphore_prioritize.o(.text._tx_semaphore_prioritize), (386 bytes). + Removing tx_semaphore_prioritize.o(.ARM.exidx.text._tx_semaphore_prioritize), (8 bytes). + Removing tx_semaphore_put.o(.text), (0 bytes). + Removing tx_semaphore_put.o(.text._tx_semaphore_put), (168 bytes). + Removing tx_semaphore_put.o(.ARM.exidx.text._tx_semaphore_put), (8 bytes). + Removing tx_semaphore_put_notify.o(.text), (0 bytes). + Removing tx_semaphore_put_notify.o(.text._tx_semaphore_put_notify), (12 bytes). + Removing tx_semaphore_put_notify.o(.ARM.exidx.text._tx_semaphore_put_notify), (8 bytes). + Removing tx_thread_create.o(.text), (0 bytes). + Removing tx_thread_create.o(.ARM.exidx.text._tx_thread_create), (8 bytes). + Removing tx_thread_delete.o(.text), (0 bytes). + Removing tx_thread_delete.o(.text._tx_thread_delete), (192 bytes). + Removing tx_thread_delete.o(.ARM.exidx.text._tx_thread_delete), (8 bytes). + Removing tx_thread_entry_exit_notify.o(.text), (0 bytes). + Removing tx_thread_entry_exit_notify.o(.text._tx_thread_entry_exit_notify), (12 bytes). + Removing tx_thread_entry_exit_notify.o(.ARM.exidx.text._tx_thread_entry_exit_notify), (8 bytes). + Removing tx_thread_identify.o(.text), (0 bytes). + Removing tx_thread_identify.o(.text._tx_thread_identify), (46 bytes). + Removing tx_thread_identify.o(.ARM.exidx.text._tx_thread_identify), (8 bytes). + Removing tx_thread_info_get.o(.text), (0 bytes). + Removing tx_thread_info_get.o(.text._tx_thread_info_get), (196 bytes). + Removing tx_thread_info_get.o(.ARM.exidx.text._tx_thread_info_get), (8 bytes). + Removing tx_thread_initialize.o(.text), (0 bytes). + Removing tx_thread_initialize.o(.ARM.exidx.text._tx_thread_initialize), (8 bytes). + Removing tx_thread_initialize.o(.data._tx_version_id), (99 bytes). + Removing tx_thread_initialize.o(.rodata._tx_thread_special_string), (87 bytes). + Removing tx_thread_initialize.o(.bss._tx_thread_application_stack_error_handler), (4 bytes). + Removing tx_thread_preemption_change.o(.text), (0 bytes). + Removing tx_thread_preemption_change.o(.text._tx_thread_preemption_change), (270 bytes). + Removing tx_thread_preemption_change.o(.ARM.exidx.text._tx_thread_preemption_change), (8 bytes). + Removing tx_thread_priority_change.o(.text), (0 bytes). + Removing tx_thread_priority_change.o(.text._tx_thread_priority_change), (406 bytes). + Removing tx_thread_priority_change.o(.ARM.exidx.text._tx_thread_priority_change), (8 bytes). + Removing tx_thread_relinquish.o(.text), (0 bytes). + Removing tx_thread_relinquish.o(.text._tx_thread_relinquish), (230 bytes). + Removing tx_thread_relinquish.o(.ARM.exidx.text._tx_thread_relinquish), (8 bytes). + Removing tx_thread_reset.o(.text), (0 bytes). + Removing tx_thread_reset.o(.text._tx_thread_reset), (172 bytes). + Removing tx_thread_reset.o(.ARM.exidx.text._tx_thread_reset), (8 bytes). + Removing tx_thread_resume.o(.text), (0 bytes). + Removing tx_thread_resume.o(.text._tx_thread_resume), (206 bytes). + Removing tx_thread_resume.o(.ARM.exidx.text._tx_thread_resume), (8 bytes). + Removing tx_thread_shell_entry.o(.text), (0 bytes). + Removing tx_thread_shell_entry.o(.ARM.exidx.text._tx_thread_shell_entry), (8 bytes). + Removing tx_thread_sleep.o(.text), (0 bytes). + Removing tx_thread_sleep.o(.text._tx_thread_sleep), (260 bytes). + Removing tx_thread_sleep.o(.ARM.exidx.text._tx_thread_sleep), (8 bytes). + Removing tx_thread_stack_analyze.o(.text), (0 bytes). + Removing tx_thread_stack_analyze.o(.text._tx_thread_stack_analyze), (276 bytes). + Removing tx_thread_stack_analyze.o(.ARM.exidx.text._tx_thread_stack_analyze), (8 bytes). + Removing tx_thread_suspend.o(.text), (0 bytes). + Removing tx_thread_suspend.o(.text._tx_thread_suspend), (258 bytes). + Removing tx_thread_suspend.o(.ARM.exidx.text._tx_thread_suspend), (8 bytes). + Removing tx_thread_system_preempt_check.o(.text), (0 bytes). + Removing tx_thread_system_preempt_check.o(.ARM.exidx.text._tx_thread_system_preempt_check), (8 bytes). + Removing tx_thread_system_suspend.o(.text), (0 bytes). + Removing tx_thread_system_suspend.o(.ARM.exidx.text._tx_thread_system_suspend), (8 bytes). + Removing tx_thread_terminate.o(.text), (0 bytes). + Removing tx_thread_terminate.o(.text._tx_thread_terminate), (704 bytes). + Removing tx_thread_terminate.o(.ARM.exidx.text._tx_thread_terminate), (8 bytes). + Removing tx_thread_time_slice.o(.text), (0 bytes). + Removing tx_thread_time_slice.o(.ARM.exidx.text._tx_thread_time_slice), (8 bytes). + Removing tx_thread_time_slice_change.o(.text), (0 bytes). + Removing tx_thread_time_slice_change.o(.text._tx_thread_time_slice_change), (96 bytes). + Removing tx_thread_time_slice_change.o(.ARM.exidx.text._tx_thread_time_slice_change), (8 bytes). + Removing tx_thread_timeout.o(.text), (0 bytes). + Removing tx_thread_timeout.o(.ARM.exidx.text._tx_thread_timeout), (8 bytes). + Removing tx_thread_wait_abort.o(.text), (0 bytes). + Removing tx_thread_wait_abort.o(.text._tx_thread_wait_abort), (280 bytes). + Removing tx_thread_wait_abort.o(.ARM.exidx.text._tx_thread_wait_abort), (8 bytes). + Removing tx_time_get.o(.text), (0 bytes). + Removing tx_time_get.o(.text._tx_time_get), (46 bytes). + Removing tx_time_get.o(.ARM.exidx.text._tx_time_get), (8 bytes). + Removing tx_time_set.o(.text), (0 bytes). + Removing tx_time_set.o(.text._tx_time_set), (46 bytes). + Removing tx_time_set.o(.ARM.exidx.text._tx_time_set), (8 bytes). + Removing txe_block_allocate.o(.text), (0 bytes). + Removing txe_block_allocate.o(.text._txe_block_allocate), (168 bytes). + Removing txe_block_allocate.o(.ARM.exidx.text._txe_block_allocate), (8 bytes). + Removing txe_block_pool_create.o(.text), (0 bytes). + Removing txe_block_pool_create.o(.text._txe_block_pool_create), (398 bytes). + Removing txe_block_pool_create.o(.ARM.exidx.text._txe_block_pool_create), (8 bytes). + Removing txe_block_pool_delete.o(.text), (0 bytes). + Removing txe_block_pool_delete.o(.text._txe_block_pool_delete), (138 bytes). + Removing txe_block_pool_delete.o(.ARM.exidx.text._txe_block_pool_delete), (8 bytes). + Removing txe_block_pool_info_get.o(.text), (0 bytes). + Removing txe_block_pool_info_get.o(.text._txe_block_pool_info_get), (106 bytes). + Removing txe_block_pool_info_get.o(.ARM.exidx.text._txe_block_pool_info_get), (8 bytes). + Removing txe_block_pool_prioritize.o(.text), (0 bytes). + Removing txe_block_pool_prioritize.o(.text._txe_block_pool_prioritize), (60 bytes). + Removing txe_block_pool_prioritize.o(.ARM.exidx.text._txe_block_pool_prioritize), (8 bytes). + Removing txe_block_release.o(.text), (0 bytes). + Removing txe_block_release.o(.text._txe_block_release), (98 bytes). + Removing txe_block_release.o(.ARM.exidx.text._txe_block_release), (8 bytes). + Removing txe_byte_allocate.o(.text), (0 bytes). + Removing txe_byte_allocate.o(.text._txe_byte_allocate), (282 bytes). + Removing txe_byte_allocate.o(.ARM.exidx.text._txe_byte_allocate), (8 bytes). + Removing txe_byte_pool_create.o(.text), (0 bytes). + Removing txe_byte_pool_create.o(.ARM.exidx.text._txe_byte_pool_create), (8 bytes). + Removing txe_byte_pool_delete.o(.text), (0 bytes). + Removing txe_byte_pool_delete.o(.text._txe_byte_pool_delete), (138 bytes). + Removing txe_byte_pool_delete.o(.ARM.exidx.text._txe_byte_pool_delete), (8 bytes). + Removing txe_byte_pool_info_get.o(.text), (0 bytes). + Removing txe_byte_pool_info_get.o(.text._txe_byte_pool_info_get), (106 bytes). + Removing txe_byte_pool_info_get.o(.ARM.exidx.text._txe_byte_pool_info_get), (8 bytes). + Removing txe_byte_pool_prioritize.o(.text), (0 bytes). + Removing txe_byte_pool_prioritize.o(.text._txe_byte_pool_prioritize), (60 bytes). + Removing txe_byte_pool_prioritize.o(.ARM.exidx.text._txe_byte_pool_prioritize), (8 bytes). + Removing txe_byte_release.o(.text), (0 bytes). + Removing txe_byte_release.o(.text._txe_byte_release), (142 bytes). + Removing txe_byte_release.o(.ARM.exidx.text._txe_byte_release), (8 bytes). + Removing txe_event_flags_create.o(.text), (0 bytes). + Removing txe_event_flags_create.o(.text._txe_event_flags_create), (332 bytes). + Removing txe_event_flags_create.o(.ARM.exidx.text._txe_event_flags_create), (8 bytes). + Removing txe_event_flags_delete.o(.text), (0 bytes). + Removing txe_event_flags_delete.o(.text._txe_event_flags_delete), (138 bytes). + Removing txe_event_flags_delete.o(.ARM.exidx.text._txe_event_flags_delete), (8 bytes). + Removing txe_event_flags_get.o(.text), (0 bytes). + Removing txe_event_flags_get.o(.text._txe_event_flags_get), (208 bytes). + Removing txe_event_flags_get.o(.ARM.exidx.text._txe_event_flags_get), (8 bytes). + Removing txe_event_flags_info_get.o(.text), (0 bytes). + Removing txe_event_flags_info_get.o(.text._txe_event_flags_info_get), (96 bytes). + Removing txe_event_flags_info_get.o(.ARM.exidx.text._txe_event_flags_info_get), (8 bytes). + Removing txe_event_flags_set.o(.text), (0 bytes). + Removing txe_event_flags_set.o(.text._txe_event_flags_set), (102 bytes). + Removing txe_event_flags_set.o(.ARM.exidx.text._txe_event_flags_set), (8 bytes). + Removing txe_event_flags_set_notify.o(.text), (0 bytes). + Removing txe_event_flags_set_notify.o(.text._txe_event_flags_set_notify), (64 bytes). + Removing txe_event_flags_set_notify.o(.ARM.exidx.text._txe_event_flags_set_notify), (8 bytes). + Removing txe_mutex_create.o(.text), (0 bytes). + Removing txe_mutex_create.o(.text._txe_mutex_create), (366 bytes). + Removing txe_mutex_create.o(.ARM.exidx.text._txe_mutex_create), (8 bytes). + Removing txe_mutex_delete.o(.text), (0 bytes). + Removing txe_mutex_delete.o(.text._txe_mutex_delete), (138 bytes). + Removing txe_mutex_delete.o(.ARM.exidx.text._txe_mutex_delete), (8 bytes). + Removing txe_mutex_get.o(.text), (0 bytes). + Removing txe_mutex_get.o(.text._txe_mutex_get), (220 bytes). + Removing txe_mutex_get.o(.ARM.exidx.text._txe_mutex_get), (8 bytes). + Removing txe_mutex_info_get.o(.text), (0 bytes). + Removing txe_mutex_info_get.o(.text._txe_mutex_info_get), (106 bytes). + Removing txe_mutex_info_get.o(.ARM.exidx.text._txe_mutex_info_get), (8 bytes). + Removing txe_mutex_prioritize.o(.text), (0 bytes). + Removing txe_mutex_prioritize.o(.text._txe_mutex_prioritize), (60 bytes). + Removing txe_mutex_prioritize.o(.ARM.exidx.text._txe_mutex_prioritize), (8 bytes). + Removing txe_mutex_put.o(.text), (0 bytes). + Removing txe_mutex_put.o(.text._txe_mutex_put), (134 bytes). + Removing txe_mutex_put.o(.ARM.exidx.text._txe_mutex_put), (8 bytes). + Removing txe_queue_create.o(.text), (0 bytes). + Removing txe_queue_create.o(.text._txe_queue_create), (420 bytes). + Removing txe_queue_create.o(.ARM.exidx.text._txe_queue_create), (8 bytes). + Removing txe_queue_delete.o(.text), (0 bytes). + Removing txe_queue_delete.o(.text._txe_queue_delete), (138 bytes). + Removing txe_queue_delete.o(.ARM.exidx.text._txe_queue_delete), (8 bytes). + Removing txe_queue_flush.o(.text), (0 bytes). + Removing txe_queue_flush.o(.text._txe_queue_flush), (60 bytes). + Removing txe_queue_flush.o(.ARM.exidx.text._txe_queue_flush), (8 bytes). + Removing txe_queue_front_send.o(.text), (0 bytes). + Removing txe_queue_front_send.o(.text._txe_queue_front_send), (168 bytes). + Removing txe_queue_front_send.o(.ARM.exidx.text._txe_queue_front_send), (8 bytes). + Removing txe_queue_info_get.o(.text), (0 bytes). + Removing txe_queue_info_get.o(.text._txe_queue_info_get), (106 bytes). + Removing txe_queue_info_get.o(.ARM.exidx.text._txe_queue_info_get), (8 bytes). + Removing txe_queue_prioritize.o(.text), (0 bytes). + Removing txe_queue_prioritize.o(.text._txe_queue_prioritize), (60 bytes). + Removing txe_queue_prioritize.o(.ARM.exidx.text._txe_queue_prioritize), (8 bytes). + Removing txe_queue_receive.o(.text), (0 bytes). + Removing txe_queue_receive.o(.text._txe_queue_receive), (168 bytes). + Removing txe_queue_receive.o(.ARM.exidx.text._txe_queue_receive), (8 bytes). + Removing txe_queue_send.o(.text), (0 bytes). + Removing txe_queue_send.o(.text._txe_queue_send), (168 bytes). + Removing txe_queue_send.o(.ARM.exidx.text._txe_queue_send), (8 bytes). + Removing txe_queue_send_notify.o(.text), (0 bytes). + Removing txe_queue_send_notify.o(.text._txe_queue_send_notify), (64 bytes). + Removing txe_queue_send_notify.o(.ARM.exidx.text._txe_queue_send_notify), (8 bytes). + Removing txe_semaphore_ceiling_put.o(.text), (0 bytes). + Removing txe_semaphore_ceiling_put.o(.text._txe_semaphore_ceiling_put), (78 bytes). + Removing txe_semaphore_ceiling_put.o(.ARM.exidx.text._txe_semaphore_ceiling_put), (8 bytes). + Removing txe_semaphore_create.o(.text), (0 bytes). + Removing txe_semaphore_create.o(.text._txe_semaphore_create), (344 bytes). + Removing txe_semaphore_create.o(.ARM.exidx.text._txe_semaphore_create), (8 bytes). + Removing txe_semaphore_delete.o(.text), (0 bytes). + Removing txe_semaphore_delete.o(.text._txe_semaphore_delete), (138 bytes). + Removing txe_semaphore_delete.o(.ARM.exidx.text._txe_semaphore_delete), (8 bytes). + Removing txe_semaphore_get.o(.text), (0 bytes). + Removing txe_semaphore_get.o(.text._txe_semaphore_get), (150 bytes). + Removing txe_semaphore_get.o(.ARM.exidx.text._txe_semaphore_get), (8 bytes). + Removing txe_semaphore_info_get.o(.text), (0 bytes). + Removing txe_semaphore_info_get.o(.text._txe_semaphore_info_get), (96 bytes). + Removing txe_semaphore_info_get.o(.ARM.exidx.text._txe_semaphore_info_get), (8 bytes). + Removing txe_semaphore_prioritize.o(.text), (0 bytes). + Removing txe_semaphore_prioritize.o(.text._txe_semaphore_prioritize), (60 bytes). + Removing txe_semaphore_prioritize.o(.ARM.exidx.text._txe_semaphore_prioritize), (8 bytes). + Removing txe_semaphore_put.o(.text), (0 bytes). + Removing txe_semaphore_put.o(.text._txe_semaphore_put), (60 bytes). + Removing txe_semaphore_put.o(.ARM.exidx.text._txe_semaphore_put), (8 bytes). + Removing txe_semaphore_put_notify.o(.text), (0 bytes). + Removing txe_semaphore_put_notify.o(.text._txe_semaphore_put_notify), (64 bytes). + Removing txe_semaphore_put_notify.o(.ARM.exidx.text._txe_semaphore_put_notify), (8 bytes). + Removing txe_thread_create.o(.text), (0 bytes). + Removing txe_thread_create.o(.text._txe_thread_create), (612 bytes). + Removing txe_thread_create.o(.ARM.exidx.text._txe_thread_create), (8 bytes). + Removing txe_thread_delete.o(.text), (0 bytes). + Removing txe_thread_delete.o(.text._txe_thread_delete), (92 bytes). + Removing txe_thread_delete.o(.ARM.exidx.text._txe_thread_delete), (8 bytes). + Removing txe_thread_entry_exit_notify.o(.text), (0 bytes). + Removing txe_thread_entry_exit_notify.o(.text._txe_thread_entry_exit_notify), (64 bytes). + Removing txe_thread_entry_exit_notify.o(.ARM.exidx.text._txe_thread_entry_exit_notify), (8 bytes). + Removing txe_thread_info_get.o(.text), (0 bytes). + Removing txe_thread_info_get.o(.text._txe_thread_info_get), (126 bytes). + Removing txe_thread_info_get.o(.ARM.exidx.text._txe_thread_info_get), (8 bytes). + Removing txe_thread_preemption_change.o(.text), (0 bytes). + Removing txe_thread_preemption_change.o(.text._txe_thread_preemption_change), (136 bytes). + Removing txe_thread_preemption_change.o(.ARM.exidx.text._txe_thread_preemption_change), (8 bytes). + Removing txe_thread_priority_change.o(.text), (0 bytes). + Removing txe_thread_priority_change.o(.text._txe_thread_priority_change), (130 bytes). + Removing txe_thread_priority_change.o(.ARM.exidx.text._txe_thread_priority_change), (8 bytes). + Removing txe_thread_relinquish.o(.text), (0 bytes). + Removing txe_thread_relinquish.o(.text._txe_thread_relinquish), (58 bytes). + Removing txe_thread_relinquish.o(.ARM.exidx.text._txe_thread_relinquish), (8 bytes). + Removing txe_thread_reset.o(.text), (0 bytes). + Removing txe_thread_reset.o(.text._txe_thread_reset), (136 bytes). + Removing txe_thread_reset.o(.ARM.exidx.text._txe_thread_reset), (8 bytes). + Removing txe_thread_resume.o(.text), (0 bytes). + Removing txe_thread_resume.o(.text._txe_thread_resume), (60 bytes). + Removing txe_thread_resume.o(.ARM.exidx.text._txe_thread_resume), (8 bytes). + Removing txe_thread_suspend.o(.text), (0 bytes). + Removing txe_thread_suspend.o(.text._txe_thread_suspend), (60 bytes). + Removing txe_thread_suspend.o(.ARM.exidx.text._txe_thread_suspend), (8 bytes). + Removing txe_thread_terminate.o(.text), (0 bytes). + Removing txe_thread_terminate.o(.text._txe_thread_terminate), (92 bytes). + Removing txe_thread_terminate.o(.ARM.exidx.text._txe_thread_terminate), (8 bytes). + Removing txe_thread_time_slice_change.o(.text), (0 bytes). + Removing txe_thread_time_slice_change.o(.text._txe_thread_time_slice_change), (114 bytes). + Removing txe_thread_time_slice_change.o(.ARM.exidx.text._txe_thread_time_slice_change), (8 bytes). + Removing txe_thread_wait_abort.o(.text), (0 bytes). + Removing txe_thread_wait_abort.o(.text._txe_thread_wait_abort), (60 bytes). + Removing txe_thread_wait_abort.o(.ARM.exidx.text._txe_thread_wait_abort), (8 bytes). + Removing tx_timer_activate.o(.text), (0 bytes). + Removing tx_timer_activate.o(.text._tx_timer_activate), (82 bytes). + Removing tx_timer_activate.o(.ARM.exidx.text._tx_timer_activate), (8 bytes). + Removing tx_timer_change.o(.text), (0 bytes). + Removing tx_timer_change.o(.text._tx_timer_change), (62 bytes). + Removing tx_timer_change.o(.ARM.exidx.text._tx_timer_change), (8 bytes). + Removing tx_timer_create.o(.text), (0 bytes). + Removing tx_timer_create.o(.text._tx_timer_create), (218 bytes). + Removing tx_timer_create.o(.ARM.exidx.text._tx_timer_create), (8 bytes). + Removing tx_timer_deactivate.o(.text), (0 bytes). + Removing tx_timer_deactivate.o(.text._tx_timer_deactivate), (392 bytes). + Removing tx_timer_deactivate.o(.ARM.exidx.text._tx_timer_deactivate), (8 bytes). + Removing tx_timer_delete.o(.text), (0 bytes). + Removing tx_timer_delete.o(.text._tx_timer_delete), (154 bytes). + Removing tx_timer_delete.o(.ARM.exidx.text._tx_timer_delete), (8 bytes). + Removing tx_timer_expiration_process.o(.text), (0 bytes). + Removing tx_timer_expiration_process.o(.ARM.exidx.text._tx_timer_expiration_process), (8 bytes). + Removing tx_timer_info_get.o(.text), (0 bytes). + Removing tx_timer_info_get.o(.text._tx_timer_info_get), (398 bytes). + Removing tx_timer_info_get.o(.ARM.exidx.text._tx_timer_info_get), (8 bytes). + Removing tx_timer_initialize.o(.text), (0 bytes). + Removing tx_timer_initialize.o(.ARM.exidx.text._tx_timer_initialize), (8 bytes). + Removing tx_timer_system_activate.o(.text), (0 bytes). + Removing tx_timer_system_activate.o(.ARM.exidx.text._tx_timer_system_activate), (8 bytes). + Removing tx_timer_system_deactivate.o(.text), (0 bytes). + Removing tx_timer_system_deactivate.o(.ARM.exidx.text._tx_timer_system_deactivate), (8 bytes). + Removing tx_timer_thread_entry.o(.text), (0 bytes). + Removing tx_timer_thread_entry.o(.ARM.exidx.text._tx_timer_thread_entry), (8 bytes). + Removing txe_timer_activate.o(.text), (0 bytes). + Removing txe_timer_activate.o(.text._txe_timer_activate), (60 bytes). + Removing txe_timer_activate.o(.ARM.exidx.text._txe_timer_activate), (8 bytes). + Removing txe_timer_change.o(.text), (0 bytes). + Removing txe_timer_change.o(.text._txe_timer_change), (118 bytes). + Removing txe_timer_change.o(.ARM.exidx.text._txe_timer_change), (8 bytes). + Removing txe_timer_create.o(.text), (0 bytes). + Removing txe_timer_create.o(.text._txe_timer_create), (420 bytes). + Removing txe_timer_create.o(.ARM.exidx.text._txe_timer_create), (8 bytes). + Removing txe_timer_deactivate.o(.text), (0 bytes). + Removing txe_timer_deactivate.o(.text._txe_timer_deactivate), (60 bytes). + Removing txe_timer_deactivate.o(.ARM.exidx.text._txe_timer_deactivate), (8 bytes). + Removing txe_timer_delete.o(.text), (0 bytes). + Removing txe_timer_delete.o(.text._txe_timer_delete), (138 bytes). + Removing txe_timer_delete.o(.ARM.exidx.text._txe_timer_delete), (8 bytes). + Removing txe_timer_info_get.o(.text), (0 bytes). + Removing txe_timer_info_get.o(.text._txe_timer_info_get), (96 bytes). + Removing txe_timer_info_get.o(.ARM.exidx.text._txe_timer_info_get), (8 bytes). + Removing hcble.o(.text), (0 bytes). + Removing hcble.o(.text.HCBle_SendData), (70 bytes). + Removing hcble.o(.ARM.exidx.text.HCBle_SendData), (8 bytes). + Removing hcble.o(.text.HAL_UART_RxCpltCallback), (166 bytes). + Removing hcble.o(.ARM.exidx.text.HAL_UART_RxCpltCallback), (8 bytes). + Removing hcble.o(.bss.rx_index), (2 bytes). + Removing hcble.o(.bss.data_received), (1 bytes). + Removing hcble.o(.bss.HC_Send_Data), (128 bytes). + Removing hcble.o(.bss.rx_data), (1 bytes). + Removing hcble.o(.bss.HC_Recevie), (128 bytes). + +1703 unused section(s) (total 136006 bytes) removed from the image. + +============================================================================== + +Image Symbol Table + + Local Symbols + + Symbol Name Value Ov Type Size Object(Section) + + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit1.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit2.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardinit3.o ABSOLUTE + ../clib/angel/boardlib.s 0x00000000 Number 0 boardshut.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_copy.o ABSOLUTE + ../clib/angel/handlers.s 0x00000000 Number 0 __scatter_zi.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry2.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 __rtentry4.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit.o ABSOLUTE + ../clib/angel/kernel.s 0x00000000 Number 0 rtexit2.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 aeabi_ldiv0_sigfpe.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_div0.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_ctype_table.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_locale_intlibspace.o ABSOLUTE + ../clib/angel/rt.s 0x00000000 Number 0 rt_raise.o ABSOLUTE + ../clib/angel/scatter.s 0x00000000 Number 0 __scatter.o ABSOLUTE + ../clib/angel/startup.s 0x00000000 Number 0 __main.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 sys_stackheap_outer.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 libspace.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 use_no_semi.o ABSOLUTE + ../clib/angel/sys.s 0x00000000 Number 0 indicate_semi.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_exit_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_wrch_hlt.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command.o ABSOLUTE + ../clib/angel/sysapp.c 0x00000000 Number 0 sys_command_hlt.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 argv_veneer.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 _get_argv_nomalloc.o ABSOLUTE + ../clib/armsys.c 0x00000000 Number 0 no_argv.o ABSOLUTE + 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__cpp_initialize__aeabi_ - Undefined Weak Reference + __cxa_finalize - Undefined Weak Reference + __sigvec_lookup - Undefined Weak Reference + _atexit_init - Undefined Weak Reference + _call_atexit_fns - Undefined Weak Reference + _clock_init - Undefined Weak Reference + _fp_trap_init - Undefined Weak Reference + _fp_trap_shutdown - Undefined Weak Reference + _get_lc_collate - Undefined Weak Reference + _get_lc_monetary - Undefined Weak Reference + _get_lc_time - Undefined Weak Reference + _getenv_init - Undefined Weak Reference + _handle_redirection - Undefined Weak Reference + _init_alloc - Undefined Weak Reference + _init_user_alloc - Undefined Weak Reference + _initio - Undefined Weak Reference + _printf_mbtowc - Undefined Weak Reference + _printf_wc - Undefined Weak Reference + _rand_init - Undefined Weak Reference + _signal_finish - Undefined Weak Reference + _signal_init - Undefined Weak Reference + _terminate_alloc - Undefined Weak Reference + _terminate_user_alloc - Undefined Weak Reference + _terminateio - Undefined Weak Reference + __Vectors_Size 0x0000024c Number 0 startup_stm32h563xx.o ABSOLUTE + __Vectors 0x08000000 Data 4 startup_stm32h563xx.o(RESET) + __Vectors_End 0x0800024c Data 0 startup_stm32h563xx.o(RESET) + __main 0x0800024d Thumb Code 8 __main.o(!!!main) + __scatterload 0x08000255 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_rt2 0x08000255 Thumb Code 84 __scatter.o(!!!scatter) + __scatterload_rt2_thumb_only 0x08000255 Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_loop 0x0800025f Thumb Code 0 __scatter.o(!!!scatter) + __scatterload_copy 0x080002b1 Thumb Code 26 __scatter_copy.o(!!handler_copy) + __scatterload_null 0x080002cd Thumb Code 2 __scatter.o(!!handler_null) + __scatterload_zeroinit 0x080002d1 Thumb Code 28 __scatter_zi.o(!!handler_zi) + __rt_lib_init 0x080002ed Thumb Code 0 libinit.o(.ARM.Collect$$libinit$$00000000) + __rt_lib_init_fp_1 0x080002ef Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000001) + 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libinit2.o(.ARM.Collect$$libinit$$00000015) + __rt_lib_init_lc_monetary_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000017) + __rt_lib_init_lc_numeric_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000019) + __rt_lib_init_lc_time_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001B) + __rt_lib_init_preinit_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000006) + __rt_lib_init_rand_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000010) + __rt_lib_init_relocate_pie_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000004) + __rt_lib_init_return 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000035) + __rt_lib_init_signal_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000001F) + __rt_lib_init_stdio_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$00000027) + __rt_lib_init_user_alloc_1 0x080002f3 Thumb Code 0 libinit2.o(.ARM.Collect$$libinit$$0000000E) + __rt_lib_shutdown 0x080002f5 Thumb Code 0 libshutdown.o(.ARM.Collect$$libshutdown$$00000000) + __rt_lib_shutdown_cpp_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000002) + __rt_lib_shutdown_fp_trap_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000007) + __rt_lib_shutdown_heap_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000F) + __rt_lib_shutdown_return 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000010) + __rt_lib_shutdown_signal_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000A) + __rt_lib_shutdown_stdio_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$00000004) + __rt_lib_shutdown_user_alloc_1 0x080002f7 Thumb Code 0 libshutdown2.o(.ARM.Collect$$libshutdown$$0000000C) + __rt_entry 0x080002f9 Thumb Code 0 __rtentry.o(.ARM.Collect$$rtentry$$00000000) + __rt_entry_presh_1 0x080002f9 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000002) + __rt_entry_sh 0x080002f9 Thumb Code 0 __rtentry4.o(.ARM.Collect$$rtentry$$00000004) + __rt_entry_li 0x080002ff Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000A) + __rt_entry_postsh_1 0x080002ff Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$00000009) + __rt_entry_main 0x08000303 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000D) + __rt_entry_postli_1 0x08000303 Thumb Code 0 __rtentry2.o(.ARM.Collect$$rtentry$$0000000C) + __rt_exit 0x0800030b Thumb Code 0 rtexit.o(.ARM.Collect$$rtexit$$00000000) + __rt_exit_ls 0x0800030d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000003) + __rt_exit_prels_1 0x0800030d Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000002) + __rt_exit_exit 0x08000311 Thumb Code 0 rtexit2.o(.ARM.Collect$$rtexit$$00000004) + Reset_Handler 0x08000319 Thumb Code 8 startup_stm32h563xx.o(.text) + SecureFault_Handler 0x0800032b Thumb Code 2 startup_stm32h563xx.o(.text) + SVC_Handler 0x0800032d Thumb Code 2 startup_stm32h563xx.o(.text) + ADC1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + ADC2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + CEC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + CORDIC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + CRS_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + DAC1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + DCACHE1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + DCMI_PSSI_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + DTS_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + ETH_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + ETH_WKUP_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI0_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI10_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI11_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI12_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI13_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI14_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI15_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI7_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI8_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + EXTI9_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FDCAN1_IT0_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FDCAN1_IT1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FDCAN2_IT0_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FDCAN2_IT1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FLASH_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FLASH_S_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FMAC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FMC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + FPU_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel0_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA1_Channel7_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel0_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GPDMA2_Channel7_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + GTZC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + HASH_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C1_ER_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C1_EV_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C2_ER_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C2_EV_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C3_ER_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C3_EV_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C4_ER_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I2C4_EV_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I3C1_ER_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + I3C1_EV_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + ICACHE_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + IWDG_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPTIM6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + LPUART1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + OCTOSPI1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + PVD_AVD_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RAMCFG_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RCC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RCC_S_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RNG_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RTC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + RTC_S_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SAI1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SAI2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SDMMC1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SDMMC2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + SPI6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TAMP_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM12_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM13_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM14_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM15_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM16_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM17_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM1_BRK_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM1_CC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM1_TRG_COM_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM7_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM8_BRK_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM8_CC_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM8_TRG_COM_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + TIM8_UP_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART12_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART4_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART5_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART7_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART8_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UART9_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + UCPD1_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USART10_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USART11_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USART2_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USART3_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USART6_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + USB_DRD_FS_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + WWDG_IRQHandler 0x08000335 Thumb Code 0 startup_stm32h563xx.o(.text) + __user_initial_stackheap 0x08000339 Thumb Code 10 startup_stm32h563xx.o(.text) + _tx_initialize_low_level 0x0800035d Thumb Code 0 tx_initialize_low_level.o(.text) + __tx_BadHandler 0x080003a1 Thumb Code 0 tx_initialize_low_level.o(.text) + __tx_IntHandler 0x080003a5 Thumb Code 0 tx_initialize_low_level.o(.text) + SysTick_Handler 0x080003ad Thumb Code 0 tx_initialize_low_level.o(.text) + __tx_NMIHandler 0x080003b9 Thumb Code 0 tx_initialize_low_level.o(.text) + __tx_DBGHandler 0x080003bd Thumb Code 0 tx_initialize_low_level.o(.text) + _tx_thread_schedule 0x080003d5 Thumb Code 0 tx_thread_schedule.o(.text) + PendSV_Handler 0x08000401 Thumb Code 0 tx_thread_schedule.o(.text) + _tx_vfp_access 0x0800048d Thumb Code 0 tx_thread_schedule.o(.text) + _tx_thread_stack_build 0x080004a5 Thumb Code 0 tx_thread_stack_build.o(.text) + _tx_timer_interrupt 0x080004e5 Thumb Code 0 tx_timer_interrupt.o(.text) + __aeabi_uldivmod 0x0800059d Thumb Code 0 lludivv7m.o(.text) + _ll_udiv 0x0800059d Thumb Code 240 lludivv7m.o(.text) + __aeabi_memset 0x0800068d Thumb Code 16 aeabi_memset.o(.text) + __aeabi_memclr 0x0800069d Thumb Code 0 rt_memclr.o(.text) + __rt_memclr 0x0800069d Thumb Code 0 rt_memclr.o(.text) + _memset 0x080006a1 Thumb Code 64 rt_memclr.o(.text) + __aeabi_memclr4 0x080006e1 Thumb Code 0 rt_memclr_w.o(.text) + __aeabi_memclr8 0x080006e1 Thumb Code 0 rt_memclr_w.o(.text) + __rt_memclr_w 0x080006e1 Thumb Code 0 rt_memclr_w.o(.text) + _memset_w 0x080006e5 Thumb Code 74 rt_memclr_w.o(.text) + __use_two_region_memory 0x0800072f Thumb Code 2 heapauxi.o(.text) + __rt_heap_escrow$2region 0x08000731 Thumb Code 2 heapauxi.o(.text) + __rt_heap_expand$2region 0x08000733 Thumb Code 2 heapauxi.o(.text) + __user_setup_stackheap 0x08000735 Thumb Code 74 sys_stackheap_outer.o(.text) + exit 0x0800077f Thumb Code 18 exit.o(.text) + __user_libspace 0x08000791 Thumb Code 8 libspace.o(.text) + __user_perproc_libspace 0x08000791 Thumb Code 0 libspace.o(.text) + __user_perthread_libspace 0x08000791 Thumb Code 0 libspace.o(.text) + _sys_exit 0x08000799 Thumb Code 8 sys_exit.o(.text) + __I$use$semihosting 0x080007a5 Thumb Code 0 use_no_semi.o(.text) + __use_no_semihosting_swi 0x080007a5 Thumb Code 2 use_no_semi.o(.text) + __semihosting_library_function 0x080007a7 Thumb Code 0 indicate_semi.o(.text) + App_ThreadX_Init 0x080007a9 Thumb Code 14 app_threadx.o(.text.App_ThreadX_Init) + BusFault_Handler 0x080007b9 Thumb Code 4 stm32h5xx_it.o(.text.BusFault_Handler) + DebugMon_Handler 0x080007bd Thumb Code 2 stm32h5xx_it.o(.text.DebugMon_Handler) + Error_Handler 0x080007c1 Thumb Code 6 main.o(.text.Error_Handler) + HAL_DMA_Abort 0x080007c9 Thumb Code 278 stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort) + HAL_DMA_Abort_IT 0x080008e1 Thumb Code 84 stm32h5xx_hal_dma.o(.text.HAL_DMA_Abort_IT) + HAL_GPIO_Init 0x08000935 Thumb Code 746 stm32h5xx_hal_gpio.o(.text.HAL_GPIO_Init) + HAL_GetTick 0x08000c21 Thumb Code 12 stm32h5xx_hal.o(.text.HAL_GetTick) + HAL_IncTick 0x08000c2d Thumb Code 26 stm32h5xx_hal.o(.text.HAL_IncTick) + HAL_Init 0x08000c49 Thumb Code 94 stm32h5xx_hal.o(.text.HAL_Init) + HAL_InitTick 0x08000ca9 Thumb Code 206 stm32h5xx_hal_timebase_tim.o(.text.HAL_InitTick) + HAL_MspInit 0x08000d79 Thumb Code 2 stm32h5xx_hal_msp.o(.text.HAL_MspInit) + HAL_NVIC_EnableIRQ 0x08000d7d Thumb Code 20 stm32h5xx_hal_cortex.o(.text.HAL_NVIC_EnableIRQ) + HAL_NVIC_SetPriority 0x08000d91 Thumb Code 46 stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriority) + HAL_NVIC_SetPriorityGrouping 0x08000dc1 Thumb Code 16 stm32h5xx_hal_cortex.o(.text.HAL_NVIC_SetPriorityGrouping) + HAL_RCCEx_GetPLL1ClockFreq 0x08000dd1 Thumb Code 748 stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL1ClockFreq) + HAL_RCCEx_GetPLL2ClockFreq 0x080010c9 Thumb Code 748 stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL2ClockFreq) + HAL_RCCEx_GetPLL3ClockFreq 0x080013c1 Thumb Code 748 stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPLL3ClockFreq) + HAL_RCCEx_GetPeriphCLKFreq 0x080016b9 Thumb Code 10488 stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_GetPeriphCLKFreq) + HAL_RCCEx_PeriphCLKConfig 0x08003fb1 Thumb Code 6382 stm32h5xx_hal_rcc_ex.o(.text.HAL_RCCEx_PeriphCLKConfig) + HAL_RCC_ClockConfig 0x080058a1 Thumb Code 1172 stm32h5xx_hal_rcc.o(.text.HAL_RCC_ClockConfig) + HAL_RCC_GetClockConfig 0x08005d35 Thumb Code 108 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetClockConfig) + HAL_RCC_GetHCLKFreq 0x08005da1 Thumb Code 52 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetHCLKFreq) + HAL_RCC_GetPCLK1Freq 0x08005dd5 Thumb Code 38 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK1Freq) + HAL_RCC_GetPCLK2Freq 0x08005dfd Thumb Code 38 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK2Freq) + HAL_RCC_GetPCLK3Freq 0x08005e25 Thumb Code 38 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetPCLK3Freq) + HAL_RCC_GetSysClockFreq 0x08005e4d Thumb Code 700 stm32h5xx_hal_rcc.o(.text.HAL_RCC_GetSysClockFreq) + HAL_RCC_OscConfig 0x08006119 Thumb Code 2556 stm32h5xx_hal_rcc.o(.text.HAL_RCC_OscConfig) + HAL_SYSTICK_CLKSourceConfig 0x08006b15 Thumb Code 154 stm32h5xx_hal_cortex.o(.text.HAL_SYSTICK_CLKSourceConfig) + HAL_TIMEx_Break2Callback 0x08006bb1 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_Break2Callback) + HAL_TIMEx_BreakCallback 0x08006bb9 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_BreakCallback) + HAL_TIMEx_CommutCallback 0x08006bc1 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_CommutCallback) + HAL_TIMEx_DirectionChangeCallback 0x08006bc9 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_DirectionChangeCallback) + HAL_TIMEx_EncoderIndexCallback 0x08006bd1 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_EncoderIndexCallback) + HAL_TIMEx_IndexErrorCallback 0x08006bd9 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_IndexErrorCallback) + HAL_TIMEx_TransitionErrorCallback 0x08006be1 Thumb Code 8 stm32h5xx_hal_tim_ex.o(.text.HAL_TIMEx_TransitionErrorCallback) + HAL_TIM_Base_Init 0x08006be9 Thumb Code 168 stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Init) + HAL_TIM_Base_MspInit 0x08006c91 Thumb Code 8 stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_MspInit) + HAL_TIM_Base_Start_IT 0x08006c99 Thumb Code 402 stm32h5xx_hal_tim.o(.text.HAL_TIM_Base_Start_IT) + HAL_TIM_IC_CaptureCallback 0x08006e2d Thumb Code 8 stm32h5xx_hal_tim.o(.text.HAL_TIM_IC_CaptureCallback) + HAL_TIM_IRQHandler 0x08006e35 Thumb Code 768 stm32h5xx_hal_tim.o(.text.HAL_TIM_IRQHandler) + HAL_TIM_OC_DelayElapsedCallback 0x08007135 Thumb Code 8 stm32h5xx_hal_tim.o(.text.HAL_TIM_OC_DelayElapsedCallback) + HAL_TIM_PWM_PulseFinishedCallback 0x0800713d Thumb Code 8 stm32h5xx_hal_tim.o(.text.HAL_TIM_PWM_PulseFinishedCallback) + HAL_TIM_PeriodElapsedCallback 0x08007145 Thumb Code 34 main.o(.text.HAL_TIM_PeriodElapsedCallback) + HAL_TIM_TriggerCallback 0x08007169 Thumb Code 8 stm32h5xx_hal_tim.o(.text.HAL_TIM_TriggerCallback) + HAL_UARTEx_DisableFifoMode 0x08007171 Thumb Code 124 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_DisableFifoMode) + HAL_UARTEx_RxEventCallback 0x080071ed Thumb Code 12 stm32h5xx_hal_uart.o(.text.HAL_UARTEx_RxEventCallback) + HAL_UARTEx_RxFifoFullCallback 0x080071f9 Thumb Code 8 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_RxFifoFullCallback) + HAL_UARTEx_SetRxFifoThreshold 0x08007201 Thumb Code 140 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetRxFifoThreshold) + HAL_UARTEx_SetTxFifoThreshold 0x0800728d Thumb Code 140 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_SetTxFifoThreshold) + HAL_UARTEx_TxFifoEmptyCallback 0x08007319 Thumb Code 8 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_TxFifoEmptyCallback) + HAL_UARTEx_WakeupCallback 0x08007321 Thumb Code 8 stm32h5xx_hal_uart_ex.o(.text.HAL_UARTEx_WakeupCallback) + HAL_UART_ErrorCallback 0x08007329 Thumb Code 8 stm32h5xx_hal_uart.o(.text.HAL_UART_ErrorCallback) + HAL_UART_IRQHandler 0x08007331 Thumb Code 1346 stm32h5xx_hal_uart.o(.text.HAL_UART_IRQHandler) + HAL_UART_Init 0x08007875 Thumb Code 170 stm32h5xx_hal_uart.o(.text.HAL_UART_Init) + HAL_UART_MspInit 0x08007921 Thumb Code 192 usart.o(.text.HAL_UART_MspInit) + HAL_UART_TxCpltCallback 0x080079e1 Thumb Code 8 stm32h5xx_hal_uart.o(.text.HAL_UART_TxCpltCallback) + HardFault_Handler 0x080079e9 Thumb Code 4 stm32h5xx_it.o(.text.HardFault_Handler) + MX_GPIO_Init 0x080079ed Thumb Code 66 gpio.o(.text.MX_GPIO_Init) + MX_ThreadX_Init 0x08007a31 Thumb Code 8 app_threadx.o(.text.MX_ThreadX_Init) + MX_USART1_UART_Init 0x08007a39 Thumb Code 142 usart.o(.text.MX_USART1_UART_Init) + MemManage_Handler 0x08007ac9 Thumb Code 4 stm32h5xx_it.o(.text.MemManage_Handler) + NMI_Handler 0x08007acd Thumb Code 4 stm32h5xx_it.o(.text.NMI_Handler) + SystemClock_Config 0x08007e15 Thumb Code 198 main.o(.text.SystemClock_Config) + SystemInit 0x08007edd Thumb Code 310 system_stm32h5xx.o(.text.SystemInit) + TIM1_UP_IRQHandler 0x08008015 Thumb Code 16 stm32h5xx_it.o(.text.TIM1_UP_IRQHandler) + TIM_Base_SetConfig 0x08008025 Thumb Code 858 stm32h5xx_hal_tim.o(.text.TIM_Base_SetConfig) + UART_AdvFeatureConfig 0x0800840d Thumb Code 328 stm32h5xx_hal_uart.o(.text.UART_AdvFeatureConfig) + UART_CheckIdleState 0x08008555 Thumb Code 326 stm32h5xx_hal_uart.o(.text.UART_CheckIdleState) + UART_SetConfig 0x080087a1 Thumb Code 1048 stm32h5xx_hal_uart.o(.text.UART_SetConfig) + UART_WaitOnFlagUntilTimeout 0x08008bb9 Thumb Code 268 stm32h5xx_hal_uart.o(.text.UART_WaitOnFlagUntilTimeout) + USART1_IRQHandler 0x08008cc5 Thumb Code 16 stm32h5xx_it.o(.text.USART1_IRQHandler) + UsageFault_Handler 0x08008cd5 Thumb Code 4 stm32h5xx_it.o(.text.UsageFault_Handler) + _tx_byte_pool_create 0x08008d99 Thumb Code 304 tx_byte_pool_create.o(.text._tx_byte_pool_create) + _tx_initialize_high_level 0x08008ec9 Thumb Code 134 tx_initialize_high_level.o(.text._tx_initialize_high_level) + _tx_initialize_kernel_enter 0x08008f51 Thumb Code 104 tx_initialize_kernel_enter.o(.text._tx_initialize_kernel_enter) + _tx_thread_create 0x08008fb9 Thumb Code 538 tx_thread_create.o(.text._tx_thread_create) + _tx_thread_initialize 0x080091d5 Thumb Code 126 tx_thread_initialize.o(.text._tx_thread_initialize) + _tx_thread_shell_entry 0x08009255 Thumb Code 148 tx_thread_shell_entry.o(.text._tx_thread_shell_entry) + _tx_thread_system_preempt_check 0x080092e9 Thumb Code 112 tx_thread_system_preempt_check.o(.text._tx_thread_system_preempt_check) + _tx_thread_system_resume 0x08009359 Thumb Code 584 tx_thread_system_resume.o(.text._tx_thread_system_resume) + _tx_thread_system_suspend 0x080095a1 Thumb Code 640 tx_thread_system_suspend.o(.text._tx_thread_system_suspend) + _tx_thread_time_slice 0x08009821 Thumb Code 162 tx_thread_time_slice.o(.text._tx_thread_time_slice) + _tx_thread_timeout 0x080098c5 Thumb Code 114 tx_thread_timeout.o(.text._tx_thread_timeout) + _tx_timer_expiration_process 0x08009939 Thumb Code 60 tx_timer_expiration_process.o(.text._tx_timer_expiration_process) + _tx_timer_initialize 0x08009975 Thumb Code 286 tx_timer_initialize.o(.text._tx_timer_initialize) + _tx_timer_system_activate 0x08009a95 Thumb Code 212 tx_timer_system_activate.o(.text._tx_timer_system_activate) + _tx_timer_system_deactivate 0x08009b69 Thumb Code 112 tx_timer_system_deactivate.o(.text._tx_timer_system_deactivate) + _tx_timer_thread_entry 0x08009bd9 Thumb Code 536 tx_timer_thread_entry.o(.text._tx_timer_thread_entry) + _txe_byte_pool_create 0x08009df1 Thumb Code 372 txe_byte_pool_create.o(.text._txe_byte_pool_create) + main 0x08009f65 Thumb Code 32 main.o(.text.main) + tx_application_define 0x08009f85 Thumb Code 88 app_azure_rtos.o(.text.tx_application_define) + _fp_init 0x08009fdd Thumb Code 26 fpinit.o(x$fpl$fpinit) + __fplib_config_fpu_vfp 0x08009ff5 Thumb Code 0 fpinit.o(x$fpl$fpinit) + __fplib_config_pureend_doubles 0x08009ff5 Thumb Code 0 fpinit.o(x$fpl$fpinit) + AHBPrescTable 0x08009ff6 Data 16 system_stm32h5xx.o(.rodata.AHBPrescTable) + APBPrescTable 0x0800a006 Data 8 system_stm32h5xx.o(.rodata.APBPrescTable) + UARTPrescTable 0x0800a01e Data 24 stm32h5xx_hal_uart.o(.rodata.UARTPrescTable) + Region$$Table$$Base 0x0800a060 Number 0 anon$$obj.o(Region$$Table) + Region$$Table$$Limit 0x0800a080 Number 0 anon$$obj.o(Region$$Table) + SystemCoreClock 0x20000000 Data 4 system_stm32h5xx.o(.data.SystemCoreClock) + _tx_thread_system_state 0x20000004 Data 4 tx_thread_initialize.o(.data._tx_thread_system_state) + uwTickFreq 0x20000008 Data 1 stm32h5xx_hal.o(.data.uwTickFreq) + uwTickPrio 0x2000000c Data 4 stm32h5xx_hal.o(.data.uwTickPrio) + __libspace_start 0x20000010 Data 96 libspace.o(.bss) + __temporary_stack_top$libspace 0x20000070 Data 0 libspace.o(.bss) + _tx_block_pool_created_count 0x20000070 Data 4 tx_initialize_high_level.o(.bss._tx_block_pool_created_count) + _tx_block_pool_created_ptr 0x20000074 Data 4 tx_initialize_high_level.o(.bss._tx_block_pool_created_ptr) + _tx_build_options 0x20000078 Data 4 tx_thread_initialize.o(.bss._tx_build_options) + _tx_byte_pool_created_count 0x2000007c Data 4 tx_initialize_high_level.o(.bss._tx_byte_pool_created_count) + _tx_byte_pool_created_ptr 0x20000080 Data 4 tx_initialize_high_level.o(.bss._tx_byte_pool_created_ptr) + _tx_event_flags_created_count 0x20000084 Data 4 tx_initialize_high_level.o(.bss._tx_event_flags_created_count) + _tx_event_flags_created_ptr 0x20000088 Data 4 tx_initialize_high_level.o(.bss._tx_event_flags_created_ptr) + _tx_initialize_unused_memory 0x2000008c Data 4 tx_initialize_high_level.o(.bss._tx_initialize_unused_memory) + _tx_mutex_created_count 0x20000090 Data 4 tx_initialize_high_level.o(.bss._tx_mutex_created_count) + _tx_mutex_created_ptr 0x20000094 Data 4 tx_initialize_high_level.o(.bss._tx_mutex_created_ptr) + _tx_queue_created_count 0x20000098 Data 4 tx_initialize_high_level.o(.bss._tx_queue_created_count) + _tx_queue_created_ptr 0x2000009c Data 4 tx_initialize_high_level.o(.bss._tx_queue_created_ptr) + _tx_semaphore_created_count 0x200000a0 Data 4 tx_initialize_high_level.o(.bss._tx_semaphore_created_count) + _tx_semaphore_created_ptr 0x200000a4 Data 4 tx_initialize_high_level.o(.bss._tx_semaphore_created_ptr) + _tx_thread_created_count 0x200000a8 Data 4 tx_thread_initialize.o(.bss._tx_thread_created_count) + _tx_thread_created_ptr 0x200000ac Data 4 tx_thread_initialize.o(.bss._tx_thread_created_ptr) + _tx_thread_current_ptr 0x200000b0 Data 4 tx_thread_initialize.o(.bss._tx_thread_current_ptr) + _tx_thread_execute_ptr 0x200000b4 Data 4 tx_thread_initialize.o(.bss._tx_thread_execute_ptr) + _tx_thread_highest_priority 0x200000b8 Data 4 tx_thread_initialize.o(.bss._tx_thread_highest_priority) + _tx_thread_mutex_release 0x200000bc Data 4 tx_thread_initialize.o(.bss._tx_thread_mutex_release) + _tx_thread_preempt_disable 0x200000c0 Data 4 tx_thread_initialize.o(.bss._tx_thread_preempt_disable) + _tx_thread_priority_list 0x200000c4 Data 128 tx_thread_initialize.o(.bss._tx_thread_priority_list) + _tx_thread_priority_maps 0x20000144 Data 4 tx_thread_initialize.o(.bss._tx_thread_priority_maps) + _tx_thread_system_stack_ptr 0x20000148 Data 4 tx_thread_initialize.o(.bss._tx_thread_system_stack_ptr) + _tx_timer_created_count 0x2000014c Data 4 tx_timer_initialize.o(.bss._tx_timer_created_count) + _tx_timer_created_ptr 0x20000150 Data 4 tx_timer_initialize.o(.bss._tx_timer_created_ptr) + _tx_timer_current_ptr 0x20000154 Data 4 tx_timer_initialize.o(.bss._tx_timer_current_ptr) + _tx_timer_expired 0x20000158 Data 4 tx_timer_initialize.o(.bss._tx_timer_expired) + _tx_timer_expired_time_slice 0x2000015c Data 4 tx_timer_initialize.o(.bss._tx_timer_expired_time_slice) + _tx_timer_expired_timer_ptr 0x20000160 Data 4 tx_timer_initialize.o(.bss._tx_timer_expired_timer_ptr) + _tx_timer_list 0x20000164 Data 128 tx_timer_initialize.o(.bss._tx_timer_list) + _tx_timer_list_end 0x200001e4 Data 4 tx_timer_initialize.o(.bss._tx_timer_list_end) + _tx_timer_list_start 0x200001e8 Data 4 tx_timer_initialize.o(.bss._tx_timer_list_start) + _tx_timer_priority 0x200001ec Data 4 tx_timer_initialize.o(.bss._tx_timer_priority) + _tx_timer_stack_size 0x200001f0 Data 4 tx_timer_initialize.o(.bss._tx_timer_stack_size) + _tx_timer_stack_start 0x200001f4 Data 4 tx_timer_initialize.o(.bss._tx_timer_stack_start) + _tx_timer_system_clock 0x200001f8 Data 4 tx_timer_initialize.o(.bss._tx_timer_system_clock) + _tx_timer_thread 0x200001fc Data 176 tx_timer_initialize.o(.bss._tx_timer_thread) + _tx_timer_thread_stack_area 0x200002ac Data 1024 tx_timer_initialize.o(.bss._tx_timer_thread_stack_area) + _tx_timer_time_slice 0x200006ac Data 4 tx_timer_initialize.o(.bss._tx_timer_time_slice) + htim1 0x200006b0 Data 76 stm32h5xx_hal_timebase_tim.o(.bss.htim1) + huart1 0x200006fc Data 148 usart.o(.bss.huart1) + uwTick 0x20000bc4 Data 4 stm32h5xx_hal.o(.bss.uwTick) + + + +============================================================================== + +Memory Map of the image + + Image Entry point : 0x0800024d + + Load Region LR_IROM1 (Base: 0x08000000, Size: 0x0000a090, Max: 0x00200000, ABSOLUTE) + + Execution Region ER_IROM1 (Exec base: 0x08000000, Load base: 0x08000000, Size: 0x0000a080, Max: 0x00200000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x08000000 0x08000000 0x0000024c Data RO 3 RESET startup_stm32h563xx.o + 0x0800024c 0x0800024c 0x00000008 Code RO 2836 * !!!main c_w.l(__main.o) + 0x08000254 0x08000254 0x0000005c Code RO 3183 !!!scatter c_w.l(__scatter.o) + 0x080002b0 0x080002b0 0x0000001a Code RO 3187 !!handler_copy c_w.l(__scatter_copy.o) + 0x080002ca 0x080002ca 0x00000002 PAD + 0x080002cc 0x080002cc 0x00000002 Code RO 3184 !!handler_null c_w.l(__scatter.o) + 0x080002ce 0x080002ce 0x00000002 PAD + 0x080002d0 0x080002d0 0x0000001c Code RO 3189 !!handler_zi c_w.l(__scatter_zi.o) + 0x080002ec 0x080002ec 0x00000002 Code RO 3031 .ARM.Collect$$libinit$$00000000 c_w.l(libinit.o) + 0x080002ee 0x080002ee 0x00000004 Code RO 3055 .ARM.Collect$$libinit$$00000001 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3058 .ARM.Collect$$libinit$$00000004 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3060 .ARM.Collect$$libinit$$00000006 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3063 .ARM.Collect$$libinit$$0000000C c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3065 .ARM.Collect$$libinit$$0000000E c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3067 .ARM.Collect$$libinit$$00000010 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3070 .ARM.Collect$$libinit$$00000013 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3072 .ARM.Collect$$libinit$$00000015 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3074 .ARM.Collect$$libinit$$00000017 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3076 .ARM.Collect$$libinit$$00000019 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3078 .ARM.Collect$$libinit$$0000001B c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3080 .ARM.Collect$$libinit$$0000001D c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3082 .ARM.Collect$$libinit$$0000001F c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3084 .ARM.Collect$$libinit$$00000021 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3086 .ARM.Collect$$libinit$$00000023 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3088 .ARM.Collect$$libinit$$00000025 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3090 .ARM.Collect$$libinit$$00000027 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3094 .ARM.Collect$$libinit$$0000002E c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3096 .ARM.Collect$$libinit$$00000030 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3098 .ARM.Collect$$libinit$$00000032 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000000 Code RO 3100 .ARM.Collect$$libinit$$00000034 c_w.l(libinit2.o) + 0x080002f2 0x080002f2 0x00000002 Code RO 3101 .ARM.Collect$$libinit$$00000035 c_w.l(libinit2.o) + 0x080002f4 0x080002f4 0x00000002 Code RO 3138 .ARM.Collect$$libshutdown$$00000000 c_w.l(libshutdown.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3166 .ARM.Collect$$libshutdown$$00000002 c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3168 .ARM.Collect$$libshutdown$$00000004 c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3171 .ARM.Collect$$libshutdown$$00000007 c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3174 .ARM.Collect$$libshutdown$$0000000A c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3176 .ARM.Collect$$libshutdown$$0000000C c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000000 Code RO 3179 .ARM.Collect$$libshutdown$$0000000F c_w.l(libshutdown2.o) + 0x080002f6 0x080002f6 0x00000002 Code RO 3180 .ARM.Collect$$libshutdown$$00000010 c_w.l(libshutdown2.o) + 0x080002f8 0x080002f8 0x00000000 Code RO 2838 .ARM.Collect$$rtentry$$00000000 c_w.l(__rtentry.o) + 0x080002f8 0x080002f8 0x00000000 Code RO 2943 .ARM.Collect$$rtentry$$00000002 c_w.l(__rtentry2.o) + 0x080002f8 0x080002f8 0x00000006 Code RO 2955 .ARM.Collect$$rtentry$$00000004 c_w.l(__rtentry4.o) + 0x080002fe 0x080002fe 0x00000000 Code RO 2945 .ARM.Collect$$rtentry$$00000009 c_w.l(__rtentry2.o) + 0x080002fe 0x080002fe 0x00000004 Code RO 2946 .ARM.Collect$$rtentry$$0000000A c_w.l(__rtentry2.o) + 0x08000302 0x08000302 0x00000000 Code RO 2948 .ARM.Collect$$rtentry$$0000000C c_w.l(__rtentry2.o) + 0x08000302 0x08000302 0x00000008 Code RO 2949 .ARM.Collect$$rtentry$$0000000D c_w.l(__rtentry2.o) + 0x0800030a 0x0800030a 0x00000002 Code RO 3040 .ARM.Collect$$rtexit$$00000000 c_w.l(rtexit.o) + 0x0800030c 0x0800030c 0x00000000 Code RO 3107 .ARM.Collect$$rtexit$$00000002 c_w.l(rtexit2.o) + 0x0800030c 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Code RO 2979 .text c_w.l(sys_stackheap_outer.o) + 0x0800077e 0x0800077e 0x00000012 Code RO 3020 .text c_w.l(exit.o) + 0x08000790 0x08000790 0x00000008 Code RO 3037 .text c_w.l(libspace.o) + 0x08000798 0x08000798 0x0000000c Code RO 3102 .text c_w.l(sys_exit.o) + 0x080007a4 0x080007a4 0x00000002 Code RO 3127 .text c_w.l(use_no_semi.o) + 0x080007a6 0x080007a6 0x00000000 Code RO 3129 .text c_w.l(indicate_semi.o) + 0x080007a6 0x080007a6 0x00000002 PAD + 0x080007a8 0x080007a8 0x0000000e Code RO 41 .text.App_ThreadX_Init app_threadx.o + 0x080007b6 0x080007b6 0x00000002 PAD + 0x080007b8 0x080007b8 0x00000004 Code RO 72 .text.BusFault_Handler stm32h5xx_it.o + 0x080007bc 0x080007bc 0x00000002 Code RO 76 .text.DebugMon_Handler stm32h5xx_it.o + 0x080007be 0x080007be 0x00000002 PAD + 0x080007c0 0x080007c0 0x00000006 Code RO 15 .text.Error_Handler main.o + 0x080007c6 0x080007c6 0x00000002 PAD + 0x080007c8 0x080007c8 0x00000116 Code RO 875 .text.HAL_DMA_Abort stm32h5xx_hal_dma.o + 0x080008de 0x080008de 0x00000002 PAD + 0x080008e0 0x080008e0 0x00000054 Code RO 877 .text.HAL_DMA_Abort_IT stm32h5xx_hal_dma.o + 0x08000934 0x08000934 0x000002ea Code RO 832 .text.HAL_GPIO_Init stm32h5xx_hal_gpio.o + 0x08000c1e 0x08000c1e 0x00000002 PAD + 0x08000c20 0x08000c20 0x0000000c Code RO 1150 .text.HAL_GetTick stm32h5xx_hal.o + 0x08000c2c 0x08000c2c 0x0000001a Code RO 1148 .text.HAL_IncTick stm32h5xx_hal.o + 0x08000c46 0x08000c46 0x00000002 PAD + 0x08000c48 0x08000c48 0x0000005e Code RO 1138 .text.HAL_Init stm32h5xx_hal.o + 0x08000ca6 0x08000ca6 0x00000002 PAD + 0x08000ca8 0x08000ca8 0x000000ce Code RO 97 .text.HAL_InitTick stm32h5xx_hal_timebase_tim.o + 0x08000d76 0x08000d76 0x00000002 PAD + 0x08000d78 0x08000d78 0x00000002 Code RO 89 .text.HAL_MspInit stm32h5xx_hal_msp.o + 0x08000d7a 0x08000d7a 0x00000002 PAD + 0x08000d7c 0x08000d7c 0x00000014 Code RO 530 .text.HAL_NVIC_EnableIRQ stm32h5xx_hal_cortex.o + 0x08000d90 0x08000d90 0x0000002e Code RO 522 .text.HAL_NVIC_SetPriority stm32h5xx_hal_cortex.o + 0x08000dbe 0x08000dbe 0x00000002 PAD + 0x08000dc0 0x08000dc0 0x00000010 Code RO 518 .text.HAL_NVIC_SetPriorityGrouping stm32h5xx_hal_cortex.o + 0x08000dd0 0x08000dd0 0x000002f8 Code RO 648 .text.HAL_RCCEx_GetPLL1ClockFreq stm32h5xx_hal_rcc_ex.o + 0x080010c8 0x080010c8 0x000002f8 Code RO 650 .text.HAL_RCCEx_GetPLL2ClockFreq stm32h5xx_hal_rcc_ex.o + 0x080013c0 0x080013c0 0x000002f8 Code RO 652 .text.HAL_RCCEx_GetPLL3ClockFreq stm32h5xx_hal_rcc_ex.o + 0x080016b8 0x080016b8 0x000028f8 Code RO 654 .text.HAL_RCCEx_GetPeriphCLKFreq stm32h5xx_hal_rcc_ex.o + 0x08003fb0 0x08003fb0 0x000018ee Code RO 640 .text.HAL_RCCEx_PeriphCLKConfig stm32h5xx_hal_rcc_ex.o + 0x0800589e 0x0800589e 0x00000002 PAD + 0x080058a0 0x080058a0 0x00000494 Code RO 605 .text.HAL_RCC_ClockConfig stm32h5xx_hal_rcc.o + 0x08005d34 0x08005d34 0x0000006c Code RO 619 .text.HAL_RCC_GetClockConfig stm32h5xx_hal_rcc.o + 0x08005da0 0x08005da0 0x00000034 Code RO 603 .text.HAL_RCC_GetHCLKFreq stm32h5xx_hal_rcc.o + 0x08005dd4 0x08005dd4 0x00000026 Code RO 611 .text.HAL_RCC_GetPCLK1Freq stm32h5xx_hal_rcc.o + 0x08005dfa 0x08005dfa 0x00000002 PAD + 0x08005dfc 0x08005dfc 0x00000026 Code RO 613 .text.HAL_RCC_GetPCLK2Freq stm32h5xx_hal_rcc.o + 0x08005e22 0x08005e22 0x00000002 PAD + 0x08005e24 0x08005e24 0x00000026 Code RO 615 .text.HAL_RCC_GetPCLK3Freq stm32h5xx_hal_rcc.o + 0x08005e4a 0x08005e4a 0x00000002 PAD + 0x08005e4c 0x08005e4c 0x000002cc Code RO 607 .text.HAL_RCC_GetSysClockFreq stm32h5xx_hal_rcc.o + 0x08006118 0x08006118 0x000009fc Code RO 601 .text.HAL_RCC_OscConfig stm32h5xx_hal_rcc.o + 0x08006b14 0x08006b14 0x0000009a Code RO 568 .text.HAL_SYSTICK_CLKSourceConfig stm32h5xx_hal_cortex.o + 0x08006bae 0x08006bae 0x00000002 PAD + 0x08006bb0 0x08006bb0 0x00000008 Code RO 497 .text.HAL_TIMEx_Break2Callback stm32h5xx_hal_tim_ex.o + 0x08006bb8 0x08006bb8 0x00000008 Code RO 495 .text.HAL_TIMEx_BreakCallback stm32h5xx_hal_tim_ex.o + 0x08006bc0 0x08006bc0 0x00000008 Code RO 491 .text.HAL_TIMEx_CommutCallback stm32h5xx_hal_tim_ex.o + 0x08006bc8 0x08006bc8 0x00000008 Code RO 501 .text.HAL_TIMEx_DirectionChangeCallback stm32h5xx_hal_tim_ex.o + 0x08006bd0 0x08006bd0 0x00000008 Code RO 499 .text.HAL_TIMEx_EncoderIndexCallback stm32h5xx_hal_tim_ex.o + 0x08006bd8 0x08006bd8 0x00000008 Code RO 503 .text.HAL_TIMEx_IndexErrorCallback stm32h5xx_hal_tim_ex.o + 0x08006be0 0x08006be0 0x00000008 Code RO 505 .text.HAL_TIMEx_TransitionErrorCallback stm32h5xx_hal_tim_ex.o + 0x08006be8 0x08006be8 0x000000a8 Code RO 122 .text.HAL_TIM_Base_Init stm32h5xx_hal_tim.o + 0x08006c90 0x08006c90 0x00000008 Code RO 124 .text.HAL_TIM_Base_MspInit stm32h5xx_hal_tim.o + 0x08006c98 0x08006c98 0x00000192 Code RO 136 .text.HAL_TIM_Base_Start_IT stm32h5xx_hal_tim.o + 0x08006e2a 0x08006e2a 0x00000002 PAD + 0x08006e2c 0x08006e2c 0x00000008 Code RO 260 .text.HAL_TIM_IC_CaptureCallback stm32h5xx_hal_tim.o + 0x08006e34 0x08006e34 0x00000300 Code RO 258 .text.HAL_TIM_IRQHandler stm32h5xx_hal_tim.o + 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Code RO 1453 .text.HAL_UARTEx_TxFifoEmptyCallback stm32h5xx_hal_uart_ex.o + 0x08007320 0x08007320 0x00000008 Code RO 1449 .text.HAL_UARTEx_WakeupCallback stm32h5xx_hal_uart_ex.o + 0x08007328 0x08007328 0x00000008 Code RO 1391 .text.HAL_UART_ErrorCallback stm32h5xx_hal_uart.o + 0x08007330 0x08007330 0x00000542 Code RO 1387 .text.HAL_UART_IRQHandler stm32h5xx_hal_uart.o + 0x08007872 0x08007872 0x00000002 PAD + 0x08007874 0x08007874 0x000000aa Code RO 1299 .text.HAL_UART_Init stm32h5xx_hal_uart.o + 0x0800791e 0x0800791e 0x00000002 PAD + 0x08007920 0x08007920 0x000000c0 Code RO 54 .text.HAL_UART_MspInit usart.o + 0x080079e0 0x080079e0 0x00000008 Code RO 1397 .text.HAL_UART_TxCpltCallback stm32h5xx_hal_uart.o + 0x080079e8 0x080079e8 0x00000004 Code RO 68 .text.HardFault_Handler stm32h5xx_it.o + 0x080079ec 0x080079ec 0x00000042 Code RO 32 .text.MX_GPIO_Init gpio.o + 0x08007a2e 0x08007a2e 0x00000002 PAD + 0x08007a30 0x08007a30 0x00000008 Code RO 43 .text.MX_ThreadX_Init app_threadx.o + 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0x0800837e 0x00000002 PAD + 0x08008380 0x08008380 0x0000008a Code RO 1467 .text.UARTEx_SetNbDataToProcess stm32h5xx_hal_uart_ex.o + 0x0800840a 0x0800840a 0x00000002 PAD + 0x0800840c 0x0800840c 0x00000148 Code RO 1303 .text.UART_AdvFeatureConfig stm32h5xx_hal_uart.o + 0x08008554 0x08008554 0x00000146 Code RO 1307 .text.UART_CheckIdleState stm32h5xx_hal_uart.o + 0x0800869a 0x0800869a 0x00000002 PAD + 0x0800869c 0x0800869c 0x0000001e Code RO 1389 .text.UART_DMAAbortOnError stm32h5xx_hal_uart.o + 0x080086ba 0x080086ba 0x00000002 PAD + 0x080086bc 0x080086bc 0x0000009e Code RO 1359 .text.UART_EndRxTransfer stm32h5xx_hal_uart.o + 0x0800875a 0x0800875a 0x00000002 PAD + 0x0800875c 0x0800875c 0x00000044 Code RO 1395 .text.UART_EndTransmit_IT stm32h5xx_hal_uart.o + 0x080087a0 0x080087a0 0x00000418 Code RO 1305 .text.UART_SetConfig stm32h5xx_hal_uart.o + 0x08008bb8 0x08008bb8 0x0000010c Code RO 1321 .text.UART_WaitOnFlagUntilTimeout stm32h5xx_hal_uart.o + 0x08008cc4 0x08008cc4 0x00000010 Code RO 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tx_timer_expiration_process.o + 0x08009974 0x08009974 0x0000011e Code RO 2708 .text._tx_timer_initialize tx_timer_initialize.o + 0x08009a92 0x08009a92 0x00000002 PAD + 0x08009a94 0x08009a94 0x000000d4 Code RO 2733 .text._tx_timer_system_activate tx_timer_system_activate.o + 0x08009b68 0x08009b68 0x00000070 Code RO 2741 .text._tx_timer_system_deactivate tx_timer_system_deactivate.o + 0x08009bd8 0x08009bd8 0x00000218 Code RO 2749 .text._tx_timer_thread_entry tx_timer_thread_entry.o + 0x08009df0 0x08009df0 0x00000174 Code RO 2276 .text._txe_byte_pool_create txe_byte_pool_create.o + 0x08009f64 0x08009f64 0x00000020 Code RO 11 .text.main main.o + 0x08009f84 0x08009f84 0x00000058 Code RO 111 .text.tx_application_define app_azure_rtos.o + 0x08009fdc 0x08009fdc 0x0000001a Code RO 3121 x$fpl$fpinit fz_wm.l(fpinit.o) + 0x08009ff6 0x08009ff6 0x00000010 Data RO 1497 .rodata.AHBPrescTable system_stm32h5xx.o + 0x0800a006 0x0800a006 0x00000008 Data RO 1498 .rodata.APBPrescTable system_stm32h5xx.o + 0x0800a00e 0x0800a00e 0x00000008 Data RO 1484 .rodata.UARTEx_SetNbDataToProcess.denominator stm32h5xx_hal_uart_ex.o + 0x0800a016 0x0800a016 0x00000008 Data RO 1483 .rodata.UARTEx_SetNbDataToProcess.numerator stm32h5xx_hal_uart_ex.o + 0x0800a01e 0x0800a01e 0x00000018 Data RO 1439 .rodata.UARTPrescTable stm32h5xx_hal_uart.o + 0x0800a036 0x0800a036 0x00000013 Data RO 114 .rodata.str1.1 app_azure_rtos.o + 0x0800a049 0x0800a049 0x00000014 Data RO 2724 .rodata.str1.1 tx_timer_initialize.o + 0x0800a05d 0x0800a05d 0x00000003 PAD + 0x0800a060 0x0800a060 0x00000020 Data RO 3182 Region$$Table anon$$obj.o + + + Execution Region RW_IRAM1 (Exec base: 0x20000000, Load base: 0x0800a080, Size: 0x000011c8, Max: 0x000a0000, ABSOLUTE) + + Exec Addr Load Addr Size Type Attr Idx E Section Name Object + + 0x20000000 0x0800a080 0x00000004 Data RW 1496 .data.SystemCoreClock system_stm32h5xx.o + 0x20000004 0x0800a084 0x00000004 Data RW 2056 .data._tx_thread_system_state tx_thread_initialize.o + 0x20000008 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0x0000004c Zero RW 103 .bss.htim1 stm32h5xx_hal_timebase_tim.o + 0x200006fc - 0x00000094 Zero RW 58 .bss.huart1 usart.o + 0x20000790 - 0x00000034 Zero RW 113 .bss.tx_app_byte_pool app_azure_rtos.o + 0x200007c4 - 0x00000400 Zero RW 115 .bss.tx_byte_pool_buffer app_azure_rtos.o + 0x20000bc4 - 0x00000004 Zero RW 1262 .bss.uwTick stm32h5xx_hal.o + 0x20000bc8 - 0x00000200 Zero RW 2 HEAP startup_stm32h563xx.o + 0x20000dc8 - 0x00000400 Zero RW 1 STACK startup_stm32h563xx.o + + +============================================================================== + +Image component sizes + + + Code (inc. data) RO Data RW Data ZI Data Debug Object Name + + 88 0 19 0 1076 4013 app_azure_rtos.o + 22 0 0 0 0 714 app_threadx.o + 66 0 0 0 0 2187 gpio.o + 270 0 0 0 0 8399 main.o + 68 28 588 0 1536 944 startup_stm32h563xx.o + 132 0 0 5 4 13991 stm32h5xx_hal.o + 534 6 0 0 0 13387 stm32h5xx_hal_cortex.o + 362 0 0 0 0 9291 stm32h5xx_hal_dma.o + 746 0 0 0 0 5090 stm32h5xx_hal_gpio.o + 2 0 0 0 0 369 stm32h5xx_hal_msp.o + 4718 16 0 0 0 13001 stm32h5xx_hal_rcc.o + 19878 178 0 0 0 29257 stm32h5xx_hal_rcc_ex.o + 2236 0 0 0 0 39348 stm32h5xx_hal_tim.o + 56 0 0 0 0 21807 stm32h5xx_hal_tim_ex.o + 206 0 0 0 76 9734 stm32h5xx_hal_timebase_tim.o + 3770 0 24 0 0 26676 stm32h5xx_hal_uart.o + 566 0 16 0 0 9343 stm32h5xx_hal_uart_ex.o + 54 0 0 0 0 947 stm32h5xx_it.o + 310 0 24 4 0 6001 system_stm32h5xx.o + 304 0 0 0 0 4756 tx_byte_pool_create.o + 134 0 0 0 52 6286 tx_initialize_high_level.o + 104 0 0 0 0 655 tx_initialize_kernel_enter.o + 120 20 0 0 0 550 tx_initialize_low_level.o + 538 0 0 0 0 4752 tx_thread_create.o + 126 0 0 4 168 3995 tx_thread_initialize.o + 208 16 0 0 0 774 tx_thread_schedule.o + 148 0 0 0 0 3912 tx_thread_shell_entry.o + 64 0 0 0 0 459 tx_thread_stack_build.o + 112 0 0 0 0 3892 tx_thread_system_preempt_check.o + 584 0 0 0 0 4859 tx_thread_system_resume.o + 640 0 0 0 0 5068 tx_thread_system_suspend.o + 162 0 0 0 0 3716 tx_thread_time_slice.o + 114 0 0 0 0 3844 tx_thread_timeout.o + 60 0 0 0 0 1108 tx_timer_expiration_process.o + 286 0 20 0 1380 4262 tx_timer_initialize.o + 184 44 0 0 0 812 tx_timer_interrupt.o + 212 0 0 0 0 1562 tx_timer_system_activate.o + 112 0 0 0 0 1413 tx_timer_system_deactivate.o + 536 0 0 0 0 4737 tx_timer_thread_entry.o + 372 0 0 0 0 4931 txe_byte_pool_create.o + 334 0 0 0 148 11787 usart.o + + ---------------------------------------------------------------------- + 39608 308 726 16 4440 292629 Object Totals + 0 0 32 0 0 0 (incl. Generated) + 70 0 3 3 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Member Name + + 8 0 0 0 0 68 __main.o + 0 0 0 0 0 0 __rtentry.o + 12 0 0 0 0 0 __rtentry2.o + 6 0 0 0 0 0 __rtentry4.o + 94 8 0 0 0 0 __scatter.o + 26 0 0 0 0 0 __scatter_copy.o + 28 0 0 0 0 0 __scatter_zi.o + 16 0 0 0 0 68 aeabi_memset.o + 18 0 0 0 0 80 exit.o + 6 0 0 0 0 152 heapauxi.o + 0 0 0 0 0 0 indicate_semi.o + 2 0 0 0 0 0 libinit.o + 6 0 0 0 0 0 libinit2.o + 2 0 0 0 0 0 libshutdown.o + 2 0 0 0 0 0 libshutdown2.o + 8 4 0 0 96 68 libspace.o + 240 0 0 0 0 100 lludivv7m.o + 68 0 0 0 0 68 rt_memclr.o + 78 0 0 0 0 80 rt_memclr_w.o + 2 0 0 0 0 0 rtexit.o + 10 0 0 0 0 0 rtexit2.o + 12 4 0 0 0 68 sys_exit.o + 74 0 0 0 0 80 sys_stackheap_outer.o + 2 0 0 0 0 68 use_no_semi.o + 26 0 0 0 0 116 fpinit.o + + ---------------------------------------------------------------------- + 754 16 0 0 96 1016 Library Totals + 8 0 0 0 0 0 (incl. Padding) + + ---------------------------------------------------------------------- + + Code (inc. data) RO Data RW Data ZI Data Debug Library Name + + 720 16 0 0 96 900 c_w.l + 26 0 0 0 0 116 fz_wm.l + + ---------------------------------------------------------------------- + 754 16 0 0 96 1016 Library Totals + + ---------------------------------------------------------------------- + +============================================================================== + + + Code (inc. data) RO Data RW Data ZI Data Debug + + 40362 324 726 16 4536 292649 Grand Totals + 40362 324 726 16 4536 292649 ELF Image Totals + 40362 324 726 16 0 0 ROM Totals + +============================================================================== + + Total RO Size (Code + RO Data) 41088 ( 40.12kB) + Total RW Size (RW Data + ZI Data) 4552 ( 4.45kB) + Total ROM Size (Code + RO Data + RW Data) 41104 ( 40.14kB) + +============================================================================== + diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick.sct b/MDK-ARM/AutoGuideStick/AutoGuideStick.sct new file mode 100644 index 0000000..c1ef19e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick.sct @@ -0,0 +1,16 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x08000000 0x00200000 { ; load region size_region + ER_IROM1 0x08000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x20000000 0x000A0000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep b/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep new file mode 100644 index 0000000..c76fe06 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/AutoGuideStick_AutoGuideStick.dep @@ -0,0 +1,1996 @@ +Dependencies for Project 'AutoGuideStick', Target 'AutoGuideStick': (DO NOT MODIFY !) +CompilerVersion: 6210000::V6.21::ARMCLANG +F (startup_stm32h563xx.s)(0x684461E3)(--target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -masm=auto -Wa,armasm,--diag_suppress=A1950W -c -gdwarf-4 -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -Wa,armasm,--pd,"__UVISION_VERSION SETA 539" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"STM32H563xx SETA 1" -Wa,armasm,--pd,"_RTE_ SETA 1" -Wa,armasm,--pd,"TX_SINGLE_MODE_NON_SECURE SETA 1" -o autoguidestick/startup_stm32h563xx.o) +F (../Core/Src/main.c)(0x684461E1)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx -o autoguidestick/main.o -MD) +I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA) +I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9) +I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000) +I (D:\keil5\ARM\ARMCLANG\include\string.hL\Core\Inc\main.h)(0x00000000) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD) +I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD) +I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD) +I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000) +F (../Core/Src/tx_initialize_low_level.S)(0x6840230D)(--target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -masm=auto -Wa,armasm,--diag_suppress=A1950W -c -gdwarf-4 -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION=539 -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_SINGLE_MODE_NON_SECURE=1 -o autoguidestick/tx_initialize_low_level.o) +F (../Core/Src/gpio.c)(0x684461DF)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx -o autoguidestick/gpio.o -MD) +I (..\Core\Inc\main.ho.\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x00000000) +I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE) +I (d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD) +I 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(..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD) +F (../Core/Src/memorymap.c)(0x6840230D)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I 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../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx -o autoguidestick/txe_timer_delete.o -MD) +I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA) +I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9) +I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000) +I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012) +I (..\Middlewares\ST\threadx\common\inc\tx_thread.h)(0x683FA4DA) +I (..\Middlewares\ST\threadx\common\inc\tx_timer.h)(0x683FA4DA) +F (../Middlewares/ST/threadx/common/src/txe_timer_info_get.c)(0x683FA4DA)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx -o autoguidestick/txe_timer_info_get.o -MD) +I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA) +I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9) +I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000) +I (D:\keil5\ARM\ARMCLANG\include\string.h)(0x6569B012) +I (..\Middlewares\ST\threadx\common\inc\tx_timer.h)(0x683FA4DA) +F (..\fun\HCBle.c)(0x68459D61)(-xc -std=c11 --target=arm-arm-none-eabi -mcpu=cortex-m33 -mfpu=fpv5-sp-d16 -mfloat-abi=hard -c -fno-rtti -funsigned-char -fshort-enums -fshort-wchar -gdwarf-4 -O0 -ffunction-sections -Wno-packed -Wno-missing-variable-declarations -Wno-missing-prototypes -Wno-missing-noreturn -Wno-sign-conversion -Wno-nonportable-include-path -Wno-reserved-id-macro -Wno-unused-macros -Wno-documentation-unknown-command -Wno-documentation -Wno-license-management -Wno-parentheses-equality -Wno-reserved-identifier -I ../Core/Inc -I ../AZURE_RTOS/App -I ../Drivers/STM32H5xx_HAL_Driver/Inc -I ../Drivers/STM32H5xx_HAL_Driver/Inc/Legacy -I ../Middlewares/ST/threadx/common/inc -I ../Drivers/CMSIS/Device/ST/STM32H5xx/Include -I ../Middlewares/ST/threadx/ports/cortex_m33/ac6/inc -I ../Drivers/CMSIS/Include -I ../fun -I./RTE/_AutoGuideStick -ID:/keil5/ARM/PACK/ARM/CMSIS/5.9.0/CMSIS/Core/Include -ID:/keil5/ARM/PACK/Keil/STM32H5xx_DFP/1.3.0/Drivers/CMSIS/Device/ST/STM32H5xx/Include -D__UVISION_VERSION="539" -D_RTE_ -DSTM32H563xx -D_RTE_ -DTX_INCLUDE_USER_DEFINE_FILE -DTX_SINGLE_MODE_NON_SECURE="1" -DUSE_HAL_DRIVER -DSTM32H563xx -o autoguidestick/hcble.o -MD) +I (..\Core\Inc\app_threadx.h)(0x6840230D) +I (..\Middlewares\ST\threadx\common\inc\tx_api.h)(0x683FA4DA) +I (..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h)(0x683FA4D9) +I (..\Core\Inc\tx_user.he:\keil5\ARM\ARMCLANG\include\stdlib.h)(0x00000000) +I (D:\keil5\ARM\ARMCLANG\include\string.hL\Core\Inc\main.h)(0x00000000) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h)(0x683FA4DD) +I (..\Core\Inc\stm32h5xx_hal_conf.h)(0x684461E1) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h)(0x683FA4DD) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\math.h)(0x6569B012) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Include\core_cm33.h)(0x683FA4DE) +I (D:\keil5\ARM\ARMCLANG\include\stdint.h)(0x6569B012) +I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h)(0x683FA4DE) +I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h)(0x683FA4DE) +I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h)(0x683FA4DE) +I (D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h)(0x683FA4DE) +I (..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h)(0x683FA4DE) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h)(0x683FA4DD) +I (D:\keil5\ARM\ARMCLANG\include\stddef.h)(0x6569B012) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h)(0x683FA4DD) +I (..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h)(0x683FA4DD) +I (..\Core\Inc\memorymap.hL.\Core\Inc\usart.h5.\Core\Inc\gpio.h)(0x00000000) +I (D:\keil5\ARM\ARMCLANG\include\stdio.h)(0x6569B012) +I (D:\keil5\ARM\ARMCLANG\include\stdarg.h)(0x6569B012) +F (..\fun\HCBle.h)(0x68459D61)() +F (..\fun\headfile.h)(0x68459599)() diff --git a/MDK-ARM/AutoGuideStick/app_azure_rtos.d b/MDK-ARM/AutoGuideStick/app_azure_rtos.d new file mode 100644 index 0000000..082266f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/app_azure_rtos.d @@ -0,0 +1,38 @@ +autoguidestick/app_azure_rtos.o: ..\AZURE_RTOS\App\app_azure_rtos.c \ + ..\AZURE_RTOS\App\app_azure_rtos.h ..\Core\Inc\app_threadx.h \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \ + ..\AZURE_RTOS\App\app_azure_rtos_config.h diff --git a/MDK-ARM/AutoGuideStick/app_azure_rtos.o b/MDK-ARM/AutoGuideStick/app_azure_rtos.o new file mode 100644 index 0000000..c2fee0f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/app_azure_rtos.o differ diff --git a/MDK-ARM/AutoGuideStick/app_threadx.d b/MDK-ARM/AutoGuideStick/app_threadx.d new file mode 100644 index 0000000..30b154d --- /dev/null +++ b/MDK-ARM/AutoGuideStick/app_threadx.d @@ -0,0 +1,6 @@ +autoguidestick/app_threadx.o: ..\Core\Src\app_threadx.c \ + ..\Core\Inc\app_threadx.h \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h diff --git a/MDK-ARM/AutoGuideStick/app_threadx.o b/MDK-ARM/AutoGuideStick/app_threadx.o new file mode 100644 index 0000000..6d2336a Binary files /dev/null and b/MDK-ARM/AutoGuideStick/app_threadx.o differ diff --git a/MDK-ARM/AutoGuideStick/gpio.d b/MDK-ARM/AutoGuideStick/gpio.d new file mode 100644 index 0000000..c6734c9 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/gpio.d @@ -0,0 +1,32 @@ +autoguidestick/gpio.o: ..\Core\Src\gpio.c ..\Core\Inc\gpio.h \ + ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/gpio.o b/MDK-ARM/AutoGuideStick/gpio.o new file mode 100644 index 0000000..2cad619 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/gpio.o differ diff --git a/MDK-ARM/AutoGuideStick/hcble.d b/MDK-ARM/AutoGuideStick/hcble.d new file mode 100644 index 0000000..3f7710c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/hcble.d @@ -0,0 +1,40 @@ +autoguidestick/hcble.o: ..\fun\HCBle.c ..\fun\HCBle.h ..\fun\headfile.h \ + ..\Core\Inc\app_threadx.h \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h ..\Core\Inc\main.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \ + ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h \ + D:\keil5\ARM\ARMCLANG\include\stdio.h \ + D:\keil5\ARM\ARMCLANG\include\stdarg.h diff --git a/MDK-ARM/AutoGuideStick/hcble.o b/MDK-ARM/AutoGuideStick/hcble.o new file mode 100644 index 0000000..e4f78ed Binary files /dev/null and b/MDK-ARM/AutoGuideStick/hcble.o differ diff --git a/MDK-ARM/AutoGuideStick/icache.d b/MDK-ARM/AutoGuideStick/icache.d new file mode 100644 index 0000000..63574f5 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/icache.d @@ -0,0 +1,31 @@ +autoguidestick/icache.o: ..\Core\Src\icache.c ..\Core\Inc\icache.h \ + ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/icache.o b/MDK-ARM/AutoGuideStick/icache.o new file mode 100644 index 0000000..b72a00d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/icache.o differ diff --git a/MDK-ARM/AutoGuideStick/main.d b/MDK-ARM/AutoGuideStick/main.d new file mode 100644 index 0000000..835459e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/main.d @@ -0,0 +1,37 @@ +autoguidestick/main.o: ..\Core\Src\main.c ..\Core\Inc\app_threadx.h \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h ..\Core\Inc\main.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \ + ..\Core\Inc\memorymap.h ..\Core\Inc\usart.h ..\Core\Inc\gpio.h diff --git a/MDK-ARM/AutoGuideStick/main.o b/MDK-ARM/AutoGuideStick/main.o new file mode 100644 index 0000000..0e57ab7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/main.o differ diff --git a/MDK-ARM/AutoGuideStick/memorymap.d b/MDK-ARM/AutoGuideStick/memorymap.d new file mode 100644 index 0000000..dcd215a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/memorymap.d @@ -0,0 +1,33 @@ +autoguidestick/memorymap.o: ..\Core\Src\memorymap.c \ + ..\Core\Inc\memorymap.h ..\Core\Inc\main.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/memorymap.o b/MDK-ARM/AutoGuideStick/memorymap.o new file mode 100644 index 0000000..9f15029 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/memorymap.o differ diff --git a/MDK-ARM/AutoGuideStick/startup_stm32h563xx.o b/MDK-ARM/AutoGuideStick/startup_stm32h563xx.o new file mode 100644 index 0000000..3396022 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/startup_stm32h563xx.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal.d new file mode 100644 index 0000000..8eae2de --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal.o new file mode 100644 index 0000000..0743026 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.d new file mode 100644 index 0000000..2d84462 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_cortex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_cortex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.o new file mode 100644 index 0000000..4b9080c Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_cortex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.d new file mode 100644 index 0000000..b665eaa --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_dma.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.o new file mode 100644 index 0000000..faee8a9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.d new file mode 100644 index 0000000..cd46fb4 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_dma_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_dma_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.o new file mode 100644 index 0000000..b943b29 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_dma_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.d new file mode 100644 index 0000000..3966a98 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_exti.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_exti.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.o new file mode 100644 index 0000000..632eb65 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_exti.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.d new file mode 100644 index 0000000..b7a8e76 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_flash.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.o new file mode 100644 index 0000000..0ef0217 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.d new file mode 100644 index 0000000..b7604eb --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_flash_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_flash_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.o new file mode 100644 index 0000000..94381c4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_flash_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.d new file mode 100644 index 0000000..0ce5b13 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_gpio.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_gpio.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.o new file mode 100644 index 0000000..740b32b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_gpio.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.d new file mode 100644 index 0000000..6894ca0 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.d @@ -0,0 +1,32 @@ +autoguidestick/stm32h5xx_hal_icache.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_icache.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + d:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_icache.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.o new file mode 100644 index 0000000..de41f2e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_icache.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.d new file mode 100644 index 0000000..ec45142 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.d @@ -0,0 +1,32 @@ +autoguidestick/stm32h5xx_hal_msp.o: ..\Core\Src\stm32h5xx_hal_msp.c \ + ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.o new file mode 100644 index 0000000..7f666c4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_msp.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.d new file mode 100644 index 0000000..f3a7e1c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_pwr.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.o new file mode 100644 index 0000000..53d2f90 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.d new file mode 100644 index 0000000..faa1906 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_pwr_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_pwr_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.o new file mode 100644 index 0000000..a16e60a Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_pwr_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.d new file mode 100644 index 0000000..aec1187 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_rcc.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.o new file mode 100644 index 0000000..d8f2538 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.d new file mode 100644 index 0000000..055d5fa --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_rcc_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_rcc_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.o new file mode 100644 index 0000000..f694d44 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_rcc_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.d new file mode 100644 index 0000000..33fd8ad --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_tim.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.o new file mode 100644 index 0000000..78155a0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.d new file mode 100644 index 0000000..adf1ebf --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_tim_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_tim_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.o new file mode 100644 index 0000000..4d9dbe8 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_tim_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.d new file mode 100644 index 0000000..2f26680 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_timebase_tim.o: \ + ..\Core\Src\stm32h5xx_hal_timebase_tim.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.o new file mode 100644 index 0000000..4e4d31b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_timebase_tim.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.d new file mode 100644 index 0000000..c4208a2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_uart.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.o new file mode 100644 index 0000000..6351a7b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.d b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.d new file mode 100644 index 0000000..4cd3694 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_hal_uart_ex.o: \ + ..\Drivers\STM32H5xx_HAL_Driver\Src\stm32h5xx_hal_uart_ex.c \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.o b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.o new file mode 100644 index 0000000..86ffa99 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_hal_uart_ex.o differ diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_it.d b/MDK-ARM/AutoGuideStick/stm32h5xx_it.d new file mode 100644 index 0000000..638bf29 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/stm32h5xx_it.d @@ -0,0 +1,33 @@ +autoguidestick/stm32h5xx_it.o: ..\Core\Src\stm32h5xx_it.c \ + ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h \ + ..\Core\Inc\stm32h5xx_it.h diff --git a/MDK-ARM/AutoGuideStick/stm32h5xx_it.o b/MDK-ARM/AutoGuideStick/stm32h5xx_it.o new file mode 100644 index 0000000..5b1793f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/stm32h5xx_it.o differ diff --git a/MDK-ARM/AutoGuideStick/system_stm32h5xx.d b/MDK-ARM/AutoGuideStick/system_stm32h5xx.d new file mode 100644 index 0000000..94515a8 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/system_stm32h5xx.d @@ -0,0 +1,32 @@ +autoguidestick/system_stm32h5xx.o: ..\Core\Src\system_stm32h5xx.c \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/system_stm32h5xx.o b/MDK-ARM/AutoGuideStick/system_stm32h5xx.o new file mode 100644 index 0000000..69c89f4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/system_stm32h5xx.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_allocate.d b/MDK-ARM/AutoGuideStick/tx_block_allocate.d new file mode 100644 index 0000000..92ba39a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_allocate.d @@ -0,0 +1,8 @@ +autoguidestick/tx_block_allocate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_allocate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_allocate.o b/MDK-ARM/AutoGuideStick/tx_block_allocate.o new file mode 100644 index 0000000..95beb80 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_allocate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.d b/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.d new file mode 100644 index 0000000..c2bbe2a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_block_pool_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.o b/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.o new file mode 100644 index 0000000..65db627 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_create.d b/MDK-ARM/AutoGuideStick/tx_block_pool_create.d new file mode 100644 index 0000000..1b185a7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_block_pool_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_create.o b/MDK-ARM/AutoGuideStick/tx_block_pool_create.o new file mode 100644 index 0000000..caadfc4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_delete.d b/MDK-ARM/AutoGuideStick/tx_block_pool_delete.d new file mode 100644 index 0000000..3fcf57e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_block_pool_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_delete.o b/MDK-ARM/AutoGuideStick/tx_block_pool_delete.o new file mode 100644 index 0000000..2dbb345 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.d b/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.d new file mode 100644 index 0000000..1532fa7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_block_pool_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.o b/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.o new file mode 100644 index 0000000..e27a965 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.d b/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.d new file mode 100644 index 0000000..44de1ff --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_block_pool_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.o b/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.o new file mode 100644 index 0000000..567537b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.d b/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.d new file mode 100644 index 0000000..f19b8c9 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.d @@ -0,0 +1,9 @@ +autoguidestick/tx_block_pool_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_pool_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.o b/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.o new file mode 100644 index 0000000..4d6b3f0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_pool_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_block_release.d b/MDK-ARM/AutoGuideStick/tx_block_release.d new file mode 100644 index 0000000..366a8fc --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_block_release.d @@ -0,0 +1,9 @@ +autoguidestick/tx_block_release.o: \ + ..\Middlewares\ST\threadx\common\src\tx_block_release.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_block_release.o b/MDK-ARM/AutoGuideStick/tx_block_release.o new file mode 100644 index 0000000..74d7a46 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_block_release.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_allocate.d b/MDK-ARM/AutoGuideStick/tx_byte_allocate.d new file mode 100644 index 0000000..8b44ef6 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_allocate.d @@ -0,0 +1,8 @@ +autoguidestick/tx_byte_allocate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_allocate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_allocate.o b/MDK-ARM/AutoGuideStick/tx_byte_allocate.o new file mode 100644 index 0000000..bb3061e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_allocate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.d new file mode 100644 index 0000000..e53176b --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_byte_pool_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.o new file mode 100644 index 0000000..5818500 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_create.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_create.d new file mode 100644 index 0000000..a29f72f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_byte_pool_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_create.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_create.o new file mode 100644 index 0000000..3bf34be Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.d new file mode 100644 index 0000000..c55a9af --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_byte_pool_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.o new file mode 100644 index 0000000..c743be8 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.d new file mode 100644 index 0000000..37dbae2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_byte_pool_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.o new file mode 100644 index 0000000..323b00e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.d new file mode 100644 index 0000000..bd2a130 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_byte_pool_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.o new file mode 100644 index 0000000..bf90f4d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.d new file mode 100644 index 0000000..b016cf6 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.d @@ -0,0 +1,9 @@ +autoguidestick/tx_byte_pool_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.o new file mode 100644 index 0000000..6357370 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_search.d b/MDK-ARM/AutoGuideStick/tx_byte_pool_search.d new file mode 100644 index 0000000..ece656d --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_pool_search.d @@ -0,0 +1,8 @@ +autoguidestick/tx_byte_pool_search.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_pool_search.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_pool_search.o b/MDK-ARM/AutoGuideStick/tx_byte_pool_search.o new file mode 100644 index 0000000..d19ee96 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_pool_search.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_byte_release.d b/MDK-ARM/AutoGuideStick/tx_byte_release.d new file mode 100644 index 0000000..715976d --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_byte_release.d @@ -0,0 +1,9 @@ +autoguidestick/tx_byte_release.o: \ + ..\Middlewares\ST\threadx\common\src\tx_byte_release.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_byte_release.o b/MDK-ARM/AutoGuideStick/tx_byte_release.o new file mode 100644 index 0000000..0924d2d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_byte_release.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.d b/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.d new file mode 100644 index 0000000..3947417 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_event_flags_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.o b/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.o new file mode 100644 index 0000000..3ed8cf8 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_create.d b/MDK-ARM/AutoGuideStick/tx_event_flags_create.d new file mode 100644 index 0000000..3eb33b7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_event_flags_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_create.o b/MDK-ARM/AutoGuideStick/tx_event_flags_create.o new file mode 100644 index 0000000..01bf2e7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_delete.d b/MDK-ARM/AutoGuideStick/tx_event_flags_delete.d new file mode 100644 index 0000000..507b9b1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_event_flags_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_delete.o b/MDK-ARM/AutoGuideStick/tx_event_flags_delete.o new file mode 100644 index 0000000..df65045 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_get.d b/MDK-ARM/AutoGuideStick/tx_event_flags_get.d new file mode 100644 index 0000000..4a4cffb --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_get.d @@ -0,0 +1,9 @@ +autoguidestick/tx_event_flags_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_get.o b/MDK-ARM/AutoGuideStick/tx_event_flags_get.o new file mode 100644 index 0000000..0a09589 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.d b/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.d new file mode 100644 index 0000000..47ce9c9 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_event_flags_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.o b/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.o new file mode 100644 index 0000000..4842d8f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.d b/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.d new file mode 100644 index 0000000..435a1eb --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_event_flags_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.o b/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.o new file mode 100644 index 0000000..318a344 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_set.d b/MDK-ARM/AutoGuideStick/tx_event_flags_set.d new file mode 100644 index 0000000..08f71eb --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_set.d @@ -0,0 +1,9 @@ +autoguidestick/tx_event_flags_set.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_set.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_set.o b/MDK-ARM/AutoGuideStick/tx_event_flags_set.o new file mode 100644 index 0000000..746b42d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_set.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.d b/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.d new file mode 100644 index 0000000..6df99f6 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.d @@ -0,0 +1,8 @@ +autoguidestick/tx_event_flags_set_notify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_event_flags_set_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.o b/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.o new file mode 100644 index 0000000..a400eeb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_event_flags_set_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_high_level.d b/MDK-ARM/AutoGuideStick/tx_initialize_high_level.d new file mode 100644 index 0000000..0a4c22f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_initialize_high_level.d @@ -0,0 +1,16 @@ +autoguidestick/tx_initialize_high_level.o: \ + ..\Middlewares\ST\threadx\common\src\tx_initialize_high_level.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_high_level.o b/MDK-ARM/AutoGuideStick/tx_initialize_high_level.o new file mode 100644 index 0000000..b997b15 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_initialize_high_level.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.d b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.d new file mode 100644 index 0000000..af73828 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.d @@ -0,0 +1,9 @@ +autoguidestick/tx_initialize_kernel_enter.o: \ + ..\Middlewares\ST\threadx\common\src\tx_initialize_kernel_enter.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.o b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.o new file mode 100644 index 0000000..30c0dfa Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_enter.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.d b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.d new file mode 100644 index 0000000..30d0aae --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_initialize_kernel_setup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_initialize_kernel_setup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.o b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.o new file mode 100644 index 0000000..7eb194a Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_initialize_kernel_setup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_initialize_low_level.o b/MDK-ARM/AutoGuideStick/tx_initialize_low_level.o new file mode 100644 index 0000000..67e4dce Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_initialize_low_level.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.d b/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.d new file mode 100644 index 0000000..ee27a28 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_mutex_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.o b/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.o new file mode 100644 index 0000000..f116b6e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_create.d b/MDK-ARM/AutoGuideStick/tx_mutex_create.d new file mode 100644 index 0000000..bde7c05 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_create.d @@ -0,0 +1,9 @@ +autoguidestick/tx_mutex_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_create.o b/MDK-ARM/AutoGuideStick/tx_mutex_create.o new file mode 100644 index 0000000..a499efb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_delete.d b/MDK-ARM/AutoGuideStick/tx_mutex_delete.d new file mode 100644 index 0000000..fc6667a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_mutex_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_delete.o b/MDK-ARM/AutoGuideStick/tx_mutex_delete.o new file mode 100644 index 0000000..32c45e4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_get.d b/MDK-ARM/AutoGuideStick/tx_mutex_get.d new file mode 100644 index 0000000..df16ec2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_get.d @@ -0,0 +1,9 @@ +autoguidestick/tx_mutex_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_get.o b/MDK-ARM/AutoGuideStick/tx_mutex_get.o new file mode 100644 index 0000000..0772b49 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_info_get.d b/MDK-ARM/AutoGuideStick/tx_mutex_info_get.d new file mode 100644 index 0000000..a500251 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_mutex_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_info_get.o b/MDK-ARM/AutoGuideStick/tx_mutex_info_get.o new file mode 100644 index 0000000..6dc369f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_initialize.d b/MDK-ARM/AutoGuideStick/tx_mutex_initialize.d new file mode 100644 index 0000000..e6c719b --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_mutex_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_initialize.o b/MDK-ARM/AutoGuideStick/tx_mutex_initialize.o new file mode 100644 index 0000000..5793f12 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.d b/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.d new file mode 100644 index 0000000..6adc748 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.d @@ -0,0 +1,9 @@ +autoguidestick/tx_mutex_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.o b/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.o new file mode 100644 index 0000000..3a38e26 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.d b/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.d new file mode 100644 index 0000000..3c2a9c0 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.d @@ -0,0 +1,8 @@ +autoguidestick/tx_mutex_priority_change.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_priority_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.o b/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.o new file mode 100644 index 0000000..8576d60 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_priority_change.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_put.d b/MDK-ARM/AutoGuideStick/tx_mutex_put.d new file mode 100644 index 0000000..7d8cc4e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_mutex_put.d @@ -0,0 +1,9 @@ +autoguidestick/tx_mutex_put.o: \ + ..\Middlewares\ST\threadx\common\src\tx_mutex_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/tx_mutex_put.o b/MDK-ARM/AutoGuideStick/tx_mutex_put.o new file mode 100644 index 0000000..185376c Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_mutex_put.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_cleanup.d b/MDK-ARM/AutoGuideStick/tx_queue_cleanup.d new file mode 100644 index 0000000..328899e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_queue_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_cleanup.o b/MDK-ARM/AutoGuideStick/tx_queue_cleanup.o new file mode 100644 index 0000000..56ae74d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_create.d b/MDK-ARM/AutoGuideStick/tx_queue_create.d new file mode 100644 index 0000000..708e2bd --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_queue_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_create.o b/MDK-ARM/AutoGuideStick/tx_queue_create.o new file mode 100644 index 0000000..4f0b0e7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_delete.d b/MDK-ARM/AutoGuideStick/tx_queue_delete.d new file mode 100644 index 0000000..fcf4abf --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_delete.o b/MDK-ARM/AutoGuideStick/tx_queue_delete.o new file mode 100644 index 0000000..31e6102 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_flush.d b/MDK-ARM/AutoGuideStick/tx_queue_flush.d new file mode 100644 index 0000000..cbf1421 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_flush.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_flush.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_flush.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_flush.o b/MDK-ARM/AutoGuideStick/tx_queue_flush.o new file mode 100644 index 0000000..20b9ea9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_flush.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_front_send.d b/MDK-ARM/AutoGuideStick/tx_queue_front_send.d new file mode 100644 index 0000000..6ae16f1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_front_send.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_front_send.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_front_send.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_front_send.o b/MDK-ARM/AutoGuideStick/tx_queue_front_send.o new file mode 100644 index 0000000..d323015 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_front_send.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_info_get.d b/MDK-ARM/AutoGuideStick/tx_queue_info_get.d new file mode 100644 index 0000000..bda0694 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_queue_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_info_get.o b/MDK-ARM/AutoGuideStick/tx_queue_info_get.o new file mode 100644 index 0000000..ce01d50 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_initialize.d b/MDK-ARM/AutoGuideStick/tx_queue_initialize.d new file mode 100644 index 0000000..b7809c0 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_queue_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_initialize.o b/MDK-ARM/AutoGuideStick/tx_queue_initialize.o new file mode 100644 index 0000000..377b951 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_prioritize.d b/MDK-ARM/AutoGuideStick/tx_queue_prioritize.d new file mode 100644 index 0000000..a6a63d8 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_prioritize.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_prioritize.o b/MDK-ARM/AutoGuideStick/tx_queue_prioritize.o new file mode 100644 index 0000000..4507cc5 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_receive.d b/MDK-ARM/AutoGuideStick/tx_queue_receive.d new file mode 100644 index 0000000..38d24f8 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_receive.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_receive.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_receive.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_receive.o b/MDK-ARM/AutoGuideStick/tx_queue_receive.o new file mode 100644 index 0000000..e5cf8aa Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_receive.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_send.d b/MDK-ARM/AutoGuideStick/tx_queue_send.d new file mode 100644 index 0000000..5acdff2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_send.d @@ -0,0 +1,9 @@ +autoguidestick/tx_queue_send.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_send.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_send.o b/MDK-ARM/AutoGuideStick/tx_queue_send.o new file mode 100644 index 0000000..3f06d81 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_send.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_queue_send_notify.d b/MDK-ARM/AutoGuideStick/tx_queue_send_notify.d new file mode 100644 index 0000000..effef5f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_queue_send_notify.d @@ -0,0 +1,8 @@ +autoguidestick/tx_queue_send_notify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_queue_send_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/tx_queue_send_notify.o b/MDK-ARM/AutoGuideStick/tx_queue_send_notify.o new file mode 100644 index 0000000..607d85f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_queue_send_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.d b/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.d new file mode 100644 index 0000000..a8e2916 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.d @@ -0,0 +1,9 @@ +autoguidestick/tx_semaphore_ceiling_put.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_ceiling_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.o b/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.o new file mode 100644 index 0000000..8373e0a Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_ceiling_put.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.d b/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.d new file mode 100644 index 0000000..4689276 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.d @@ -0,0 +1,8 @@ +autoguidestick/tx_semaphore_cleanup.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_cleanup.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.o b/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.o new file mode 100644 index 0000000..ea61474 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_cleanup.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_create.d b/MDK-ARM/AutoGuideStick/tx_semaphore_create.d new file mode 100644 index 0000000..dab52d7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_semaphore_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_create.o b/MDK-ARM/AutoGuideStick/tx_semaphore_create.o new file mode 100644 index 0000000..a2f3603 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_delete.d b/MDK-ARM/AutoGuideStick/tx_semaphore_delete.d new file mode 100644 index 0000000..425a54f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_delete.d @@ -0,0 +1,9 @@ +autoguidestick/tx_semaphore_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_delete.o b/MDK-ARM/AutoGuideStick/tx_semaphore_delete.o new file mode 100644 index 0000000..4b4fda9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_get.d b/MDK-ARM/AutoGuideStick/tx_semaphore_get.d new file mode 100644 index 0000000..651860f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_get.d @@ -0,0 +1,9 @@ +autoguidestick/tx_semaphore_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_get.o b/MDK-ARM/AutoGuideStick/tx_semaphore_get.o new file mode 100644 index 0000000..f332e23 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.d b/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.d new file mode 100644 index 0000000..b5e2a71 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_semaphore_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.o b/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.o new file mode 100644 index 0000000..dd55c6f Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.d b/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.d new file mode 100644 index 0000000..80dccf1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.d @@ -0,0 +1,7 @@ +autoguidestick/tx_semaphore_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.o b/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.o new file mode 100644 index 0000000..d11a0b4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.d b/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.d new file mode 100644 index 0000000..fd9833c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.d @@ -0,0 +1,9 @@ +autoguidestick/tx_semaphore_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.o b/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.o new file mode 100644 index 0000000..7968dc3 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_put.d b/MDK-ARM/AutoGuideStick/tx_semaphore_put.d new file mode 100644 index 0000000..3cc6309 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_put.d @@ -0,0 +1,9 @@ +autoguidestick/tx_semaphore_put.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_put.o b/MDK-ARM/AutoGuideStick/tx_semaphore_put.o new file mode 100644 index 0000000..ab3a51a Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_put.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.d b/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.d new file mode 100644 index 0000000..d6f532f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.d @@ -0,0 +1,8 @@ +autoguidestick/tx_semaphore_put_notify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_semaphore_put_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.o b/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.o new file mode 100644 index 0000000..7997928 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_semaphore_put_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_context_restore.o b/MDK-ARM/AutoGuideStick/tx_thread_context_restore.o new file mode 100644 index 0000000..df5eb33 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_context_restore.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_context_save.o b/MDK-ARM/AutoGuideStick/tx_thread_context_save.o new file mode 100644 index 0000000..3f8eaa2 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_context_save.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_create.d b/MDK-ARM/AutoGuideStick/tx_thread_create.d new file mode 100644 index 0000000..4f84228 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_create.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_create.o b/MDK-ARM/AutoGuideStick/tx_thread_create.o new file mode 100644 index 0000000..cfbaba3 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_delete.d b/MDK-ARM/AutoGuideStick/tx_thread_delete.d new file mode 100644 index 0000000..960c7a4 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_delete.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_delete.o b/MDK-ARM/AutoGuideStick/tx_thread_delete.o new file mode 100644 index 0000000..43eeab6 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.d b/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.d new file mode 100644 index 0000000..91cb2ee --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_entry_exit_notify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_entry_exit_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.o b/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.o new file mode 100644 index 0000000..27a61b1 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_entry_exit_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_identify.d b/MDK-ARM/AutoGuideStick/tx_thread_identify.d new file mode 100644 index 0000000..b675852 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_identify.d @@ -0,0 +1,7 @@ +autoguidestick/tx_thread_identify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_identify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_identify.o b/MDK-ARM/AutoGuideStick/tx_thread_identify.o new file mode 100644 index 0000000..243f496 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_identify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_info_get.d b/MDK-ARM/AutoGuideStick/tx_thread_info_get.d new file mode 100644 index 0000000..4b8788b --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_info_get.o b/MDK-ARM/AutoGuideStick/tx_thread_info_get.o new file mode 100644 index 0000000..f9843ef Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_initialize.d b/MDK-ARM/AutoGuideStick/tx_thread_initialize.d new file mode 100644 index 0000000..fa8cdf8 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_initialize.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_initialize.o b/MDK-ARM/AutoGuideStick/tx_thread_initialize.o new file mode 100644 index 0000000..d41846b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_interrupt_control.o b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_control.o new file mode 100644 index 0000000..179f694 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_control.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_interrupt_disable.o b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_disable.o new file mode 100644 index 0000000..0096cf5 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_disable.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_interrupt_restore.o b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_restore.o new file mode 100644 index 0000000..cb036f4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_interrupt_restore.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.d b/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.d new file mode 100644 index 0000000..48c8349 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_preemption_change.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_preemption_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.o b/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.o new file mode 100644 index 0000000..7b32029 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_preemption_change.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_priority_change.d b/MDK-ARM/AutoGuideStick/tx_thread_priority_change.d new file mode 100644 index 0000000..d89f64e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_priority_change.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_priority_change.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_priority_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_priority_change.o b/MDK-ARM/AutoGuideStick/tx_thread_priority_change.o new file mode 100644 index 0000000..f79cee0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_priority_change.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_relinquish.d b/MDK-ARM/AutoGuideStick/tx_thread_relinquish.d new file mode 100644 index 0000000..bdd2388 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_relinquish.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_relinquish.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_relinquish.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_relinquish.o b/MDK-ARM/AutoGuideStick/tx_thread_relinquish.o new file mode 100644 index 0000000..452e9f9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_relinquish.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_reset.d b/MDK-ARM/AutoGuideStick/tx_thread_reset.d new file mode 100644 index 0000000..5be7e82 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_reset.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_reset.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_reset.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_reset.o b/MDK-ARM/AutoGuideStick/tx_thread_reset.o new file mode 100644 index 0000000..1e93936 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_reset.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_resume.d b/MDK-ARM/AutoGuideStick/tx_thread_resume.d new file mode 100644 index 0000000..dc09bbd --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_resume.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_resume.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_resume.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_resume.o b/MDK-ARM/AutoGuideStick/tx_thread_resume.o new file mode 100644 index 0000000..e90fb51 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_resume.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_schedule.o b/MDK-ARM/AutoGuideStick/tx_thread_schedule.o new file mode 100644 index 0000000..057a601 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_schedule.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.d b/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.d new file mode 100644 index 0000000..8c79a43 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.d @@ -0,0 +1,7 @@ +autoguidestick/tx_thread_shell_entry.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_shell_entry.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.o b/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.o new file mode 100644 index 0000000..96e05e2 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_shell_entry.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_sleep.d b/MDK-ARM/AutoGuideStick/tx_thread_sleep.d new file mode 100644 index 0000000..74b39d0 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_sleep.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_sleep.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_sleep.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_sleep.o b/MDK-ARM/AutoGuideStick/tx_thread_sleep.o new file mode 100644 index 0000000..9768729 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_sleep.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.d b/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.d new file mode 100644 index 0000000..503309c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.d @@ -0,0 +1,7 @@ +autoguidestick/tx_thread_stack_analyze.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_stack_analyze.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.o b/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.o new file mode 100644 index 0000000..a783f24 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_stack_analyze.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_build.o b/MDK-ARM/AutoGuideStick/tx_thread_stack_build.o new file mode 100644 index 0000000..9fe38c4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_stack_build.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.d b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.d new file mode 100644 index 0000000..c664453 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.d @@ -0,0 +1,7 @@ +autoguidestick/tx_thread_stack_error_handler.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_stack_error_handler.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.o b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.o new file mode 100644 index 0000000..a480301 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_handler.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.d b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.d new file mode 100644 index 0000000..d4387aa --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_stack_error_notify.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_stack_error_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.o b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.o new file mode 100644 index 0000000..7915d03 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_stack_error_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_suspend.d b/MDK-ARM/AutoGuideStick/tx_thread_suspend.d new file mode 100644 index 0000000..5e71f21 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_suspend.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_suspend.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_suspend.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_suspend.o b/MDK-ARM/AutoGuideStick/tx_thread_suspend.o new file mode 100644 index 0000000..e3eb649 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_suspend.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.d b/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.d new file mode 100644 index 0000000..67f8c93 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.d @@ -0,0 +1,7 @@ +autoguidestick/tx_thread_system_preempt_check.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_system_preempt_check.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.o b/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.o new file mode 100644 index 0000000..1851abe Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_system_preempt_check.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_resume.d b/MDK-ARM/AutoGuideStick/tx_thread_system_resume.d new file mode 100644 index 0000000..febb26c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_system_resume.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_system_resume.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_system_resume.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_resume.o b/MDK-ARM/AutoGuideStick/tx_thread_system_resume.o new file mode 100644 index 0000000..61252cc Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_system_resume.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_return.o b/MDK-ARM/AutoGuideStick/tx_thread_system_return.o new file mode 100644 index 0000000..cb121f5 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_system_return.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.d b/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.d new file mode 100644 index 0000000..7e5605e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_system_suspend.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_system_suspend.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.o b/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.o new file mode 100644 index 0000000..ca63800 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_system_suspend.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_terminate.d b/MDK-ARM/AutoGuideStick/tx_thread_terminate.d new file mode 100644 index 0000000..f5f2797 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_terminate.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_terminate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_terminate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_terminate.o b/MDK-ARM/AutoGuideStick/tx_thread_terminate.o new file mode 100644 index 0000000..fde2d0d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_terminate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_time_slice.d b/MDK-ARM/AutoGuideStick/tx_thread_time_slice.d new file mode 100644 index 0000000..a8fdd81 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_time_slice.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_time_slice.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_time_slice.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_time_slice.o b/MDK-ARM/AutoGuideStick/tx_thread_time_slice.o new file mode 100644 index 0000000..98e67a7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_time_slice.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.d b/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.d new file mode 100644 index 0000000..c7dadff --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.d @@ -0,0 +1,9 @@ +autoguidestick/tx_thread_time_slice_change.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_time_slice_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.o b/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.o new file mode 100644 index 0000000..cb5ba53 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_time_slice_change.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_timeout.d b/MDK-ARM/AutoGuideStick/tx_thread_timeout.d new file mode 100644 index 0000000..3d3f886 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_timeout.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_timeout.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_timeout.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_timeout.o b/MDK-ARM/AutoGuideStick/tx_thread_timeout.o new file mode 100644 index 0000000..a07e570 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_timeout.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.d b/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.d new file mode 100644 index 0000000..f1fe127 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.d @@ -0,0 +1,8 @@ +autoguidestick/tx_thread_wait_abort.o: \ + ..\Middlewares\ST\threadx\common\src\tx_thread_wait_abort.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.o b/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.o new file mode 100644 index 0000000..4230e5c Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_thread_wait_abort.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_time_get.d b/MDK-ARM/AutoGuideStick/tx_time_get.d new file mode 100644 index 0000000..188afea --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_time_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_time_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_time_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_time_get.o b/MDK-ARM/AutoGuideStick/tx_time_get.o new file mode 100644 index 0000000..ebb6d09 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_time_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_time_set.d b/MDK-ARM/AutoGuideStick/tx_time_set.d new file mode 100644 index 0000000..208550e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_time_set.d @@ -0,0 +1,8 @@ +autoguidestick/tx_time_set.o: \ + ..\Middlewares\ST\threadx\common\src\tx_time_set.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_time_set.o b/MDK-ARM/AutoGuideStick/tx_time_set.o new file mode 100644 index 0000000..7a88201 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_time_set.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_activate.d b/MDK-ARM/AutoGuideStick/tx_timer_activate.d new file mode 100644 index 0000000..62a2c55 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_activate.d @@ -0,0 +1,7 @@ +autoguidestick/tx_timer_activate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_activate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_activate.o b/MDK-ARM/AutoGuideStick/tx_timer_activate.o new file mode 100644 index 0000000..50ba3e0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_activate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_change.d b/MDK-ARM/AutoGuideStick/tx_timer_change.d new file mode 100644 index 0000000..8701c1a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_change.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_change.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_change.o b/MDK-ARM/AutoGuideStick/tx_timer_change.o new file mode 100644 index 0000000..47233cb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_change.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_create.d b/MDK-ARM/AutoGuideStick/tx_timer_create.d new file mode 100644 index 0000000..10e62c5 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_create.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_create.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_create.o b/MDK-ARM/AutoGuideStick/tx_timer_create.o new file mode 100644 index 0000000..d6a543c Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_create.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_deactivate.d b/MDK-ARM/AutoGuideStick/tx_timer_deactivate.d new file mode 100644 index 0000000..c3ed0b8 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_deactivate.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_deactivate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_deactivate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_deactivate.o b/MDK-ARM/AutoGuideStick/tx_timer_deactivate.o new file mode 100644 index 0000000..78a6431 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_deactivate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_delete.d b/MDK-ARM/AutoGuideStick/tx_timer_delete.d new file mode 100644 index 0000000..bb24270 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_delete.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_delete.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_delete.o b/MDK-ARM/AutoGuideStick/tx_timer_delete.o new file mode 100644 index 0000000..b4554bf Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.d b/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.d new file mode 100644 index 0000000..aa5d6f1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_expiration_process.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_expiration_process.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.o b/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.o new file mode 100644 index 0000000..f631168 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_expiration_process.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_info_get.d b/MDK-ARM/AutoGuideStick/tx_timer_info_get.d new file mode 100644 index 0000000..fb8fd6e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_info_get.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_trace.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_info_get.o b/MDK-ARM/AutoGuideStick/tx_timer_info_get.o new file mode 100644 index 0000000..4a169dc Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_initialize.d b/MDK-ARM/AutoGuideStick/tx_timer_initialize.d new file mode 100644 index 0000000..d7a2b9a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_initialize.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_initialize.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_initialize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_initialize.o b/MDK-ARM/AutoGuideStick/tx_timer_initialize.o new file mode 100644 index 0000000..45c6717 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_initialize.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_interrupt.o b/MDK-ARM/AutoGuideStick/tx_timer_interrupt.o new file mode 100644 index 0000000..6b4f72e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_interrupt.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_system_activate.d b/MDK-ARM/AutoGuideStick/tx_timer_system_activate.d new file mode 100644 index 0000000..6e2ef49 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_system_activate.d @@ -0,0 +1,7 @@ +autoguidestick/tx_timer_system_activate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_system_activate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_system_activate.o b/MDK-ARM/AutoGuideStick/tx_timer_system_activate.o new file mode 100644 index 0000000..ea9ee33 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_system_activate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.d b/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.d new file mode 100644 index 0000000..0dd6035 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.d @@ -0,0 +1,7 @@ +autoguidestick/tx_timer_system_deactivate.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_system_deactivate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.o b/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.o new file mode 100644 index 0000000..3021a20 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_system_deactivate.o differ diff --git a/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.d b/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.d new file mode 100644 index 0000000..17faddf --- /dev/null +++ b/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.d @@ -0,0 +1,8 @@ +autoguidestick/tx_timer_thread_entry.o: \ + ..\Middlewares\ST\threadx\common\src\tx_timer_thread_entry.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.o b/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.o new file mode 100644 index 0000000..9240f78 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/tx_timer_thread_entry.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_allocate.d b/MDK-ARM/AutoGuideStick/txe_block_allocate.d new file mode 100644 index 0000000..00fbe27 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_allocate.d @@ -0,0 +1,9 @@ +autoguidestick/txe_block_allocate.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_allocate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_allocate.o b/MDK-ARM/AutoGuideStick/txe_block_allocate.o new file mode 100644 index 0000000..bfd2232 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_allocate.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_create.d b/MDK-ARM/AutoGuideStick/txe_block_pool_create.d new file mode 100644 index 0000000..534b32b --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_pool_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_block_pool_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_pool_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_create.o b/MDK-ARM/AutoGuideStick/txe_block_pool_create.o new file mode 100644 index 0000000..160bba7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_pool_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_delete.d b/MDK-ARM/AutoGuideStick/txe_block_pool_delete.d new file mode 100644 index 0000000..84c613d --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_pool_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_block_pool_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_pool_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_delete.o b/MDK-ARM/AutoGuideStick/txe_block_pool_delete.o new file mode 100644 index 0000000..fdd448d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_pool_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.d b/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.d new file mode 100644 index 0000000..641e31c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_block_pool_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_pool_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.o b/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.o new file mode 100644 index 0000000..eb3fcbe Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_pool_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.d b/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.d new file mode 100644 index 0000000..65676e7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.d @@ -0,0 +1,7 @@ +autoguidestick/txe_block_pool_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_pool_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.o b/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.o new file mode 100644 index 0000000..51eca93 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_pool_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_block_release.d b/MDK-ARM/AutoGuideStick/txe_block_release.d new file mode 100644 index 0000000..0823fe9 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_block_release.d @@ -0,0 +1,7 @@ +autoguidestick/txe_block_release.o: \ + ..\Middlewares\ST\threadx\common\src\txe_block_release.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_block_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_block_release.o b/MDK-ARM/AutoGuideStick/txe_block_release.o new file mode 100644 index 0000000..f112fb4 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_block_release.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_allocate.d b/MDK-ARM/AutoGuideStick/txe_byte_allocate.d new file mode 100644 index 0000000..ca9eed2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_allocate.d @@ -0,0 +1,10 @@ +autoguidestick/txe_byte_allocate.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_allocate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_allocate.o b/MDK-ARM/AutoGuideStick/txe_byte_allocate.o new file mode 100644 index 0000000..9594a4b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_allocate.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_create.d b/MDK-ARM/AutoGuideStick/txe_byte_pool_create.d new file mode 100644 index 0000000..31aba9c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_pool_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_byte_pool_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_pool_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_create.o b/MDK-ARM/AutoGuideStick/txe_byte_pool_create.o new file mode 100644 index 0000000..103323b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_pool_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.d b/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.d new file mode 100644 index 0000000..ed69cec --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_byte_pool_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_pool_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.o b/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.o new file mode 100644 index 0000000..e79d0b0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_pool_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.d b/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.d new file mode 100644 index 0000000..17d73f7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_byte_pool_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_pool_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.o b/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.o new file mode 100644 index 0000000..0c83c9b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_pool_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.d b/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.d new file mode 100644 index 0000000..87f089a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.d @@ -0,0 +1,7 @@ +autoguidestick/txe_byte_pool_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_pool_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.o b/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.o new file mode 100644 index 0000000..93e9749 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_pool_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_byte_release.d b/MDK-ARM/AutoGuideStick/txe_byte_release.d new file mode 100644 index 0000000..5433fb9 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_byte_release.d @@ -0,0 +1,10 @@ +autoguidestick/txe_byte_release.o: \ + ..\Middlewares\ST\threadx\common\src\txe_byte_release.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_byte_pool.h diff --git a/MDK-ARM/AutoGuideStick/txe_byte_release.o b/MDK-ARM/AutoGuideStick/txe_byte_release.o new file mode 100644 index 0000000..b7103a9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_byte_release.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_create.d b/MDK-ARM/AutoGuideStick/txe_event_flags_create.d new file mode 100644 index 0000000..9d2bfae --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_event_flags_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_create.o b/MDK-ARM/AutoGuideStick/txe_event_flags_create.o new file mode 100644 index 0000000..0598257 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_delete.d b/MDK-ARM/AutoGuideStick/txe_event_flags_delete.d new file mode 100644 index 0000000..807cca2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_event_flags_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_delete.o b/MDK-ARM/AutoGuideStick/txe_event_flags_delete.o new file mode 100644 index 0000000..5b49e8d Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_get.d b/MDK-ARM/AutoGuideStick/txe_event_flags_get.d new file mode 100644 index 0000000..ff438f6 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_get.d @@ -0,0 +1,9 @@ +autoguidestick/txe_event_flags_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_get.o b/MDK-ARM/AutoGuideStick/txe_event_flags_get.o new file mode 100644 index 0000000..3efd1eb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.d b/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.d new file mode 100644 index 0000000..e92b083 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_event_flags_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.o b/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.o new file mode 100644 index 0000000..9815d52 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_set.d b/MDK-ARM/AutoGuideStick/txe_event_flags_set.d new file mode 100644 index 0000000..900464a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_set.d @@ -0,0 +1,7 @@ +autoguidestick/txe_event_flags_set.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_set.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_set.o b/MDK-ARM/AutoGuideStick/txe_event_flags_set.o new file mode 100644 index 0000000..1862791 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_set.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.d b/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.d new file mode 100644 index 0000000..03180d2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.d @@ -0,0 +1,7 @@ +autoguidestick/txe_event_flags_set_notify.o: \ + ..\Middlewares\ST\threadx\common\src\txe_event_flags_set_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_event_flags.h diff --git a/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.o b/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.o new file mode 100644 index 0000000..538f3b2 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_event_flags_set_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_create.d b/MDK-ARM/AutoGuideStick/txe_mutex_create.d new file mode 100644 index 0000000..4f1e624 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_mutex_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_create.o b/MDK-ARM/AutoGuideStick/txe_mutex_create.o new file mode 100644 index 0000000..703f941 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_delete.d b/MDK-ARM/AutoGuideStick/txe_mutex_delete.d new file mode 100644 index 0000000..cabea8e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_mutex_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_delete.o b/MDK-ARM/AutoGuideStick/txe_mutex_delete.o new file mode 100644 index 0000000..a577311 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_get.d b/MDK-ARM/AutoGuideStick/txe_mutex_get.d new file mode 100644 index 0000000..5d5e618 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_get.d @@ -0,0 +1,10 @@ +autoguidestick/txe_mutex_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_get.o b/MDK-ARM/AutoGuideStick/txe_mutex_get.o new file mode 100644 index 0000000..ee73cc7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_info_get.d b/MDK-ARM/AutoGuideStick/txe_mutex_info_get.d new file mode 100644 index 0000000..8523f11 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_mutex_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_info_get.o b/MDK-ARM/AutoGuideStick/txe_mutex_info_get.o new file mode 100644 index 0000000..e36a84e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.d b/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.d new file mode 100644 index 0000000..c2a0680 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.d @@ -0,0 +1,7 @@ +autoguidestick/txe_mutex_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.o b/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.o new file mode 100644 index 0000000..2dd79f3 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_put.d b/MDK-ARM/AutoGuideStick/txe_mutex_put.d new file mode 100644 index 0000000..e782926 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_mutex_put.d @@ -0,0 +1,9 @@ +autoguidestick/txe_mutex_put.o: \ + ..\Middlewares\ST\threadx\common\src\txe_mutex_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_mutex.h diff --git a/MDK-ARM/AutoGuideStick/txe_mutex_put.o b/MDK-ARM/AutoGuideStick/txe_mutex_put.o new file mode 100644 index 0000000..f889047 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_mutex_put.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_create.d b/MDK-ARM/AutoGuideStick/txe_queue_create.d new file mode 100644 index 0000000..2a176f2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_queue_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_create.o b/MDK-ARM/AutoGuideStick/txe_queue_create.o new file mode 100644 index 0000000..f7852a2 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_delete.d b/MDK-ARM/AutoGuideStick/txe_queue_delete.d new file mode 100644 index 0000000..8f0f04f --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_queue_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_delete.o b/MDK-ARM/AutoGuideStick/txe_queue_delete.o new file mode 100644 index 0000000..cb410d0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_flush.d b/MDK-ARM/AutoGuideStick/txe_queue_flush.d new file mode 100644 index 0000000..bf9b9cd --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_flush.d @@ -0,0 +1,7 @@ +autoguidestick/txe_queue_flush.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_flush.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_flush.o b/MDK-ARM/AutoGuideStick/txe_queue_flush.o new file mode 100644 index 0000000..4ea058e Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_flush.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_front_send.d b/MDK-ARM/AutoGuideStick/txe_queue_front_send.d new file mode 100644 index 0000000..38ed470 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_front_send.d @@ -0,0 +1,9 @@ +autoguidestick/txe_queue_front_send.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_front_send.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_front_send.o b/MDK-ARM/AutoGuideStick/txe_queue_front_send.o new file mode 100644 index 0000000..cd0b233 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_front_send.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_info_get.d b/MDK-ARM/AutoGuideStick/txe_queue_info_get.d new file mode 100644 index 0000000..f98fea3 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_queue_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_info_get.o b/MDK-ARM/AutoGuideStick/txe_queue_info_get.o new file mode 100644 index 0000000..65135fb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_prioritize.d b/MDK-ARM/AutoGuideStick/txe_queue_prioritize.d new file mode 100644 index 0000000..83d8c30 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_prioritize.d @@ -0,0 +1,7 @@ +autoguidestick/txe_queue_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_prioritize.o b/MDK-ARM/AutoGuideStick/txe_queue_prioritize.o new file mode 100644 index 0000000..3556257 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_receive.d b/MDK-ARM/AutoGuideStick/txe_queue_receive.d new file mode 100644 index 0000000..649af3a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_receive.d @@ -0,0 +1,9 @@ +autoguidestick/txe_queue_receive.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_receive.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_receive.o b/MDK-ARM/AutoGuideStick/txe_queue_receive.o new file mode 100644 index 0000000..971c1c7 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_receive.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_send.d b/MDK-ARM/AutoGuideStick/txe_queue_send.d new file mode 100644 index 0000000..bc659e7 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_send.d @@ -0,0 +1,9 @@ +autoguidestick/txe_queue_send.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_send.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_send.o b/MDK-ARM/AutoGuideStick/txe_queue_send.o new file mode 100644 index 0000000..5942dde Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_send.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_queue_send_notify.d b/MDK-ARM/AutoGuideStick/txe_queue_send_notify.d new file mode 100644 index 0000000..c38ec16 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_queue_send_notify.d @@ -0,0 +1,7 @@ +autoguidestick/txe_queue_send_notify.o: \ + ..\Middlewares\ST\threadx\common\src\txe_queue_send_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_queue.h diff --git a/MDK-ARM/AutoGuideStick/txe_queue_send_notify.o b/MDK-ARM/AutoGuideStick/txe_queue_send_notify.o new file mode 100644 index 0000000..7c93e72 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_queue_send_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.d b/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.d new file mode 100644 index 0000000..e58c69b --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.d @@ -0,0 +1,7 @@ +autoguidestick/txe_semaphore_ceiling_put.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_ceiling_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.o b/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.o new file mode 100644 index 0000000..ddab2e1 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_ceiling_put.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_create.d b/MDK-ARM/AutoGuideStick/txe_semaphore_create.d new file mode 100644 index 0000000..cae9b2e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_create.d @@ -0,0 +1,10 @@ +autoguidestick/txe_semaphore_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_create.o b/MDK-ARM/AutoGuideStick/txe_semaphore_create.o new file mode 100644 index 0000000..f430155 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_delete.d b/MDK-ARM/AutoGuideStick/txe_semaphore_delete.d new file mode 100644 index 0000000..be3c04c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_delete.d @@ -0,0 +1,9 @@ +autoguidestick/txe_semaphore_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_delete.o b/MDK-ARM/AutoGuideStick/txe_semaphore_delete.o new file mode 100644 index 0000000..6363669 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_get.d b/MDK-ARM/AutoGuideStick/txe_semaphore_get.d new file mode 100644 index 0000000..12128b5 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_get.d @@ -0,0 +1,9 @@ +autoguidestick/txe_semaphore_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_get.o b/MDK-ARM/AutoGuideStick/txe_semaphore_get.o new file mode 100644 index 0000000..8b81358 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.d b/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.d new file mode 100644 index 0000000..128406a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_semaphore_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.o b/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.o new file mode 100644 index 0000000..873fd03 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.d b/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.d new file mode 100644 index 0000000..60743bf --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.d @@ -0,0 +1,7 @@ +autoguidestick/txe_semaphore_prioritize.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_prioritize.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.o b/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.o new file mode 100644 index 0000000..c42c962 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_prioritize.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_put.d b/MDK-ARM/AutoGuideStick/txe_semaphore_put.d new file mode 100644 index 0000000..9605697 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_put.d @@ -0,0 +1,7 @@ +autoguidestick/txe_semaphore_put.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_put.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_put.o b/MDK-ARM/AutoGuideStick/txe_semaphore_put.o new file mode 100644 index 0000000..603f586 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_put.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.d b/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.d new file mode 100644 index 0000000..e31ab9e --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.d @@ -0,0 +1,7 @@ +autoguidestick/txe_semaphore_put_notify.o: \ + ..\Middlewares\ST\threadx\common\src\txe_semaphore_put_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_semaphore.h diff --git a/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.o b/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.o new file mode 100644 index 0000000..04a4ca0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_semaphore_put_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_create.d b/MDK-ARM/AutoGuideStick/txe_thread_create.d new file mode 100644 index 0000000..55ca5f3 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_create.d @@ -0,0 +1,9 @@ +autoguidestick/txe_thread_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_create.o b/MDK-ARM/AutoGuideStick/txe_thread_create.o new file mode 100644 index 0000000..e6f77ee Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_delete.d b/MDK-ARM/AutoGuideStick/txe_thread_delete.d new file mode 100644 index 0000000..1bfdd56 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_delete.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_delete.o b/MDK-ARM/AutoGuideStick/txe_thread_delete.o new file mode 100644 index 0000000..73de0ab Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.d b/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.d new file mode 100644 index 0000000..f5b9e1d --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_entry_exit_notify.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_entry_exit_notify.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.o b/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.o new file mode 100644 index 0000000..7e3c8b8 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_entry_exit_notify.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_info_get.d b/MDK-ARM/AutoGuideStick/txe_thread_info_get.d new file mode 100644 index 0000000..dbb9382 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_info_get.o b/MDK-ARM/AutoGuideStick/txe_thread_info_get.o new file mode 100644 index 0000000..2e5e592 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.d b/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.d new file mode 100644 index 0000000..8768ca1 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_preemption_change.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_preemption_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.o b/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.o new file mode 100644 index 0000000..539f1c9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_preemption_change.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_priority_change.d b/MDK-ARM/AutoGuideStick/txe_thread_priority_change.d new file mode 100644 index 0000000..4b4cc42 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_priority_change.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_priority_change.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_priority_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_priority_change.o b/MDK-ARM/AutoGuideStick/txe_thread_priority_change.o new file mode 100644 index 0000000..8a2c9f0 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_priority_change.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_relinquish.d b/MDK-ARM/AutoGuideStick/txe_thread_relinquish.d new file mode 100644 index 0000000..c091bbd --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_relinquish.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_relinquish.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_relinquish.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_relinquish.o b/MDK-ARM/AutoGuideStick/txe_thread_relinquish.o new file mode 100644 index 0000000..4d1ee17 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_relinquish.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_reset.d b/MDK-ARM/AutoGuideStick/txe_thread_reset.d new file mode 100644 index 0000000..aa192ca --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_reset.d @@ -0,0 +1,8 @@ +autoguidestick/txe_thread_reset.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_reset.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_reset.o b/MDK-ARM/AutoGuideStick/txe_thread_reset.o new file mode 100644 index 0000000..133f945 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_reset.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_resume.d b/MDK-ARM/AutoGuideStick/txe_thread_resume.d new file mode 100644 index 0000000..c7fbdd2 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_resume.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_resume.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_resume.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_resume.o b/MDK-ARM/AutoGuideStick/txe_thread_resume.o new file mode 100644 index 0000000..1eee919 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_resume.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_suspend.d b/MDK-ARM/AutoGuideStick/txe_thread_suspend.d new file mode 100644 index 0000000..9f599a4 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_suspend.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_suspend.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_suspend.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_suspend.o b/MDK-ARM/AutoGuideStick/txe_thread_suspend.o new file mode 100644 index 0000000..ffe5294 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_suspend.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_terminate.d b/MDK-ARM/AutoGuideStick/txe_thread_terminate.d new file mode 100644 index 0000000..8ef506c --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_terminate.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_terminate.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_terminate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_terminate.o b/MDK-ARM/AutoGuideStick/txe_thread_terminate.o new file mode 100644 index 0000000..0dd2758 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_terminate.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.d b/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.d new file mode 100644 index 0000000..1eeb610 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_time_slice_change.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_time_slice_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.o b/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.o new file mode 100644 index 0000000..e484784 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_time_slice_change.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.d b/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.d new file mode 100644 index 0000000..5024510 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.d @@ -0,0 +1,7 @@ +autoguidestick/txe_thread_wait_abort.o: \ + ..\Middlewares\ST\threadx\common\src\txe_thread_wait_abort.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h diff --git a/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.o b/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.o new file mode 100644 index 0000000..d4d00eb Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_thread_wait_abort.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_activate.d b/MDK-ARM/AutoGuideStick/txe_timer_activate.d new file mode 100644 index 0000000..4ed5fe4 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_activate.d @@ -0,0 +1,7 @@ +autoguidestick/txe_timer_activate.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_activate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_activate.o b/MDK-ARM/AutoGuideStick/txe_timer_activate.o new file mode 100644 index 0000000..37a7277 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_activate.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_change.d b/MDK-ARM/AutoGuideStick/txe_timer_change.d new file mode 100644 index 0000000..a8f788a --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_change.d @@ -0,0 +1,9 @@ +autoguidestick/txe_timer_change.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_change.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_change.o b/MDK-ARM/AutoGuideStick/txe_timer_change.o new file mode 100644 index 0000000..46ed4f9 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_change.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_create.d b/MDK-ARM/AutoGuideStick/txe_timer_create.d new file mode 100644 index 0000000..5499aa4 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_create.d @@ -0,0 +1,9 @@ +autoguidestick/txe_timer_create.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_create.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_initialize.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_create.o b/MDK-ARM/AutoGuideStick/txe_timer_create.o new file mode 100644 index 0000000..5c2112b Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_create.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_deactivate.d b/MDK-ARM/AutoGuideStick/txe_timer_deactivate.d new file mode 100644 index 0000000..936d8bb --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_deactivate.d @@ -0,0 +1,7 @@ +autoguidestick/txe_timer_deactivate.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_deactivate.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_deactivate.o b/MDK-ARM/AutoGuideStick/txe_timer_deactivate.o new file mode 100644 index 0000000..41e9a19 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_deactivate.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_delete.d b/MDK-ARM/AutoGuideStick/txe_timer_delete.d new file mode 100644 index 0000000..cabcf73 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_delete.d @@ -0,0 +1,8 @@ +autoguidestick/txe_timer_delete.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_delete.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_thread.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_delete.o b/MDK-ARM/AutoGuideStick/txe_timer_delete.o new file mode 100644 index 0000000..ba42b65 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_delete.o differ diff --git a/MDK-ARM/AutoGuideStick/txe_timer_info_get.d b/MDK-ARM/AutoGuideStick/txe_timer_info_get.d new file mode 100644 index 0000000..ec76c11 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/txe_timer_info_get.d @@ -0,0 +1,7 @@ +autoguidestick/txe_timer_info_get.o: \ + ..\Middlewares\ST\threadx\common\src\txe_timer_info_get.c \ + ..\Middlewares\ST\threadx\common\inc\tx_api.h \ + ..\Middlewares\ST\threadx\ports\cortex_m33\ac6\inc\tx_port.h \ + ..\Core\Inc\tx_user.h D:\keil5\ARM\ARMCLANG\include\stdlib.h \ + D:\keil5\ARM\ARMCLANG\include\string.h \ + ..\Middlewares\ST\threadx\common\inc\tx_timer.h diff --git a/MDK-ARM/AutoGuideStick/txe_timer_info_get.o b/MDK-ARM/AutoGuideStick/txe_timer_info_get.o new file mode 100644 index 0000000..9b2e369 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/txe_timer_info_get.o differ diff --git a/MDK-ARM/AutoGuideStick/usart.d b/MDK-ARM/AutoGuideStick/usart.d new file mode 100644 index 0000000..d745a95 --- /dev/null +++ b/MDK-ARM/AutoGuideStick/usart.d @@ -0,0 +1,32 @@ +autoguidestick/usart.o: ..\Core\Src\usart.c ..\Core\Inc\usart.h \ + ..\Core\Inc\main.h ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal.h \ + ..\Core\Inc\stm32h5xx_hal_conf.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_def.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h5xx.h \ + D:\keil5\ARM\ARMCLANG\include\math.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\stm32h563xx.h \ + ..\Drivers\CMSIS\Include\core_cm33.h \ + D:\keil5\ARM\ARMCLANG\include\stdint.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_version.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_compiler.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\cmsis_armclang.h \ + D:\advance_stick\AutoGuideStick\Drivers\CMSIS\Include\mpu_armv8.h \ + ..\Drivers\CMSIS\Device\ST\STM32H5xx\Include\system_stm32h5xx.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h \ + D:\keil5\ARM\ARMCLANG\include\stddef.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_rcc_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_gpio_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_dma_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_cortex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_flash_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_pwr_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_tim_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_uart_ex.h \ + ..\Drivers\STM32H5xx_HAL_Driver\Inc\stm32h5xx_hal_exti.h diff --git a/MDK-ARM/AutoGuideStick/usart.o b/MDK-ARM/AutoGuideStick/usart.o new file mode 100644 index 0000000..0151318 Binary files /dev/null and b/MDK-ARM/AutoGuideStick/usart.o differ diff --git a/MDK-ARM/DebugConfig/AutoGuideStick_STM32H563ZITx_1.0.0.dbgconf b/MDK-ARM/DebugConfig/AutoGuideStick_STM32H563ZITx_1.0.0.dbgconf new file mode 100644 index 0000000..5a720dd --- /dev/null +++ b/MDK-ARM/DebugConfig/AutoGuideStick_STM32H563ZITx_1.0.0.dbgconf @@ -0,0 +1,128 @@ +// File: STM32H562xx_H563xx_H573xx.dbgconf +// Version: 1.0.1 +// Note: refer to STM32H563/H573 and STM32H562 reference manual (RM0481) +// refer to STM32H562xx STM32H563xx STM32H573xx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// +DbgMCU_CR = 0x00000006; + +// Debug MCU APB1L freeze register (DBGMCU_APB1LFZR) +// Reserved bits must be kept at reset value +// DBG_I2C3_STOP I2C3 SMBUS timeout is frozen while CPU is in debug mode +// DBG_I2C2_STOP I2C2 SMBUS timeout is frozen while CPU is in debug mode +// DBG_I2C1_STOP I2C1 SMBUS timeout is frozen while CPU is in debug mode +// DBG_IWDG_STOP Debug independent watchdog is frozen while CPU is in debug mode +// DBG_WWDG_STOP Debug window watchdog is frozen while CPU is in debug mode +// DBG_TIM14_STOP TIM14 is frozen while CPU is in debug mode +// DBG_TIM13_STOP TIM13 is frozen while CPU is in debug mode +// DBG_TIM12_STOP TIM12 is frozen while CPU is in debug mode +// DBG_TIM7_STOP TIM7 is frozen while CPU is in debug mode +// DBG_TIM6_STOP TIM6 is frozen while CPU is in debug mode +// DBG_TIM5_STOP TIM5 is frozen while CPU is in debug mode +// DBG_TIM4_STOP TIM4 is frozen while CPU is in debug mode +// DBG_TIM3_STOP TIM3 is frozen while CPU is in debug mode +// DBG_TIM2_STOP TIM2 is frozen while CPU is in debug mode +// +DbgMCU_APB1L_Fz = 0x00000000; + +// Debug MCU APB1H freeze register (DBGMCU_APB1HFZR) +// Reserved bits must be kept at reset value +// DBG_LPTIM2_STOP LPTIM2 is frozen while CPU is in debug mode +// +DbgMCU_APB1H_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2FZR) +// Reserved bits must be kept at reset value +// DBG_TIM17_STOP TIM17 is frozen while CPU is in debug mode +// DBG_TIM16_STOP TIM16 is frozen while CPU is in debug mode +// DBG_TIM15_STOP TIM15 is frozen while CPU is in debug mode +// DBG_TIM8_STOP TIM8 is frozen while CPU is in debug mode +// DBG_TIM1_STOP TIM1 is frozen while CPU is in debug mode +// +DbgMCU_APB2_Fz = 0x00000000; + +// Debug MCU APB3 freeze register (DBGMCU_APB3FZR) +// Reserved bits must be kept at reset value +// DBG_RTC_STOP RTC is frozen while CPU is in debug mode. +// DBG_LPTIM6_STOP LPTIM6 is frozen while CPU is in debug mode +// DBG_LPTIM5_STOP LPTIM5 is frozen while CPU is in debug mode +// DBG_LPTIM4_STOP LPTIM4 is frozen while CPU is in debug mode +// DBG_LPTIM3_STOP LPTIM3 is frozen while CPU is in debug mode +// DBG_LPTIM1_STOP LPTIM1 is frozen while CPU is in debug mode +// DBG_I2C4_STOP I2C3 is frozen while CPU is in debug mode +// DBG_I2C3_STOP I2C3 is frozen while CPU is in debug mode +// +DbgMCU_APB3_Fz = 0x00000000; + +// Debug MCU AHB1 freeze register (DBGMCU_AHB1FZR) +// Reserved bits must be kept at reset value +// DBG_GPDMA2_15_STOP GPDMA2 channel 15 is frozen while CPU is in debug mode +// DBG_GPDMA2_14_STOP GPDMA2 channel 14 is frozen while CPU is in debug mode +// DBG_GPDMA2_13_STOP GPDMA2 channel 13 is frozen while CPU is in debug mode +// DBG_GPDMA2_12_STOP GPDMA2 channel 12 is frozen while CPU is in debug mode +// DBG_GPDMA2_11_STOP GPDMA2 channel 11 is frozen while CPU is in debug mode +// DBG_GPDMA2_10_STOP GPDMA2 channel 10 is frozen while CPU is in debug mode +// DBG_GPDMA2_9_STOP GPDMA2 channel 9 is frozen while CPU is in debug mode +// DBG_GPDMA2_8_STOP GPDMA2 channel 8 is frozen while CPU is in debug mode +// DBG_GPDMA2_7_STOP GPDMA2 channel 7 is frozen while CPU is in debug mode +// DBG_GPDMA2_6_STOP GPDMA2 channel 6 is frozen while CPU is in debug mode +// DBG_GPDMA2_5_STOP GPDMA2 channel 5 is frozen while CPU is in debug mode +// DBG_GPDMA2_4_STOP GPDMA2 channel 4 is frozen while CPU is in debug mode +// DBG_GPDMA2_3_STOP GPDMA2 channel 3 is frozen while CPU is in debug mode +// DBG_GPDMA2_2_STOP GPDMA2 channel 2 is frozen while CPU is in debug mode +// DBG_GPDMA2_1_STOP GPDMA2 channel 1 is frozen while CPU is in debug mode +// DBG_GPDMA2_0_STOP GPDMA2 channel 0 is frozen while CPU is in debug mode +// DBG_GPDMA1_15_STOP GPDMA1 channel 15 is frozen while CPU is in debug mode +// DBG_GPDMA1_14_STOP GPDMA1 channel 14 is frozen while CPU is in debug mode +// DBG_GPDMA1_13_STOP GPDMA1 channel 13 is frozen while CPU is in debug mode +// DBG_GPDMA1_12_STOP GPDMA1 channel 12 is frozen while CPU is in debug mode +// DBG_GPDMA1_11_STOP GPDMA1 channel 11 is frozen while CPU is in debug mode +// DBG_GPDMA1_10_STOP GPDMA1 channel 10 is frozen while CPU is in debug mode +// DBG_GPDMA1_9_STOP GPDMA1 channel 9 is frozen while CPU is in debug mode +// DBG_GPDMA1_8_STOP GPDMA1 channel 8 is frozen while CPU is in debug mode +// DBG_GPDMA1_7_STOP GPDMA1 channel 7 is frozen while CPU is in debug mode +// DBG_GPDMA1_6_STOP GPDMA1 channel 6 is frozen while CPU is in debug mode +// DBG_GPDMA1_5_STOP GPDMA1 channel 5 is frozen while CPU is in debug mode +// DBG_GPDMA1_4_STOP GPDMA1 channel 4 is frozen while CPU is in debug mode +// DBG_GPDMA1_3_STOP GPDMA1 channel 3 is frozen while CPU is in debug mode +// DBG_GPDMA1_2_STOP GPDMA1 channel 2 is frozen while CPU is in debug mode +// DBG_GPDMA1_1_STOP GPDMA1 channel 1 is frozen while CPU is in debug mode +// DBG_GPDMA1_0_STOP GPDMA1 channel 0 is frozen while CPU is in debug mode +// +DbgMCU_AHB1_Fz = 0x00000000; + +// TPIU Pin Routing +// TRACECLK +// ETM Trace Clock +// <0x00040002=> Pin PE2 +// TRACED0 +// ETM Trace Data 0 +// <0x0006000D=> Pin PG13 +// <0x00040003=> Pin PE3 +// <0x00020001=> Pin PC1 +// TRACED1 +// ETM Trace Data 1 +// <0x0006000E=> Pin PG14 +// <0x00040004=> Pin PE4 +// <0x00020008=> Pin PC8 +// TRACED2 +// ETM Trace Data 2 +// <0x00040005=> Pin PE5 +// <0x00030002=> Pin PD2 +// TRACED3 +// ETM Trace Data 3 +// <0x0002000C=> Pin PC12 +// <0x00040006=> Pin PE6 +// +TraceClk_Pin = 0x00040002; +TraceD0_Pin = 0x00040003; +TraceD1_Pin = 0x00040004; +TraceD2_Pin = 0x00040005; +TraceD3_Pin = 0x00040006; + +// <<< end of configuration section >>> diff --git a/MDK-ARM/RTE/_AutoGuideStick/RTE_Components.h b/MDK-ARM/RTE/_AutoGuideStick/RTE_Components.h new file mode 100644 index 0000000..280145a --- /dev/null +++ b/MDK-ARM/RTE/_AutoGuideStick/RTE_Components.h @@ -0,0 +1,21 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'AutoGuideStick' + * Target: 'AutoGuideStick' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32h5xx.h" + + + +#endif /* RTE_COMPONENTS_H */ diff --git a/fun/HCBle.c b/fun/HCBle.c new file mode 100644 index 0000000..f506af0 --- /dev/null +++ b/fun/HCBle.c @@ -0,0 +1,68 @@ +#include "HCBle.h" + +// 外部变量引入区 +extern UART_HandleTypeDef huart1; + +/* +变量定义区 +*/ +char HC_Send_Data[128]; +uint8_t HC_Recevie[RX_DataSize]; // 蓝牙接收缓存 +volatile uint16_t rx_index = 0; //作为接收字符串指针 +volatile uint8_t data_received = 0; // 0 --- 未接收 1 --- 接收 + +uint8_t rx_data; //接收字符 + + +// 发送数据 +void HCBle_SendData(char *p,...) +{ + va_list ap; + va_start(ap,p); + vsprintf(HC_Send_Data,p,ap); + va_end(ap); +// 编译控制 +#ifdef DEBUG_EN + // 信息输出接口 + HAL_UART_Transmit(&huart1,(uint8_t *)HC_Send_Data,strlen(HC_Send_Data),1); +// HAL_UART_Transmi(&huart1,(uint8_t *)formatBuf,strlen(formatBuf),1); +// 对于没有使用中断的串口发送,是需要加入一个阻塞的 +#endif + +} +// 对于发送数据 可以加入一个DMA + + + + +// 蓝牙数据接收 +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + if(huart->Instance == USART1) + { + if(rx_data == '\n') + { + if(rx_index > 0) + { + HC_Recevie[rx_index] = '\0'; + data_received = 1; + rx_index = 0; //我认为接收完字符串后 把字符传给别的处理后 需要清除这里的字符串 memset + }else if(rx_index < RX_DataSize - 1) + { + + }else + { + rx_index = 0; //缓冲区溢出,重置 + memset(HC_Recevie,'\0',RX_DataSize); + } + } + + HAL_UART_Receive_IT(huart,&rx_data,1); + } +} + + + +// 接下来就是定义 Json数据处理 以及 发送数据给手机App + + diff --git a/fun/HCBle.h b/fun/HCBle.h new file mode 100644 index 0000000..6856e32 --- /dev/null +++ b/fun/HCBle.h @@ -0,0 +1,27 @@ +#ifndef __HCBLE_H +#define __HCBLE_H + +#include "headfile.h" + +// HCBle 相关数据定义 +typedef struct +{ + int LeftSpeed; + int RightSpeed; +}MotorCommand; + +typedef struct +{ + float lat; + float lon; + float angle; +}LocationData; + + + +#define DEBUG_EN 1 +#define RX_DataSize 128 + +extern uint8_t rx_data; + +#endif \ No newline at end of file diff --git a/fun/headfile.h b/fun/headfile.h new file mode 100644 index 0000000..2cbf0da --- /dev/null +++ b/fun/headfile.h @@ -0,0 +1,16 @@ +#ifndef __HEADFILE_H +#define __HEADFILE_H + +#include "app_threadx.h" +#include "main.h" +#include "memorymap.h" +#include "usart.h" +#include "gpio.h" + +#include "stdio.h" +#include "stdlib.h" +#include "stdarg.h" + +#include "HCBle.h" + +#endif \ No newline at end of file