generated from Template/H563ZI-HAL-CMake-Template
798 lines
24 KiB
C
798 lines
24 KiB
C
/**
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******************************************************************************
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* @file stm32h5xx_ll_crs.h
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* @author MCD Application Team
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* @brief Header file of CRS LL module.
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef STM32H5xx_LL_CRS_H
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#define STM32H5xx_LL_CRS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "stm32h5xx.h"
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/** @addtogroup STM32H5xx_LL_Driver
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* @{
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*/
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#if defined(CRS)
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/** @defgroup CRS_LL CRS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/** @defgroup CRS_LL_Private_Constants CRS Private Constants
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* @{
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*/
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/* Defines used for the bit position in the register and perform offsets*/
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#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */
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#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */
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#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants
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* @{
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*/
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/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines
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* @brief Flags defines which can be used with LL_CRS_ReadReg function
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* @{
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*/
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#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF
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#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF
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#define LL_CRS_ISR_ERRF CRS_ISR_ERRF
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#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF
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#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR
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#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS
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#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_IT IT Defines
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* @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions
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* @{
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*/
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#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE
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#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE
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#define LL_CRS_CR_ERRIE CRS_CR_ERRIE
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#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider
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* @{
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*/
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#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */
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#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
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#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
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#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
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#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
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#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
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#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
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#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source
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* @{
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*/
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#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */
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#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
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#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity
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* @{
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*/
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#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */
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#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction
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* @{
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*/
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#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */
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#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values
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* @{
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*/
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/**
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* @brief Reset value of the RELOAD field
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* @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz
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* and a synchronization signal frequency of 1 kHz (SOF signal from USB)
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*/
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#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU
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/**
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* @brief Reset value of Frequency error limit.
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*/
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#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U
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/**
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* @brief Reset value of the HSI48 Calibration field
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* @note The default value is 32, which corresponds to the middle of the trimming interval.
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* The trimming step is specified in the product datasheet.
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* A higher TRIM value corresponds to a higher output frequency.
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*/
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#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000020U
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros
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* @{
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*/
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/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros
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* @{
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*/
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/**
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* @brief Write a value in CRS register
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* @param __INSTANCE__ CRS Instance
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* @param __REG__ Register to be written
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* @param __VALUE__ Value to be written in the register
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* @retval None
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*/
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#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
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/**
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* @brief Read a value in CRS register
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* @param __INSTANCE__ CRS Instance
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* @param __REG__ Register to be read
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* @retval Register value
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*/
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#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
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/**
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* @}
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*/
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/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload
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* @{
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*/
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/**
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* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
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* @note The RELOAD value should be selected according to the ratio between
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* the target frequency and the frequency of the synchronization source after
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* prescaling. It is then decreased by one in order to reach the expected
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* synchronization on the zero value. The formula is the following:
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* RELOAD = (fTARGET / fSYNC) -1
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* @param __FTARGET__ Target frequency (value in Hz)
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* @param __FSYNC__ Synchronization signal frequency (value in Hz)
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* @retval Reload value (in Hz)
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*/
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#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions
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* @{
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*/
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/** @defgroup CRS_LL_EF_Configuration Configuration
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* @{
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*/
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/**
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* @brief Enable Frequency error counter
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* @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified
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* @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)
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{
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SET_BIT(CRS->CR, CRS_CR_CEN);
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}
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/**
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* @brief Disable Frequency error counter
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* @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)
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{
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CLEAR_BIT(CRS->CR, CRS_CR_CEN);
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}
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/**
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* @brief Check if Frequency error counter is enabled or not
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* @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)
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{
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return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);
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}
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/**
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* @brief Enable Automatic trimming counter
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* @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)
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{
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SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
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}
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/**
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* @brief Disable Automatic trimming counter
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* @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)
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{
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CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);
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}
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/**
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* @brief Check if Automatic trimming is enabled or not
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* @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming
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* @retval State of bit (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)
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{
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return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);
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}
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/**
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* @brief Set HSI48 oscillator smooth trimming
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* @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only
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* @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming
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* @param Value a number between Min_Data = 0 and Max_Data = 63
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* @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)
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{
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MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM);
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}
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/**
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* @brief Get HSI48 oscillator smooth trimming
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* @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming
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* @retval a number between Min_Data = 0 and Max_Data = 63
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)
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{
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return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM);
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}
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/**
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* @brief Set counter reload value
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* @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter
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* @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF
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* @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT
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* Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)
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{
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MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);
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}
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/**
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* @brief Get counter reload value
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* @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter
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* @retval a number between Min_Data = 0 and Max_Data = 0xFFFF
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)
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{
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return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));
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}
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/**
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* @brief Set frequency error limit
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* @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit
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* @param Value a number between Min_Data = 0 and Max_Data = 255
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* @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)
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{
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MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM);
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}
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/**
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* @brief Get frequency error limit
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* @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit
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* @retval A number between Min_Data = 0 and Max_Data = 255
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)
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{
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return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM);
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}
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/**
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* @brief Set division factor for SYNC signal
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* @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider
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* @param Divider This parameter can be one of the following values:
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* @arg @ref LL_CRS_SYNC_DIV_1
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* @arg @ref LL_CRS_SYNC_DIV_2
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* @arg @ref LL_CRS_SYNC_DIV_4
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* @arg @ref LL_CRS_SYNC_DIV_8
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* @arg @ref LL_CRS_SYNC_DIV_16
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* @arg @ref LL_CRS_SYNC_DIV_32
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* @arg @ref LL_CRS_SYNC_DIV_64
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* @arg @ref LL_CRS_SYNC_DIV_128
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)
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{
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MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);
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}
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/**
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* @brief Get division factor for SYNC signal
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* @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CRS_SYNC_DIV_1
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* @arg @ref LL_CRS_SYNC_DIV_2
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* @arg @ref LL_CRS_SYNC_DIV_4
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* @arg @ref LL_CRS_SYNC_DIV_8
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* @arg @ref LL_CRS_SYNC_DIV_16
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* @arg @ref LL_CRS_SYNC_DIV_32
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* @arg @ref LL_CRS_SYNC_DIV_64
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* @arg @ref LL_CRS_SYNC_DIV_128
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)
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{
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return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));
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}
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/**
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* @brief Set SYNC signal source
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* @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource
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* @param Source This parameter can be one of the following values:
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* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
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* @arg @ref LL_CRS_SYNC_SOURCE_LSE
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* @arg @ref LL_CRS_SYNC_SOURCE_USB
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)
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{
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MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);
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}
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/**
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* @brief Get SYNC signal source
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* @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CRS_SYNC_SOURCE_GPIO
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* @arg @ref LL_CRS_SYNC_SOURCE_LSE
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* @arg @ref LL_CRS_SYNC_SOURCE_USB
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)
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{
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return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));
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}
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/**
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* @brief Set input polarity for the SYNC signal source
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* @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity
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* @param Polarity This parameter can be one of the following values:
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* @arg @ref LL_CRS_SYNC_POLARITY_RISING
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* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
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* @retval None
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*/
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__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)
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{
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MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);
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}
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/**
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* @brief Get input polarity for the SYNC signal source
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* @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity
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* @retval Returned value can be one of the following values:
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* @arg @ref LL_CRS_SYNC_POLARITY_RISING
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* @arg @ref LL_CRS_SYNC_POLARITY_FALLING
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*/
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__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)
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{
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return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));
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}
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/**
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* @brief Configure CRS for the synchronization
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* @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n
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* CFGR RELOAD LL_CRS_ConfigSynchronization\n
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* CFGR FELIM LL_CRS_ConfigSynchronization\n
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* CFGR SYNCDIV LL_CRS_ConfigSynchronization\n
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* CFGR SYNCSRC LL_CRS_ConfigSynchronization\n
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* CFGR SYNCPOL LL_CRS_ConfigSynchronization
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* @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63
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* @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF
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* @param ReloadValue a number between Min_Data = 0 and Max_Data = 255
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* @param Settings This parameter can be a combination of the following values:
|
|
* @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8
|
|
* or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64
|
|
* or @ref LL_CRS_SYNC_DIV_128
|
|
* @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB
|
|
* @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue,
|
|
uint32_t ReloadValue, uint32_t Settings)
|
|
{
|
|
MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);
|
|
MODIFY_REG(CRS->CFGR,
|
|
CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,
|
|
ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CRS_LL_EF_CRS_Management CRS_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Generate software SYNC event
|
|
* @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_SWSYNC);
|
|
}
|
|
|
|
/**
|
|
* @brief Get the frequency error direction latched in the time of the last
|
|
* SYNC event
|
|
* @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection
|
|
* @retval Returned value can be one of the following values:
|
|
* @arg @ref LL_CRS_FREQ_ERROR_DIR_UP
|
|
* @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)
|
|
{
|
|
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));
|
|
}
|
|
|
|
/**
|
|
* @brief Get the frequency error counter value latched in the time of the last SYNC event
|
|
* @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture
|
|
* @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)
|
|
{
|
|
return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Check if SYNC event OK signal occurred or not
|
|
* @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if SYNC warning signal occurred or not
|
|
* @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Synchronization or trimming error signal occurred or not
|
|
* @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Expected SYNC signal occurred or not
|
|
* @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if SYNC error signal occurred or not
|
|
* @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if SYNC missed error signal occurred or not
|
|
* @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Trimming overflow or underflow occurred or not
|
|
* @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)
|
|
{
|
|
return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the SYNC event OK flag
|
|
* @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)
|
|
{
|
|
WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear the SYNC warning flag
|
|
* @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)
|
|
{
|
|
WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also
|
|
* the ERR flag
|
|
* @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)
|
|
{
|
|
WRITE_REG(CRS->ICR, CRS_ICR_ERRC);
|
|
}
|
|
|
|
/**
|
|
* @brief Clear Expected SYNC flag
|
|
* @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)
|
|
{
|
|
WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/** @defgroup CRS_LL_EF_IT_Management IT_Management
|
|
* @{
|
|
*/
|
|
|
|
/**
|
|
* @brief Enable SYNC event OK interrupt
|
|
* @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable SYNC event OK interrupt
|
|
* @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)
|
|
{
|
|
CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if SYNC event OK interrupt is enabled or not
|
|
* @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)
|
|
{
|
|
return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable SYNC warning interrupt
|
|
* @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable SYNC warning interrupt
|
|
* @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)
|
|
{
|
|
CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if SYNC warning interrupt is enabled or not
|
|
* @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)
|
|
{
|
|
return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Synchronization or trimming error interrupt
|
|
* @rmtoll CR ERRIE LL_CRS_EnableIT_ERR
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Synchronization or trimming error interrupt
|
|
* @rmtoll CR ERRIE LL_CRS_DisableIT_ERR
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)
|
|
{
|
|
CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Synchronization or trimming error interrupt is enabled or not
|
|
* @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)
|
|
{
|
|
return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @brief Enable Expected SYNC interrupt
|
|
* @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)
|
|
{
|
|
SET_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Disable Expected SYNC interrupt
|
|
* @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)
|
|
{
|
|
CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);
|
|
}
|
|
|
|
/**
|
|
* @brief Check if Expected SYNC interrupt is enabled or not
|
|
* @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC
|
|
* @retval State of bit (1 or 0).
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)
|
|
{
|
|
return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#if defined(USE_FULL_LL_DRIVER)
|
|
/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions
|
|
* @{
|
|
*/
|
|
|
|
ErrorStatus LL_CRS_DeInit(void);
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
#endif /* USE_FULL_LL_DRIVER */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#endif /* defined(CRS) */
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* STM32H5xx_LL_CRS_H */
|
|
|