generated from Template/H563ZI-HAL-CMake-Template
402 lines
15 KiB
C
402 lines
15 KiB
C
/**
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******************************************************************************
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* @file system_stm32h5xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32h5xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the HSI (64 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32h5xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | HSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 64000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 64000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB3 Prescaler | 1
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*-----------------------------------------------------------------------------
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* HSI Division factor | 1
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*-----------------------------------------------------------------------------
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* PLL1_SRC | No clock
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*-----------------------------------------------------------------------------
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* PLL1_M | Prescaler disabled
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*-----------------------------------------------------------------------------
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* PLL1_N | 129
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*-----------------------------------------------------------------------------
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* PLL1_P | 2
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*-----------------------------------------------------------------------------
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* PLL1_Q | 2
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*-----------------------------------------------------------------------------
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* PLL1_R | 2
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*-----------------------------------------------------------------------------
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* PLL1_FRACN | 0
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*-----------------------------------------------------------------------------
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* PLL2_SRC | No clock
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*-----------------------------------------------------------------------------
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* PLL2_M | Prescaler disabled
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*-----------------------------------------------------------------------------
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* PLL2_N | 129
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*-----------------------------------------------------------------------------
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* PLL2_P | 2
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*-----------------------------------------------------------------------------
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* PLL2_Q | 2
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*-----------------------------------------------------------------------------
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* PLL2_R | 2
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*-----------------------------------------------------------------------------
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* PLL2_FRACN | 0
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*-----------------------------------------------------------------------------
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* PLL3_SRC | No clock
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*-----------------------------------------------------------------------------
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* PLL3_M | Prescaler disabled
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*-----------------------------------------------------------------------------
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* PLL3_N | 129
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*-----------------------------------------------------------------------------
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* PLL3_P | 2
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*-----------------------------------------------------------------------------
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* PLL3_Q | 2
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*-----------------------------------------------------------------------------
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* PLL3_R | 2
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*-----------------------------------------------------------------------------
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* PLL3_FRACN | 0
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*-----------------------------------------------------------------------------
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*=============================================================================
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup STM32H5xx_system
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* @{
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*/
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/** @addtogroup STM32H5xx_System_Private_Includes
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* @{
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*/
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#include "stm32h5xx.h"
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE (25000000UL) /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (CSI_VALUE)
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#define CSI_VALUE (4000000UL) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE (64000000UL) /*!< Value of the Internal oscillator in Hz */
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#endif /* HSI_VALUE */
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 64000000U;
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32H5xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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uint32_t reg_opsr;
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set HSION bit */
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RCC->CR = RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR1 = 0U;
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RCC->CFGR2 = 0U;
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/* Reset HSEON, HSECSSON, HSEBYP, HSEEXT, HSIDIV, HSIKERON, CSION, CSIKERON, HSI48 and PLLxON bits */
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#if defined(RCC_CR_PLL3ON)
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RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
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RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
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#else
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RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_HSECSSON | RCC_CR_HSEBYP | RCC_CR_HSEEXT | RCC_CR_HSIDIV | RCC_CR_HSIKERON | \
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RCC_CR_CSION | RCC_CR_CSIKERON |RCC_CR_HSI48ON | RCC_CR_PLL1ON | RCC_CR_PLL2ON);
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#endif
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/* Reset PLLxCFGR register */
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RCC->PLL1CFGR = 0U;
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RCC->PLL2CFGR = 0U;
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#if defined(RCC_CR_PLL3ON)
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RCC->PLL3CFGR = 0U;
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#endif /* RCC_CR_PLL3ON */
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x01010280U;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000U;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x01010280U;
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000U;
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#if defined(RCC_CR_PLL3ON)
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x01010280U;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000U;
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#endif /* RCC_CR_PLL3ON */
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/* Reset HSEBYP bit */
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RCC->CR &= ~(RCC_CR_HSEBYP);
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/* Disable all interrupts */
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RCC->CIER = 0U;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif /* VECT_TAB_SRAM */
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/* Check OPSR register to verify if there is an ongoing swap or option bytes update interrupted by a reset */
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reg_opsr = FLASH->OPSR & FLASH_OPSR_CODE_OP;
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if ((reg_opsr == FLASH_OPSR_CODE_OP) || (reg_opsr == (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1)))
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{
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/* Check FLASH Option Control Register access */
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if ((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != 0U)
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{
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/* Authorizes the Option Byte registers programming */
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FLASH->OPTKEYR = 0x08192A3BU;
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FLASH->OPTKEYR = 0x4C5D6E7FU;
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}
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/* Launch the option bytes change operation */
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FLASH->OPTCR |= FLASH_OPTCR_OPTSTART;
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/* Lock the FLASH Option Control Register access */
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FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
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}
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is CSI, SystemCoreClock will contain the CSI_VALUE(*)
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(**) or CSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) CSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSI_VALUE is a constant defined in stm32h5xx_hal.h file (default value
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* 64 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32h5xx_hal.h file (default value
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* 25 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
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float_t fracn1, pllvco;
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR1 & RCC_CFGR1_SWS)
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{
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case 0x00UL: /* HSI used as system clock source */
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SystemCoreClock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
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break;
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case 0x08UL: /* CSI used as system clock source */
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SystemCoreClock = CSI_VALUE;
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break;
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case 0x10UL: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x18UL: /* PLL1 used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
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pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos);
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pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
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switch (pllsource)
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{
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case 0x01UL: /* HSI used as PLL clock source */
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
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pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
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(fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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case 0x02UL: /* CSI used as PLL clock source */
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pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
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(fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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case 0x03UL: /* HSE used as PLL clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \
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(fracn1/(float_t)0x2000) +(float_t)1 );
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break;
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default: /* No clock sent to PLL*/
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pllvco = (float_t) 0U;
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break;
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}
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pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1P) >>RCC_PLL1DIVR_PLL1P_Pos) + 1U ) ;
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SystemCoreClock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
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break;
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default:
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SystemCoreClock = HSI_VALUE;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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