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添加Ble,以及修改了H5的一些基础配置

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MADAO-LUV
2025-06-08 22:31:55 +08:00
parent 6727ac58d0
commit a502e81566
420 changed files with 34802 additions and 2117 deletions
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300
Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_icache.h
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/**
******************************************************************************
* @file stm32h5xx_hal_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H5xx_HAL_ICACHE_H
#define STM32H5xx_HAL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
#if defined(ICACHE)
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup ICACHE
* @{
*/
/* Exported types -----------------------------------------------------------*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_Exported_Types ICACHE Exported Types
* @{
*/
/**
* @brief HAL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */
uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */
uint32_t Size; /*!< Configures the Region size.
This parameter can be a value of @ref ICACHE_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_Output_Burst_Type */
} ICACHE_RegionConfigTypeDef;
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_WaysSelection Ways selection
* @{
*/
#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_Monitor_Type Monitor type
* @{
*/
#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */
#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */
#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_Region Remapped Region number
* @{
*/
#define ICACHE_REGION_0 0U /*!< Region 0 */
#define ICACHE_REGION_1 1U /*!< Region 1 */
#define ICACHE_REGION_2 2U /*!< Region 2 */
#define ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_Region_Size Remapped Region size
* @{
*/
#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_Traffic_Route Remapped Traffic route
* @{
*/
#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type
* @{
*/
#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/** @defgroup ICACHE_Interrupts Interrupts
* @{
*/
#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
/** @defgroup ICACHE_Flags Flags
* @{
*/
#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */
#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */
#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management
* @brief macros to manage the specified ICACHE flags and interrupts.
* @{
*/
/** @brief Enable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Disable ICACHE interrupts.
* @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
*/
#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__))
/** @brief Check whether the specified ICACHE interrupt source is enabled or not.
* @param __INTERRUPT__ specifies the ICACHE interrupt source to check.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_IT_BUSYEND Busy end interrupt
* @arg @ref ICACHE_IT_ERROR Cache error interrupt
* @retval The state of __INTERRUPT__ (0 or 1).
*/
#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \
((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U)
/** @brief Check whether the selected ICACHE flag is set or not.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref ICACHE_FLAG_BUSY Busy flag
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
* @retval The state of __FLAG__ (0 or 1).
*/
#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U)
/** @brief Clear the selected ICACHE flags.
* @param __FLAG__ specifies the ICACHE flags to clear.
* This parameter can be any combination of the following values:
* @arg @ref ICACHE_FLAG_BUSYEND Busy end flag
* @arg @ref ICACHE_FLAG_ERROR Cache error flag
*/
#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__))
/**
* @}
*/
/**
* @}
*/
/* Exported functions -------------------------------------------------------*/
/** @addtogroup ICACHE_Exported_Functions
* @{
*/
/** @addtogroup ICACHE_Exported_Functions_Group1
* @brief Initialization and control functions
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_ICACHE_Enable(void);
HAL_StatusTypeDef HAL_ICACHE_Disable(void);
uint32_t HAL_ICACHE_IsEnabled(void);
HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode);
HAL_StatusTypeDef HAL_ICACHE_DeInit(void);
/******* Invalidate in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate(void);
/******* Invalidate in non-blocking mode (Interrupt) */
HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void);
/******* Wait for Invalidate complete in blocking mode (Polling) */
HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void);
/******* Performance instruction cache monitoring functions */
HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType);
HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType);
uint32_t HAL_ICACHE_Monitor_GetHitValue(void);
uint32_t HAL_ICACHE_Monitor_GetMissValue(void);
/**
* @}
*/
/** @addtogroup ICACHE_Exported_Functions_Group2
* @brief IRQ and callback functions
* @{
*/
/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */
void HAL_ICACHE_IRQHandler(void);
void HAL_ICACHE_InvalidateCompleteCallback(void);
void HAL_ICACHE_ErrorCallback(void);
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @addtogroup ICACHE_Exported_Functions_Group3
* @brief Memory remapped regions functions
* @{
*/
/******* Memory remapped regions functions */
HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig);
HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region);
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_ICACHE_H */

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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart.h Normal file
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Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_hal_uart_ex.h Normal file
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/**
******************************************************************************
* @file stm32h5xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32H5xx_HAL_UART_EX_H
#define STM32H5xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32h5xx_hal_def.h"
/** @addtogroup STM32H5xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#if defined(HAL_DMA_MODULE_ENABLED)
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
#endif /* HAL_DMA_MODULE_ENABLED */
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx))
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \
} \
else if((__HANDLE__)->Instance == UART7) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART7; \
} \
else if((__HANDLE__)->Instance == UART8) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART8; \
} \
else if((__HANDLE__)->Instance == UART9) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART9; \
} \
else if((__HANDLE__)->Instance == USART10) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART10; \
} \
else if((__HANDLE__)->Instance == USART11) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART11; \
} \
else if((__HANDLE__)->Instance == UART12) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART12; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
#elif (defined(STM32H523xx) || defined(STM32H533xx))
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \
} \
else if((__HANDLE__)->Instance == USART6) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
#else
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
(__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \
} \
else \
{ \
(__CLOCKSOURCE__) = 0U; \
} \
} while(0U)
#endif /* (defined(STM32H573xx) || defined(STM32H563xx) || defined(STM32H562xx) */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_HAL_UART_EX_H */

788
Drivers/STM32H5xx_HAL_Driver/Inc/stm32h5xx_ll_icache.h
View File

@@ -1,788 +0,0 @@
/**
******************************************************************************
* @file stm32h5xx_ll_icache.h
* @author MCD Application Team
* @brief Header file of ICACHE LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2023 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion ------------------------------------*/
#ifndef STM32H5xx_LL_ICACHE_H
#define STM32H5xx_LL_ICACHE_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes -----------------------------------------------------------------*/
#include "stm32h5xx.h"
/** @addtogroup STM32H5xx_LL_Driver
* @{
*/
#if defined(ICACHE)
/** @defgroup ICACHE_LL ICACHE
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure
* @{
*/
/**
* @brief LL ICACHE region configuration structure definition
*/
typedef struct
{
uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */
uint32_t RemapAddress; /*!< Configures the remap address to be remapped */
uint32_t Size; /*!< Configures the region size.
This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */
uint32_t TrafficRoute; /*!< Selects the traffic route.
This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */
uint32_t OutputBurstType; /*!< Selects the output burst type.
This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */
} LL_ICACHE_RegionTypeDef;
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/* Exported constants -------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants
* @{
*/
/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection
* @{
*/
#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */
#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type
* @{
*/
#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */
#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */
#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_ReadReg function
* @{
*/
#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */
#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */
#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines
* @brief Flags defines which can be used with LL_ICACHE_WriteReg function
* @{
*/
#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */
#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_IT IT Defines
* @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions
* @{
*/
#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */
#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_EC_Region Remapped Region number
* @{
*/
#define LL_ICACHE_REGION_0 0U /*!< Region 0 */
#define LL_ICACHE_REGION_1 1U /*!< Region 1 */
#define LL_ICACHE_REGION_2 2U /*!< Region 2 */
#define LL_ICACHE_REGION_3 3U /*!< Region 3 */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size
* @{
*/
#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */
#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */
#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */
#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */
#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */
#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */
#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route
* @{
*/
#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */
#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */
/**
* @}
*/
/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type
* @{
*/
#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */
#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */
/**
* @}
*/
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/* Exported macros ----------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros
* @{
*/
/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros
* @{
*/
/**
* @brief Write a value in ICACHE register
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__))
/**
* @brief Read a value in ICACHE register
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__)
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions
* @{
*/
/** @defgroup ICACHE_LL_EF_Configuration Configuration
* @{
*/
/**
* @brief Enable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Enable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Enable(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Disable the ICACHE.
* @rmtoll CR EN LL_ICACHE_Disable
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Disable(void)
{
CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);
}
/**
* @brief Return if ICACHE is enabled or not.
* @rmtoll CR EN LL_ICACHE_IsEnabled
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void)
{
return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL);
}
/**
* @brief Select the ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_SetMode
* @param Mode This parameter can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode)
{
MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode);
}
/**
* @brief Get the selected ICACHE operating mode.
* @rmtoll CR WAYSEL LL_ICACHE_GetMode
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_1WAY
* @arg @ref LL_ICACHE_2WAYS
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void)
{
return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL));
}
/**
* @brief Invalidate the ICACHE.
* @note Until the BSYEND flag is set, the cache is bypassed.
* @rmtoll CR CACHEINV LL_ICACHE_Invalidate
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_Invalidate(void)
{
SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_Monitors Monitors
* @{
*/
/**
* @brief Enable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_EnableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors)
{
SET_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Disable the hit/miss monitor(s).
* @rmtoll CR HITMEN LL_ICACHE_DisableMonitors
* @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors)
{
CLEAR_BIT(ICACHE->CR, Monitors);
}
/**
* @brief Check if the monitor(s) is(are) enabled or disabled.
* @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors
* @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval State of parameter value (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors)
{
return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL);
}
/**
* @brief Reset the hit/miss monitor(s).
* @rmtoll CR HITMRST LL_ICACHE_ResetMonitors
* @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors
* @param Monitors This parameter can be one or a combination of the following values:
* @arg @ref LL_ICACHE_MONITOR_HIT
* @arg @ref LL_ICACHE_MONITOR_MISS
* @arg @ref LL_ICACHE_MONITOR_ALL
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors)
{
/* Reset */
SET_BIT(ICACHE->CR, (Monitors << 2U));
/* Release reset */
CLEAR_BIT(ICACHE->CR, (Monitors << 2U));
}
/**
* @brief Get the Hit monitor.
* @note Upon reaching the 32-bit maximum value, hit monitor does not wrap.
* @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void)
{
return (ICACHE->HMONR);
}
/**
* @brief Get the Miss monitor.
* @note Upon reaching the 16-bit maximum value, miss monitor does not wrap.
* @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor
* @retval Value between Min_Data=0 and Max_Data=0xFFFF
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void)
{
return (ICACHE->MMONR);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_IT_Management IT_Management
* @{
*/
/**
* @brief Enable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Disable BSYEND interrupt.
* @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);
}
/**
* @brief Check if the BSYEND Interrupt is enabled or disabled.
* @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL);
}
/**
* @brief Enable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void)
{
SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Disable ERR interrupt.
* @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void)
{
CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);
}
/**
* @brief Check if the ERR Interrupt is enabled or disabled.
* @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void)
{
return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL);
}
/**
* @}
*/
/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management
* @{
*/
/**
* @brief Indicate the status of an ongoing operation flag.
* @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an operation end flag.
* @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL);
}
/**
* @brief Indicate the status of an error flag.
* @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void)
{
return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL);
}
/**
* @brief Clear busy end of operation flag.
* @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);
}
/**
* @brief Clear error flag.
* @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void)
{
WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);
}
/**
* @}
*/
#if defined(ICACHE_CRRx_REN)
/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management
* @{
*/
/**
* @brief Enable the remapped memory region.
* @note The region must have been already configured.
* @rmtoll CRRx REN LL_ICACHE_EnableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region)
{
SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Disable the remapped memory region.
* @rmtoll CRRx REN LL_ICACHE_DisableRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region)
{
CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN);
}
/**
* @brief Return if remapped memory region is enabled or not.
* @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL);
}
/**
* @brief Select the memory remapped region base address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Alias address in the Code region
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U));
}
/**
* @brief Get the memory remapped region base address.
* @note The base address is the alias in the Code region.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Alias address in the Code region
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_BASEADDR) << 21U);
}
/**
* @brief Select the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Address Memory address to remap
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos));
}
/**
* @brief Get the memory remapped region address.
* @note The useful bits depends on RSIZE as described in the Reference Manual.
* @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Address Remapped memory address
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region)
{
return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U);
}
/**
* @brief Select the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Size This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos));
}
/**
* @brief Get the selected the memory remapped region size.
* @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_REGIONSIZE_2MB
* @arg @ref LL_ICACHE_REGIONSIZE_4MB
* @arg @ref LL_ICACHE_REGIONSIZE_8MB
* @arg @ref LL_ICACHE_REGIONSIZE_16MB
* @arg @ref LL_ICACHE_REGIONSIZE_32MB
* @arg @ref LL_ICACHE_REGIONSIZE_64MB
* @arg @ref LL_ICACHE_REGIONSIZE_128MB
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos);
}
/**
* @brief Select the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Type This parameter can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST, Type);
}
/**
* @brief Get the selected the memory remapped region output burst type.
* @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP
* @arg @ref LL_ICACHE_OUTPUT_BURST_INCR
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_HBURST));
}
/**
* @brief Select the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @param Port This parameter can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
* @retval None
*/
__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port)
{
MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL, Port);
}
/**
* @brief Get the selected the memory remapped region cache master port.
* @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort
* @param Region This parameter can be one of the following values:
* @arg @ref LL_ICACHE_REGION_0
* @arg @ref LL_ICACHE_REGION_1
* @arg @ref LL_ICACHE_REGION_2
* @arg @ref LL_ICACHE_REGION_3
* @retval Returned value can be one of the following values:
* @arg @ref LL_ICACHE_MASTER1_PORT
* @arg @ref LL_ICACHE_MASTER2_PORT
*/
__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region)
{
return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \
ICACHE_CRRx_MSTSEL));
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions
* @{
*/
void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
#endif /* ICACHE_CRRx_REN */
/**
* @}
*/
/**
* @}
*/
#endif /* ICACHE */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32H5xx_LL_ICACHE_H */

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