generated from Template/H563ZI-HAL-CMake-Template
开启 ThreadX
This commit is contained in:
643
Core/Src/tx_initialize_low_level.S
Normal file
643
Core/Src/tx_initialize_low_level.S
Normal file
@@ -0,0 +1,643 @@
|
||||
|
||||
// by default AzureRTOS is configured to use static byte pool for
|
||||
// allocation, in case dynamic allocation is to be used, uncomment
|
||||
// the define below and update the linker files to define the following symbols
|
||||
// EWARM toolchain:
|
||||
// place in RAM_region { last section FREE_MEM};
|
||||
// MDK-ARM toolchain;
|
||||
// either define the RW_IRAM1 region in the ".sct" file or modify this file by referring to the correct memory region.
|
||||
// LDR r1, =|Image$$RW_IRAM1$$ZI$$Limit|
|
||||
// STM32CubeIDE toolchain:
|
||||
// ._threadx_heap :
|
||||
// {
|
||||
// . = ALIGN(8);
|
||||
// __RAM_segment_used_end__ = .;
|
||||
// . = . + 64K;
|
||||
// . = ALIGN(8);
|
||||
// } >RAM_D1 AT> RAM_D1
|
||||
// The simplest way to provide memory for ThreadX is to define a new section, see ._threadx_heap above.
|
||||
// In the example above the ThreadX heap size is set to 64KBytes.
|
||||
// The ._threadx_heap must be located between the .bss and the ._user_heap_stack sections in the linker script.
|
||||
// Caution: Make sure that ThreadX does not need more than the provided heap memory (64KBytes in this example).
|
||||
// Read more in STM32CubeIDE User Guide, chapter: "Linker script".
|
||||
|
||||
//#define USE_DYNAMIC_MEMORY_ALLOCATION
|
||||
|
||||
#if defined (__clang__)
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
SYSTEM_CLOCK = 250000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M33/AC6 */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
.type _tx_initialize_low_level, function
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =Image$$RW_IRAM1$$ZI$$Limit // Build first free address
|
||||
ADD r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
#endif
|
||||
|
||||
/* Setup Vector Table Offset Register. */
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] // Set vector table address
|
||||
|
||||
/* Enable the cycle count register. */
|
||||
LDR r0, =0xE0001000 // Build address of DWT register
|
||||
LDR r1, [r0] // Pickup the current value
|
||||
ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =__Vectors // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Configure SysTick. */
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOV r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
BX lr
|
||||
// }
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
.type __tx_BadHandler, function
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
.type __tx_IntHandler, function
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
.type SysTick_Handler, function
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
BL _tx_timer_interrupt
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX LR
|
||||
// }
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_NMIHandler
|
||||
.thumb_func
|
||||
.type __tx_NMIHandler, function
|
||||
__tx_NMIHandler:
|
||||
B __tx_NMIHandler
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_DBGHandler
|
||||
.thumb_func
|
||||
.type __tx_DBGHandler, function
|
||||
__tx_DBGHandler:
|
||||
B __tx_DBGHandler
|
||||
|
||||
.end
|
||||
#endif
|
||||
|
||||
#if defined(__IAR_SYSTEMS_ASM__)
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
;/* */
|
||||
;/* This software is licensed under the Microsoft Software License */
|
||||
;/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
;/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
;/* and in the root directory of this software. */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;/** */
|
||||
;/** ThreadX Component */
|
||||
;/** */
|
||||
;/** Initialize */
|
||||
;/** */
|
||||
;/**************************************************************************/
|
||||
;/**************************************************************************/
|
||||
;
|
||||
;
|
||||
EXTERN _tx_thread_system_stack_ptr
|
||||
EXTERN _tx_initialize_unused_memory
|
||||
EXTERN _tx_timer_interrupt
|
||||
EXTERN _tx_execution_isr_enter
|
||||
EXTERN _tx_execution_isr_exit
|
||||
EXTERN __vector_table
|
||||
;
|
||||
;
|
||||
SYSTEM_CLOCK EQU 250000000
|
||||
SYSTICK_CYCLES EQU ((SYSTEM_CLOCK / 100) -1)
|
||||
;
|
||||
;
|
||||
|
||||
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
|
||||
RSEG FREE_MEM:DATA
|
||||
PUBLIC __tx_free_memory_start
|
||||
__tx_free_memory_start
|
||||
DS32 4
|
||||
#endif
|
||||
;
|
||||
;
|
||||
SECTION `.text`:CODE:NOROOT(2)
|
||||
THUMB
|
||||
|
||||
;/**************************************************************************/
|
||||
;/* */
|
||||
;/* FUNCTION RELEASE */
|
||||
;/* */
|
||||
;/* _tx_initialize_low_level Cortex-M33/IAR */
|
||||
;/* 6.1 */
|
||||
;/* AUTHOR */
|
||||
;/* */
|
||||
;/* Scott Larson, Microsoft Corporation */
|
||||
;/* */
|
||||
;/* DESCRIPTION */
|
||||
;/* */
|
||||
;/* This function is responsible for any low-level processor */
|
||||
;/* initialization, including setting up interrupt vectors, setting */
|
||||
;/* up a periodic timer interrupt source, saving the system stack */
|
||||
;/* pointer for use in ISR processing later, and finding the first */
|
||||
;/* available RAM memory address for tx_application_define. */
|
||||
;/* */
|
||||
;/* INPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* OUTPUT */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLS */
|
||||
;/* */
|
||||
;/* None */
|
||||
;/* */
|
||||
;/* CALLED BY */
|
||||
;/* */
|
||||
;/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
;/* */
|
||||
;/* RELEASE HISTORY */
|
||||
;/* */
|
||||
;/* DATE NAME DESCRIPTION */
|
||||
;/* */
|
||||
;/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
;/* */
|
||||
;/**************************************************************************/
|
||||
;VOID _tx_initialize_low_level(VOID)
|
||||
;{
|
||||
PUBLIC _tx_initialize_low_level
|
||||
_tx_initialize_low_level:
|
||||
;
|
||||
; /* Disable interrupts during ThreadX initialization. */
|
||||
;
|
||||
CPSID i
|
||||
;
|
||||
; /* Set base of available memory to end of non-initialised RAM area. */
|
||||
;
|
||||
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
|
||||
LDR r0, =_tx_initialize_unused_memory ; Build address of unused memory pointer
|
||||
LDR r1, =__tx_free_memory_start ; Build first free address
|
||||
STR r1, [r0] ; Setup first unused memory pointer
|
||||
#endif
|
||||
;
|
||||
; /* Setup Vector Table Offset Register. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =__vector_table ; Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] ; Set vector table address
|
||||
;
|
||||
; /* Enable the cycle count register. */
|
||||
;
|
||||
; LDR r0, =0xE0001000 ; Build address of DWT register
|
||||
; LDR r1, [r0] ; Pickup the current value
|
||||
; ORR r1, r1, #1 ; Set the CYCCNTENA bit
|
||||
; STR r1, [r0] ; Enable the cycle count register
|
||||
;
|
||||
; /* Set system stack pointer from vector value. */
|
||||
;
|
||||
LDR r0, =_tx_thread_system_stack_ptr ; Build address of system stack pointer
|
||||
LDR r1, =__vector_table ; Pickup address of vector table
|
||||
LDR r1, [r1] ; Pickup reset stack pointer
|
||||
STR r1, [r0] ; Save system stack pointer
|
||||
;
|
||||
; /* Configure SysTick. */
|
||||
;
|
||||
MOV r0, #0xE000E000 ; Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] ; Setup SysTick Reload Value
|
||||
MOV r1, #0x7 ; Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] ; Setup SysTick Control
|
||||
;
|
||||
; /* Configure handler priorities. */
|
||||
;
|
||||
LDR r1, =0x00000000 ; Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] ; Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 ; SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] ; Setup System Handlers 8-11 Priority Registers
|
||||
; Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 ; SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] ; Setup System Handlers 12-15 Priority Registers
|
||||
; Note: PnSV must be lowest priority, which is 0xFF
|
||||
;
|
||||
; /* Return to caller. */
|
||||
;
|
||||
BX lr
|
||||
;}
|
||||
;
|
||||
;
|
||||
;/* Define shells for each of the unused vectors. */
|
||||
;
|
||||
PUBLIC __tx_BadHandler
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
PUBLIC __tx_IntHandler
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX lr
|
||||
// }
|
||||
|
||||
PUBLIC __tx_SysTickHandler
|
||||
PUBLIC SysTick_Handler
|
||||
SysTick_Handler:
|
||||
__tx_SysTickHandler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
BL _tx_timer_interrupt
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX lr
|
||||
// }
|
||||
|
||||
PUBLIC __tx_NMIHandler
|
||||
__tx_NMIHandler:
|
||||
B __tx_NMIHandler
|
||||
|
||||
PUBLIC __tx_DBGHandler
|
||||
__tx_DBGHandler:
|
||||
B __tx_DBGHandler
|
||||
|
||||
END
|
||||
#endif
|
||||
|
||||
#if (defined(__GNUC__) && !defined(__clang__))
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* Copyright (c) Microsoft Corporation. All rights reserved. */
|
||||
/* */
|
||||
/* This software is licensed under the Microsoft Software License */
|
||||
/* Terms for Microsoft Azure RTOS. Full text of the license can be */
|
||||
/* found in the LICENSE file at https://aka.ms/AzureRTOS_EULA */
|
||||
/* and in the root directory of this software. */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
/** */
|
||||
/** ThreadX Component */
|
||||
/** */
|
||||
/** Initialize */
|
||||
/** */
|
||||
/**************************************************************************/
|
||||
/**************************************************************************/
|
||||
|
||||
SYSTEM_CLOCK = 250000000
|
||||
SYSTICK_CYCLES = ((SYSTEM_CLOCK / 100) -1)
|
||||
|
||||
/**************************************************************************/
|
||||
/* */
|
||||
/* FUNCTION RELEASE */
|
||||
/* */
|
||||
/* _tx_initialize_low_level Cortex-M33/GNU */
|
||||
/* 6.1 */
|
||||
/* AUTHOR */
|
||||
/* */
|
||||
/* Scott Larson, Microsoft Corporation */
|
||||
/* */
|
||||
/* DESCRIPTION */
|
||||
/* */
|
||||
/* This function is responsible for any low-level processor */
|
||||
/* initialization, including setting up interrupt vectors, setting */
|
||||
/* up a periodic timer interrupt source, saving the system stack */
|
||||
/* pointer for use in ISR processing later, and finding the first */
|
||||
/* available RAM memory address for tx_application_define. */
|
||||
/* */
|
||||
/* INPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* OUTPUT */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLS */
|
||||
/* */
|
||||
/* None */
|
||||
/* */
|
||||
/* CALLED BY */
|
||||
/* */
|
||||
/* _tx_initialize_kernel_enter ThreadX entry function */
|
||||
/* */
|
||||
/* RELEASE HISTORY */
|
||||
/* */
|
||||
/* DATE NAME DESCRIPTION */
|
||||
/* */
|
||||
/* 09-30-2020 Scott Larson Initial Version 6.1 */
|
||||
/* */
|
||||
/**************************************************************************/
|
||||
// VOID _tx_initialize_low_level(VOID)
|
||||
// {
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global _tx_initialize_low_level
|
||||
.thumb_func
|
||||
.type _tx_initialize_low_level, function
|
||||
_tx_initialize_low_level:
|
||||
|
||||
/* Disable interrupts during ThreadX initialization. */
|
||||
CPSID i
|
||||
|
||||
/* Set base of available memory to end of non-initialised RAM area. */
|
||||
#ifdef USE_DYNAMIC_MEMORY_ALLOCATION
|
||||
LDR r0, =_tx_initialize_unused_memory // Build address of unused memory pointer
|
||||
LDR r1, =__RAM_segment_used_end__ // Build first free address
|
||||
ADD r1, r1, #4 //
|
||||
STR r1, [r0] // Setup first unused memory pointer
|
||||
#endif
|
||||
/* Setup Vector Table Offset Register. */
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =g_pfnVectors // Pickup address of vector table
|
||||
STR r1, [r0, #0xD08] // Set vector table address
|
||||
|
||||
/* Enable the cycle count register. */
|
||||
LDR r0, =0xE0001000 // Build address of DWT register
|
||||
LDR r1, [r0] // Pickup the current value
|
||||
ORR r1, r1, #1 // Set the CYCCNTENA bit
|
||||
STR r1, [r0] // Enable the cycle count register
|
||||
|
||||
/* Set system stack pointer from vector value. */
|
||||
LDR r0, =_tx_thread_system_stack_ptr // Build address of system stack pointer
|
||||
LDR r1, =g_pfnVectors // Pickup address of vector table
|
||||
LDR r1, [r1] // Pickup reset stack pointer
|
||||
STR r1, [r0] // Save system stack pointer
|
||||
|
||||
/* Configure SysTick. */
|
||||
MOV r0, #0xE000E000 // Build address of NVIC registers
|
||||
LDR r1, =SYSTICK_CYCLES
|
||||
STR r1, [r0, #0x14] // Setup SysTick Reload Value
|
||||
MOV r1, #0x7 // Build SysTick Control Enable Value
|
||||
STR r1, [r0, #0x10] // Setup SysTick Control
|
||||
|
||||
/* Configure handler priorities. */
|
||||
LDR r1, =0x00000000 // Rsrv, UsgF, BusF, MemM
|
||||
STR r1, [r0, #0xD18] // Setup System Handlers 4-7 Priority Registers
|
||||
|
||||
LDR r1, =0xFF000000 // SVCl, Rsrv, Rsrv, Rsrv
|
||||
STR r1, [r0, #0xD1C] // Setup System Handlers 8-11 Priority Registers
|
||||
// Note: SVC must be lowest priority, which is 0xFF
|
||||
|
||||
LDR r1, =0x40FF0000 // SysT, PnSV, Rsrv, DbgM
|
||||
STR r1, [r0, #0xD20] // Setup System Handlers 12-15 Priority Registers
|
||||
// Note: PnSV must be lowest priority, which is 0xFF
|
||||
|
||||
/* Return to caller. */
|
||||
BX lr
|
||||
// }
|
||||
|
||||
/* Define shells for each of the unused vectors. */
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_BadHandler
|
||||
.thumb_func
|
||||
.type __tx_BadHandler, function
|
||||
__tx_BadHandler:
|
||||
B __tx_BadHandler
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_IntHandler
|
||||
.thumb_func
|
||||
.type __tx_IntHandler, function
|
||||
__tx_IntHandler:
|
||||
// VOID InterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
/* Do interrupt handler work here */
|
||||
/* .... */
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX lr
|
||||
// }
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global SysTick_Handler
|
||||
.thumb_func
|
||||
.type SysTick_Handler, function
|
||||
SysTick_Handler:
|
||||
// VOID TimerInterruptHandler (VOID)
|
||||
// {
|
||||
PUSH {r0,lr} // Save LR (and dummy r0 to maintain stack alignment)
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_enter // Call the ISR enter function
|
||||
#endif
|
||||
BL _tx_timer_interrupt
|
||||
#if (defined(TX_ENABLE_EXECUTION_CHANGE_NOTIFY) || defined(TX_EXECUTION_PROFILE_ENABLE))
|
||||
BL _tx_execution_isr_exit // Call the ISR exit function
|
||||
#endif
|
||||
POP {r0,lr}
|
||||
BX lr
|
||||
// }
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_NMIHandler
|
||||
.thumb_func
|
||||
.type __tx_NMIHandler, function
|
||||
__tx_NMIHandler:
|
||||
B __tx_NMIHandler
|
||||
|
||||
.section .text
|
||||
.balign 4
|
||||
.syntax unified
|
||||
.eabi_attribute Tag_ABI_align_preserved, 1
|
||||
.global __tx_DBGHandler
|
||||
.thumb_func
|
||||
.type __tx_DBGHandler, function
|
||||
__tx_DBGHandler:
|
||||
B __tx_DBGHandler
|
||||
|
||||
.end
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user